From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: YunQiang Su <yunqiang.su@cipunited.com>
Cc: gcc-patches@gcc.gnu.org, Jeff Law <jeffreyalaw@gmail.com>,
syq@debian.org
Subject: Re: [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU
Date: Sun, 10 Apr 2022 18:41:43 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.21.2204101822230.47162@angie.orcam.me.uk> (raw)
In-Reply-To: <20220315065156.856767-1-yunqiang.su@cipunited.com>
On Tue, 15 Mar 2022, YunQiang Su wrote:
> If MIPS MCU extension is enable, the IPL section in Cause and Status
> registers has been expand to 8bit instead of 6bit.
>
> In Cause: the bits are 10-17.
> In Status: the bits are 10-16 and 18.
>
> MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61.
I can see you have committed this change, but I cannot see an approval
posted to the mailing list. Who has approved your change?
> diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
> index a1c4b437cd4..91e1e964f94 100644
> --- a/gcc/config/mips/mips.cc
> +++ b/gcc/config/mips/mips.cc
> @@ -12254,10 +12254,22 @@ mips_expand_prologue (void)
> /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
> if (!cfun->machine->keep_interrupts_masked_p
> && cfun->machine->int_mask == INT_MASK_EIC)
> - emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
> - GEN_INT (6),
> + {
> + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
> + TARGET_MCU ? GEN_INT (7) : GEN_INT (6),
> GEN_INT (SR_IPL),
> gen_rtx_REG (SImode, K0_REG_NUM)));
> + if (TARGET_MCU)
> + {
> + emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
> + gen_rtx_REG (SImode, K0_REG_NUM),
> + GEN_INT (7)));
> + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
> + GEN_INT (1),
> + GEN_INT (SR_IPL+8),
> + gen_rtx_REG (SImode, K0_REG_NUM)));
> + }
> + }
While code generation has been corrected your change has code formatting
issues which should have been addressed before committing. A test case
should have been made too.
Maciej
prev parent reply other threads:[~2022-04-10 17:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 3:29 [PATCH] MIPS: use 8bit for IPL in Cause register YunQiang Su
2022-01-26 18:40 ` Maciej W. Rozycki
2022-02-09 3:18 ` [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU YunQiang Su
2022-02-12 3:54 ` Jeff Law
2022-02-12 8:47 ` Maciej W. Rozycki
2022-03-15 7:00 ` YunQiang Su
2022-03-15 6:51 ` [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers " YunQiang Su
2022-04-10 17:41 ` Maciej W. Rozycki [this message]
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