From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from angie.orcam.me.uk (angie.orcam.me.uk [IPv6:2001:4190:8020::34]) by sourceware.org (Postfix) with ESMTP id 62F493856DE8 for ; Sun, 10 Apr 2022 17:41:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 62F493856DE8 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=orcam.me.uk Authentication-Results: sourceware.org; spf=none smtp.mailfrom=orcam.me.uk Received: by angie.orcam.me.uk (Postfix, from userid 500) id 9219192009C; Sun, 10 Apr 2022 19:41:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id 83A9892009B; Sun, 10 Apr 2022 18:41:43 +0100 (BST) Date: Sun, 10 Apr 2022 18:41:43 +0100 (BST) From: "Maciej W. Rozycki" To: YunQiang Su cc: gcc-patches@gcc.gnu.org, Jeff Law , syq@debian.org Subject: Re: [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU In-Reply-To: <20220315065156.856767-1-yunqiang.su@cipunited.com> Message-ID: References: <5028ca31-8f20-f26b-13cc-8b3ea6b7ffb8@gmail.com> <20220315065156.856767-1-yunqiang.su@cipunited.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-3495.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_INFOUSMEBIZ, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Apr 2022 17:41:46 -0000 On Tue, 15 Mar 2022, YunQiang Su wrote: > If MIPS MCU extension is enable, the IPL section in Cause and Status > registers has been expand to 8bit instead of 6bit. > > In Cause: the bits are 10-17. > In Status: the bits are 10-16 and 18. > > MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61. I can see you have committed this change, but I cannot see an approval posted to the mailing list. Who has approved your change? > diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc > index a1c4b437cd4..91e1e964f94 100644 > --- a/gcc/config/mips/mips.cc > +++ b/gcc/config/mips/mips.cc > @@ -12254,10 +12254,22 @@ mips_expand_prologue (void) > /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ > if (!cfun->machine->keep_interrupts_masked_p > && cfun->machine->int_mask == INT_MASK_EIC) > - emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), > - GEN_INT (6), > + { > + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), > + TARGET_MCU ? GEN_INT (7) : GEN_INT (6), > GEN_INT (SR_IPL), > gen_rtx_REG (SImode, K0_REG_NUM))); > + if (TARGET_MCU) > + { > + emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), > + gen_rtx_REG (SImode, K0_REG_NUM), > + GEN_INT (7))); > + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), > + GEN_INT (1), > + GEN_INT (SR_IPL+8), > + gen_rtx_REG (SImode, K0_REG_NUM))); > + } > + } While code generation has been corrected your change has code formatting issues which should have been addressed before committing. A test case should have been made too. Maciej