From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=Z3Ow=6Y=orcam.me.uk=macro@sourceware.org>
Received: from angie.orcam.me.uk (angie.orcam.me.uk [IPv6:2001:4190:8020::34])
	by sourceware.org (Postfix) with ESMTP id C4FA03858C54
	for <gcc-patches@gcc.gnu.org>; Tue, 28 Feb 2023 16:42:29 +0000 (GMT)
DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C4FA03858C54
Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=orcam.me.uk
Authentication-Results: sourceware.org; spf=none smtp.mailfrom=orcam.me.uk
Received: by angie.orcam.me.uk (Postfix, from userid 500)
	id 017BB92009C; Tue, 28 Feb 2023 17:42:26 +0100 (CET)
Received: from localhost (localhost [127.0.0.1])
	by angie.orcam.me.uk (Postfix) with ESMTP id EF9F592009B;
	Tue, 28 Feb 2023 16:42:26 +0000 (GMT)
Date: Tue, 28 Feb 2023 16:42:26 +0000 (GMT)
From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Jeff Law <jeffreyalaw@gmail.com>
cc: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org, 
    Kito Cheng <kito.cheng@gmail.com>, 
    Christoph Muellner <christoph.muellner@vrull.eu>, 
    Palmer Dabbelt <palmer@rivosinc.com>, Andrew Waterman <andrew@sifive.com>, 
    Vineet Gupta <vineetg@rivosinc.com>
Subject: Re: [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero
 instructions
In-Reply-To: <90ef6883-397b-8e6a-1ecb-3663fe854ac7@gmail.com>
Message-ID: <alpine.DEB.2.21.2302281637440.40278@angie.orcam.me.uk>
References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> <20230210224150.2801962-9-philipp.tomsich@vrull.eu> <90ef6883-397b-8e6a-1ecb-3663fe854ac7@gmail.com>
User-Agent: Alpine 2.21 (DEB 202 2017-01-01)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
X-Spam-Status: No, score=-3488.9 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_INFOUSMEBIZ,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org
List-Id: <gcc-patches.gcc.gnu.org>

On Mon, 13 Feb 2023, Jeff Law via Gcc-patches wrote:

> 3. The canaonical conditional-zero-or-value assumes the target can do a
> generic SEQ/SNE of two register values.  As you know, on RISC-V we have
> SEQZ/SNEZ.  So we've added another fallback path to handle that case in
> noce_emit_condzero.  You subtract the two values, then you can do an SEQZ/SNEZ
> on the result.

 NB these machine operations are identical to MIPSr6 SELEQZ and SELNEZ 
instructions (cf. ISA_HAS_SEL), so why can't we just duplicate what the 
MIPS backend does?  Or did the MIPS backend do something wrong here?

  Maciej