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From: Marc Glisse <marc.glisse@inria.fr>
To: Christophe Lyon <christophe.lyon@linaro.org>
Cc: Richard Biener <richard.guenther@gmail.com>,
	 GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: VEC_COND_EXPR optimizations v2
Date: Thu, 6 Aug 2020 20:07:57 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.23.453.2008061937220.8021@stedding.saclay.inria.fr> (raw)
In-Reply-To: <CAKdteOYyK+QHhmiDMHbh-a-t-ix7U9ApWVabs2h3_gJz8zZ5Zg@mail.gmail.com>

On Thu, 6 Aug 2020, Christophe Lyon wrote:

>> Was I on the right track configuring with
>> --target=arm-none-linux-gnueabihf --with-cpu=cortex-a9
>> --with-fpu=neon-fp16
>> then compiling without any special option?
>
> Maybe you also need --with-float=hard, I don't remember if it's
> implied by the 'hf' target suffix

Thanks! That's what I was missing to reproduce the issue. Now I can
reproduce it with just

typedef unsigned int vec __attribute__((vector_size(16)));
typedef int vi __attribute__((vector_size(16)));
vi f(vec a,vec b){
     return a==5 | b==7;
}

with -fdisable-tree-forwprop1 -fdisable-tree-forwprop2 -fdisable-tree-forwprop3 -O1

   _1 = a_5(D) == { 5, 5, 5, 5 };
   _3 = b_6(D) == { 7, 7, 7, 7 };
   _9 = _1 | _3;
   _7 = .VCOND (_9, { 0, 0, 0, 0 }, { -1, -1, -1, -1 }, { 0, 0, 0, 0 }, 107);

we fail to expand the equality comparison (expand_vec_cmp_expr_p returns
false), while with -fdisable-tree-forwprop4 we do manage to expand

   _2 = .VCONDU (a_5(D), { 5, 5, 5, 5 }, { -1, -1, -1, -1 }, { 0, 0, 0, 0 }, 112);

It doesn't make much sense to me that we can expand the more complicated
form and not the simpler form of the same operation (both compare a to 5
and produce a vector of -1 or 0 of the same size), especially when the
target has an instruction (vceq) that does just what we want.

Introducing boolean vectors was fine, but I think they should be real 
types, that we can operate on, not be forced to appear only as the first 
argument of a vcond.

I can think of 2 natural ways to improve things: either implement vector 
comparisons in the ARM backend (possibly by forwarding to their existing 
code for vcond), or in the generic expansion code try using vcond if the 
direct comparison opcode is not provided.

We can temporarily revert my patch, but I would like it to be temporary. 
Since aarch64 seems to handle the same code just fine, maybe someone who 
knows arm could copy the relevant code over?

Does my message make sense, do people have comments?

-- 
Marc Glisse

  reply	other threads:[~2020-08-06 18:07 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-30  7:49 VEC_COND_EXPR optimizations Marc Glisse
2020-07-31 11:18 ` Richard Sandiford
2020-07-31 11:38   ` Marc Glisse
2020-07-31 11:43     ` Richard Biener
2020-07-31 11:57       ` Marc Glisse
2020-07-31 12:50     ` Richard Sandiford
2020-07-31 12:59       ` Richard Biener
2020-07-31 13:01       ` Marc Glisse
2020-07-31 13:13         ` Marc Glisse
2020-07-31 11:35 ` Richard Biener
2020-07-31 11:39   ` Richard Biener
2020-07-31 11:47     ` Richard Biener
2020-07-31 12:08       ` Richard Biener
2020-07-31 12:12       ` Marc Glisse
2020-08-05 13:32 ` VEC_COND_EXPR optimizations v2 Marc Glisse
2020-08-05 14:24   ` Richard Biener
2020-08-06  8:17     ` Christophe Lyon
2020-08-06  9:05       ` Marc Glisse
2020-08-06 11:25         ` Christophe Lyon
2020-08-06 11:42           ` Marc Glisse
2020-08-06 12:00             ` Christophe Lyon
2020-08-06 18:07               ` Marc Glisse [this message]
2020-08-07  6:38                 ` Richard Biener
2020-08-07  8:33                   ` Marc Glisse
2020-08-07  8:47                     ` Richard Biener
2020-08-07 12:15                       ` Marc Glisse
2020-08-07 13:04                         ` Richard Biener
2020-08-06 10:29       ` Richard Biener
2020-08-06 11:11         ` Marc Glisse

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