From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: "Fu, Chao-Ying" <fu@mips.com>
Cc: Daniel Jacobowitz <drow@false.org>,
gcc-patches@gcc.gnu.org,
Richard Sandiford <rdsandiford@googlemail.com>,
anemet@caviumnetworks.com, mark@codesourcery.com, "Lau,
David" <davidlau@mips.com>
Subject: Re: [PATCH] MIPS function attributes for interrupt handlers
Date: Sat, 28 Feb 2009 18:39:00 -0000 [thread overview]
Message-ID: <alpine.LFD.1.10.0902281620160.22096@ftp.linux-mips.org> (raw)
In-Reply-To: <000801c99949$50530450$a914a8c0@mips.com>
On Fri, 27 Feb 2009, Fu, Chao-Ying wrote:
> > Please note that "eret" is not supported for -march=mips1 and
> > -march=mips2 in GAS as those ISAs did not have this instrution ("rfe" in
> > the delay slot of a "jr" was used instead). While, if I understand
> > correctly, the interrupt function attribute makes sense for the EIC mode
> > only, I suggest that you make sure the compiler does not produce code GAS
> > will refuse to swallow for older ISAs. Perhaps the attribute should only
> > be supported for ISAs which can actually run the resulting code
> > ("-march=mips32" and above?).
>
> It can be used for the original mode (single,ilp0.. ilp7) and the EIC
> mode.
>
> People just need to put GCC-generated handlers to the address they want
> in the linker script, and provide some bootup code.
Hmm, I thought the shadow register sets could only be switched
automatically with the EIC mode. I have checked the ISA doc now to be
proved I was slightly confused -- the R2 ISA retrofitted the SRS switching
into the older concept of the use of a dedicated exception vector (as
provided by cp0.cause.iv) for the interrupt exception.
All is a new MIPS32r2/MIPS64r2 addition anyway. With older processors
you have to perform stack switching in software and then save/restore
registers on the interrupt stack and I think that's too system-specific to
be doable from the compiler in a generic way.
> Maybe we just emit "jr" and "ref", when mips1 or mips2 is used to compile
> code.
IMO it does not make sense to support it in any way except from making a
small amount of effort to make sure such configurations do not make the
tools behave inconsistently. There is no MIPS I or II processor that
would support the SRS so the interrupt handler won't ever run on one.
Maciej
next prev parent reply other threads:[~2009-02-28 18:06 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-14 20:29 Fu, Chao-Ying
2008-10-15 23:47 ` Richard Sandiford
2008-10-20 23:03 ` Mark Mitchell
2008-10-20 23:24 ` Adam Nemet
2008-10-21 16:15 ` Weddington, Eric
2008-10-21 17:01 ` Mark Mitchell
2008-10-21 23:11 ` Richard Sandiford
2008-10-21 23:49 ` Mark Mitchell
2008-10-22 0:16 ` Thiemo Seufer
2008-10-22 1:05 ` Mark Mitchell
2008-10-22 6:36 ` Thiemo Seufer
2008-10-22 6:54 ` Mark Mitchell
2008-10-22 7:30 ` Weddington, Eric
2008-10-22 10:03 ` Richard Sandiford
2008-10-22 17:43 ` Mark Mitchell
2008-10-22 20:28 ` Richard Sandiford
2008-10-28 5:07 ` Fu, Chao-Ying
2008-10-29 8:05 ` Richard Sandiford
2008-10-16 22:34 ` Adam Nemet
2009-02-25 7:01 ` Fu, Chao-Ying
2009-02-25 9:35 ` Adam Nemet
2009-02-25 17:51 ` Daniel Jacobowitz
2009-02-26 9:48 ` Fu, Chao-Ying
2009-02-27 20:46 ` Maciej W. Rozycki
2009-02-28 10:15 ` Fu, Chao-Ying
2009-02-28 18:39 ` Maciej W. Rozycki [this message]
2008-10-17 11:40 Fu, Chao-Ying
2008-10-23 9:06 Ross Ridge
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