From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3541 invoked by alias); 28 Feb 2009 18:06:28 -0000 Received: (qmail 3531 invoked by uid 22791); 28 Feb 2009 18:06:27 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from ftp.linux-mips.org (HELO ftp.linux-mips.org) (213.58.128.207) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 28 Feb 2009 18:06:22 +0000 Received: from localhost.localdomain ([127.0.0.1]:35468 "EHLO localhost.localdomain") by ftp.linux-mips.org with ESMTP id S20808056AbZB1SGQ (ORCPT ); Sat, 28 Feb 2009 18:06:16 +0000 Date: Sat, 28 Feb 2009 18:39:00 -0000 From: "Maciej W. Rozycki" To: "Fu, Chao-Ying" cc: Daniel Jacobowitz , gcc-patches@gcc.gnu.org, Richard Sandiford , anemet@caviumnetworks.com, mark@codesourcery.com, "Lau, David" Subject: Re: [PATCH] MIPS function attributes for interrupt handlers In-Reply-To: <000801c99949$50530450$a914a8c0@mips.com> Message-ID: References: <94BD67F8AF3ED34FA362C662BA1F12C501007E7F@MTVEXCHANGE.mips.com> <000801c996ed$112961b0$a914a8c0@mips.com> <20090225171443.GA19624@caradoc.them.org> <000e01c997b7$706b4f60$a914a8c0@mips.com> <000801c99949$50530450$a914a8c0@mips.com> User-Agent: Alpine 1.10 (LFD 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2009-02/txt/msg01268.txt.bz2 On Fri, 27 Feb 2009, Fu, Chao-Ying wrote: > > Please note that "eret" is not supported for -march=mips1 and > > -march=mips2 in GAS as those ISAs did not have this instrution ("rfe" in > > the delay slot of a "jr" was used instead). While, if I understand > > correctly, the interrupt function attribute makes sense for the EIC mode > > only, I suggest that you make sure the compiler does not produce code GAS > > will refuse to swallow for older ISAs. Perhaps the attribute should only > > be supported for ISAs which can actually run the resulting code > > ("-march=mips32" and above?). > > It can be used for the original mode (single,ilp0.. ilp7) and the EIC > mode. > > People just need to put GCC-generated handlers to the address they want > in the linker script, and provide some bootup code. Hmm, I thought the shadow register sets could only be switched automatically with the EIC mode. I have checked the ISA doc now to be proved I was slightly confused -- the R2 ISA retrofitted the SRS switching into the older concept of the use of a dedicated exception vector (as provided by cp0.cause.iv) for the interrupt exception. All is a new MIPS32r2/MIPS64r2 addition anyway. With older processors you have to perform stack switching in software and then save/restore registers on the interrupt stack and I think that's too system-specific to be doable from the compiler in a generic way. > Maybe we just emit "jr" and "ref", when mips1 or mips2 is used to compile > code. IMO it does not make sense to support it in any way except from making a small amount of effort to make sure such configurations do not make the tools behave inconsistently. There is no MIPS I or II processor that would support the SRS so the interrupt handler won't ever run on one. Maciej