Documenting the MIPS changes in 4.7

Documenting the MIPS changes in 4.7

[Richard Sandiford]

I've committed this patch to describe the MIPS changes in GCC 4.7.
Corrections, comments, and help with wordsmithing are all welcome.

Thanks,
Richard


Index: htdocs/gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.74
diff -u -p -r1.74 changes.html
--- htdocs/gcc-4.7/changes.html	16 Jan 2012 08:39:01 -0000	1.74
+++ htdocs/gcc-4.7/changes.html	5 Feb 2012 15:10:10 -0000
@@ -51,6 +51,9 @@
     <li>Support has been removed for the NetWare x86 configuration
     obsoleted in GCC 4.6.</li>
 
+    <li>It is no longer possible to use the <code>"l"</code>
+    constraint in MIPS16 asm statements.</li>
+
     <li>More information on porting to GCC 4.7 from previous versions
     of GCC can be found in
     the <a href="http://gcc.gnu.org/gcc-4.7/porting_to.html">porting
@@ -571,9 +574,29 @@ well.</p></li>
     <li>...</li>
   </ul>
 
-<!--
 <h3 id="mips">MIPS</h3>
--->
+  <ul>
+    <li>GCC now supports thread-local storage (TLS) for MIPS16.
+        This support requires GNU binutils 2.22 or later.</li>
+
+    <li>GCC can now generate code specifically for the Cavium Octeon+
+        and Octeon2 processors.  The associated command-line options are
+        <code>-march=octeon+</code> and <code>-march=octeon2</code>
+        respectively.  Both options require GNU binutils 2.22 or later.</li>
+
+    <li>GCC can now work around certain 24k errata, under the control
+        of the command-line option <code>-mfix-24k</code>.
+        These workarounds require GNU binutils 2.20 or later.</li>
+
+    <li>32-bit MIPS GNU/Linux targets such as <code>mips-linux-gnu</code>
+        can now build n32 and n64 multilibs.  The result is effectively
+        a 64-bit GNU/Linux toolchain that generates 32-bit code by default.
+        Use the configure-time option <code>--enable-targets=all</code>
+        to select these extra multilibs.</li>
+
+    <li>Passing <code>-fno-delayed-branch</code> now also stops the
+        assembler from automatically filling delay slots.</li>
+  </ul>
 
 <!--
 <h3 id="picochip">picochip</h3>

Re: Documenting the MIPS changes in 4.7

[Andrew Pinski]

On Sun, Feb 5, 2012 at 7:13 AM, Richard Sandiford
<rdsandiford@googlemail.com> wrote:
> I've committed this patch to describe the MIPS changes in GCC 4.7.
> Corrections, comments, and help with wordsmithing are all welcome.
>
> Thanks,
> Richard
>
>
> Index: htdocs/gcc-4.7/changes.html
> ===================================================================
> RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
> retrieving revision 1.74
> diff -u -p -r1.74 changes.html
> --- htdocs/gcc-4.7/changes.html 16 Jan 2012 08:39:01 -0000      1.74
> +++ htdocs/gcc-4.7/changes.html 5 Feb 2012 15:10:10 -0000
> @@ -51,6 +51,9 @@
>     <li>Support has been removed for the NetWare x86 configuration
>     obsoleted in GCC 4.6.</li>
>
> +    <li>It is no longer possible to use the <code>"l"</code>
> +    constraint in MIPS16 asm statements.</li>
> +
>     <li>More information on porting to GCC 4.7 from previous versions
>     of GCC can be found in
>     the <a href="http://gcc.gnu.org/gcc-4.7/porting_to.html">porting
> @@ -571,9 +574,29 @@ well.</p></li>
>     <li>...</li>
>   </ul>
>
> -<!--
>  <h3 id="mips">MIPS</h3>
> --->
> +  <ul>
> +    <li>GCC now supports thread-local storage (TLS) for MIPS16.
> +        This support requires GNU binutils 2.22 or later.</li>
> +
> +    <li>GCC can now generate code specifically for the Cavium Octeon+
> +        and Octeon2 processors.  The associated command-line options are
> +        <code>-march=octeon+</code> and <code>-march=octeon2</code>
> +        respectively.  Both options require GNU binutils 2.22 or later.</li>

This part looks good from my point of view.

Thanks,
Anrew Pinski


> +
> +    <li>GCC can now work around certain 24k errata, under the control
> +        of the command-line option <code>-mfix-24k</code>.
> +        These workarounds require GNU binutils 2.20 or later.</li>
> +
> +    <li>32-bit MIPS GNU/Linux targets such as <code>mips-linux-gnu</code>
> +        can now build n32 and n64 multilibs.  The result is effectively
> +        a 64-bit GNU/Linux toolchain that generates 32-bit code by default.
> +        Use the configure-time option <code>--enable-targets=all</code>
> +        to select these extra multilibs.</li>
> +
> +    <li>Passing <code>-fno-delayed-branch</code> now also stops the
> +        assembler from automatically filling delay slots.</li>
> +  </ul>
>
>  <!--
>  <h3 id="picochip">picochip</h3>

Re: Documenting the MIPS changes in 4.7

[Gerald Pfeifer]

On Sun, 5 Feb 2012, Richard Sandiford wrote:
> I've committed this patch to describe the MIPS changes in GCC 4.7.
> Corrections, comments, and help with wordsmithing are all welcome.

Nice!  How about the small follow-up below?

Gerald

Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.79
diff -u -3 -p -r1.79 changes.html
--- changes.html	12 Feb 2012 21:46:29 -0000	1.79
+++ changes.html	12 Feb 2012 22:01:35 -0000
@@ -52,7 +52,7 @@
     obsoleted in GCC 4.6.</li>
 
     <li>It is no longer possible to use the <code>"l"</code>
-    constraint in MIPS16 asm statements.</li>
+    constraint in MIPS16 <code>asm</code> statements.</li>
 
     <li>More information on porting to GCC 4.7 from previous versions
     of GCC can be found in
@@ -609,7 +609,7 @@ well.</p></li>
 <h3 id="mips">MIPS</h3>
   <ul>
     <li>GCC now supports thread-local storage (TLS) for MIPS16.
-        This support requires GNU binutils 2.22 or later.</li>
+        This requires GNU binutils 2.22 or later.</li>
 
     <li>GCC can now generate code specifically for the Cavium Octeon+
         and Octeon2 processors.  The associated command-line options are

Re: Documenting the MIPS changes in 4.7

[Richard Sandiford]

Gerald Pfeifer <gerald@pfeifer.com> writes:
> On Sun, 5 Feb 2012, Richard Sandiford wrote:
>> I've committed this patch to describe the MIPS changes in GCC 4.7.
>> Corrections, comments, and help with wordsmithing are all welcome.
>
> Nice!  How about the small follow-up below?

The first definitely looks good, thanks.  Not sure either way about
the second; I'll leave it up to you.

Richard