From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 71746 invoked by alias); 12 Apr 2015 21:36:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 71732 invoked by uid 89); 12 Apr 2015 21:36:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: ainaz.pair.com Received: from ainaz.pair.com (HELO ainaz.pair.com) (209.68.2.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sun, 12 Apr 2015 21:36:49 +0000 Received: from tuna.dhcp.nue.suse.com (charybdis-ext.suse.de [195.135.221.2]) by ainaz.pair.com (Postfix) with ESMTPSA id 4FF513F421; Sun, 12 Apr 2015 17:36:46 -0400 (EDT) Date: Sun, 12 Apr 2015 21:36:00 -0000 From: Gerald Pfeifer To: Matthew Fortune , "Moore, Catherine" , gcc-patches@gcc.gnu.org Subject: RE: [PATCH,WWWDOCS] MIPS changes for GCC 5.0 In-Reply-To: <6D39441BF12EF246A7ABCE6654B0235320FC8EA9@LEMAIL01.le.imgtec.org> Message-ID: References: <6D39441BF12EF246A7ABCE6654B0235320FC7F04@LEMAIL01.le.imgtec.org> <6D39441BF12EF246A7ABCE6654B0235320FC8EA9@LEMAIL01.le.imgtec.org> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg00536.txt.bz2 On Thu, 5 Feb 2015, Matthew Fortune wrote: > Thanks Catherine. Good call to remove the markup while reviewing. I've > done one more pass on this to have the same phrasing used where similar > points are being made. I also added a comment about link compatibility > for FP64. Updated text is at the end. Here are some more changes on top of the version that was committed. Add an article, add markup, simplify language, and use 64-bit instead of 64-bits in the MIPS section. ("has been changed" -> "has changed", "is being used" -> "is used", and there are one or two others which I left since I wasn't sure.) I applied this now, though if there is anything you disagree with we can always revisit. Just advise! Gerald Index: changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v retrieving revision 1.104 diff -u -r1.104 changes.html --- changes.html 12 Apr 2015 20:26:50 -0000 1.104 +++ changes.html 12 Apr 2015 21:32:20 -0000 @@ -739,13 +739,13 @@ -march=p5600 command-line option.
  • The Cavium Octeon3 processor is now supported using the -march=octeon3 command-line option.
    • -
  • MIPS Release 6 is now supported using -mips32r6 and - -mips64r6 command-line options.
    • +
  • MIPS Release 6 is now supported using the -mips32r6 + and -mips64r6 command-line options.
  • The o32 ABI has been modified and extended. The o32 64-bit floating-point register support is now obsolete and has been removed. It has been replaced by three ABI extensions FPXX, FP64A, and FP64. - The meaning of the -mfp64 command-line option has been - changed and it is now used to enable the FP64A and FP64 ABI extensions. + The meaning of the -mfp64 command-line option has + changed. It is now used to enable the FP64A and FP64 ABI extensions.
    • The FPXX extension requires that code generated to access double-precision values use even-numbered registers. Code that @@ -755,14 +755,14 @@ -mfpxx can be used to enable this extension. MIPS II is the minimum processor required.
    • The o32 FP64A extension requires that floating-point registers be - 64-bits and odd-numbered single-precision registers are not + 64-bit and odd-numbered single-precision registers are not allowed. Code that adheres to the o32 FP64A variant is link-compatible with all other o32 double-precision ABI variants. The command-line options -mabi=32 -mfp64 -mno-odd-spreg can be used to enable this extension. MIPS32R2 is the minimum processor required.
    • The o32 FP64 extension also requires that floating-point registers - be 64-bits, but permits the use of single-precision registers. + be 64-bit, but permits the use of single-precision registers. Code that adheres to the o32 FP64 variant is link-compatible with o32 FPXX and o32 FP64A variants only, i.e. it is not compatible with the original o32 double-precision ABI. The command-line @@ -777,10 +777,10 @@ required to run the generated code on MIPSR5 cores in conjunction with future MIPS SIMD (MSA) code and MIPSR6 cores.
    • GCC will now pass all floating-point options to the assembler if GNU - binutils 2.25 is being used. As a result, any inline assembly code that - uses hard-float instructions should be amended to include a .set - directive to override the global assembler options when compiling for - soft-float targets.
      • + binutils 2.25 is used. As a result, any inline assembly code that + uses hard-float instructions should be amended to include a + .set directive to override the global assembler options + when compiling for soft-float targets.

    NDS32