[PATCH][2/n] Avoid vectorizing IV update when not necessary

[Richard Biener <rguenther@suse.de>]

When doing SLP reduction a needlessy marked IV update causes hybrid
SLP and thus pointless unrolling to happen.  The following avoids
vectorizing the IV update when not otherwise necessary.  Currently
we're creating a dead vector stmt for all inductions that are vectorized.

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied.

Richard.

2017-06-02  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop.c (vect_analyze_loop_operations): Not relevant
	PHIs are ok.
	* tree-vect-stmts.c (process_use): Do not mark backedge defs
	for inductions as relevant.

Index: gcc/tree-vect-loop.c
===================================================================
--- gcc/tree-vect-loop.c	(revision 248788)
+++ gcc/tree-vect-loop.c	(working copy)
@@ -1708,8 +1708,7 @@ vect_analyze_loop_operations (loop_vec_i
                  are not used in the outerloop (unless it is double reduction,
                  i.e., this phi is vect_reduction_def), cause this case
                  requires to actually do something here.  */
-              if ((!STMT_VINFO_RELEVANT_P (stmt_info)
-                   || STMT_VINFO_LIVE_P (stmt_info))
+              if (STMT_VINFO_LIVE_P (stmt_info)
                   && STMT_VINFO_DEF_TYPE (stmt_info)
                      != vect_double_reduction_def)
                 {
Index: gcc/tree-vect-stmts.c
===================================================================
--- gcc/tree-vect-stmts.c	(revision 248788)
+++ gcc/tree-vect-stmts.c	(working copy)
@@ -579,6 +579,20 @@ process_use (gimple *stmt, tree use, loo
           gcc_unreachable ();
         }
     }
+  /* We are also not interested in uses on loop PHI backedges that are
+     inductions.  Otherwise we'll needlessly vectorize the IV increment
+     and cause hybrid SLP for SLP inductions.  */
+  else if (gimple_code (stmt) == GIMPLE_PHI
+	   && STMT_VINFO_DEF_TYPE (stmt_vinfo) == vect_induction_def
+	   && (PHI_ARG_DEF_FROM_EDGE (stmt, loop_latch_edge (bb->loop_father))
+	       == use))
+    {
+      if (dump_enabled_p ())
+	dump_printf_loc (MSG_NOTE, vect_location,
+                         "induction value on backedge.\n");
+      return true;
+    }
+
 
   vect_mark_relevant (worklist, def_stmt, relevant, false);
   return true;