Re: [PATCH v4 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Jeff Law <jeffreyalaw@gmail.com>]

On 9/5/23 23:47, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
> containing two instructions for conditional move and will be supported on
> their Veyron V1 CPU.
> 
> And most notably (for historical reasons), 'XVentanaCondOps' and the
> standard 'Zicond' extension are functionally equivalent (only encodings and
> instruction names are different).
> 
> *   czero.eqz == vt.maskc
> *   czero.nez == vt.maskcn
> 
> This commit adds support for the 'XVentanaCondOps' extension by extending
> 'Zicond' extension support.  With this, we can now reuse the optimization
> using the 'Zicond' extension for the 'XVentanaCondOps' extension.
> 
> The specification for the 'XVentanaCondOps' extension is based on:
> <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
> 	Parse 'XVentanaCondOps' extension.
> 	* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
> 	(TARGET_XVENTANACONDOPS): Ditto.
> 	(TARGET_ZICOND_LIKE): New to represent targets with conditional
> 	moves like 'Zicond'.  It includes RV64 + 'XVentanaCondOps'.
> 	* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
> 	with TARGET_ZICOND_LIKE.
> 	(riscv_expand_conditional_move): Ditto.
> 	* config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
> 	TARGET_ZICOND_LIKE.
> 	* config/riscv/riscv.opt: Add new riscv_xventana_subext.
> 	* config/riscv/zicond.md: Modify description.
> 	(eqz_ventana): New to match corresponding czero instructions.
> 	(nez_ventana): Ditto.
> 	(*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
> 	'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
> 	(*czero.<eqz>.<GPR><X>): Ditto.
> 	(*czero.eqz.<GPR><X>.opt1): Ditto.
> 	(*czero.nez.<GPR><X>.opt2): Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
> 	* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
> 	test to make sure that XVentanaCondOps instructions are disabled
> 	on RV32.
> 	* gcc.target/riscv/xventanacondops-xor-01.c: New test,
OK.  Thanks for taking care of this.  I guess Raphael and I should get 
more active on pushing the rest of the veyron-v1 bits upstream :-)

Jeff