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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id x8-20020aa793a8000000b0058bc60dd98dsm4822455pff.23.2023.03.05.09.41.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 05 Mar 2023 09:41:57 -0800 (PST) Message-ID: Date: Sun, 5 Mar 2023 10:41:56 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v4 5/9] riscv: thead: Add support for the XTheadBb ISA extension Content-Language: en-US To: Christoph Muellner , gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu , Andrew Pinski , Hans-Peter Nilsson References: <20230302083534.4076244-1-christoph.muellner@vrull.eu> <20230302083534.4076244-6-christoph.muellner@vrull.eu> From: Jeff Law In-Reply-To: <20230302083534.4076244-6-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_MANYTO,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 3/2/23 01:35, Christoph Muellner wrote: > From: Christoph Müllner > > This patch adds support for the XTheadBb ISA extension. > Thus, there is a functional overlap of the new instructions with > existing Bitmanip instruction, which allows a good amount of code > sharing. However, the vendor extensions are cleanly separated from > the standard extensions (e.g. by using INSN expand pattern that > will re-emit RTL that matches the patterns of either Bitmanip or > XThead INSNs). > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index d6c2265e9d4..fc8ce9f5226 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -3087,6 +3087,26 @@ (define_insn "riscv_prefetchi_" > "prefetch.i\t%a0" > ) > > +(define_expand "extv" > + [(set (match_operand:GPR 0 "register_operand" "=r") > + (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") > + (match_operand 2 "const_int_operand") > + (match_operand 3 "const_int_operand")))] > + "TARGET_XTHEADBB" > +) > + > +(define_expand "extzv" > + [(set (match_operand:GPR 0 "register_operand" "=r") > + (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r") > + (match_operand 2 "const_int_operand") > + (match_operand 3 "const_int_operand")))] > + "TARGET_XTHEADBB" > +{ > + if (TARGET_XTHEADBB > + && (INTVAL (operands[2]) < 8) && (INTVAL (operands[3]) == 0)) > + FAIL; > +}) Note that bitmanip has single bit extractions which probably should be handed by extzv rather than relying strictly on the combiner to synthesize them. Similarly for single bit insertions. I've actually got a TODO on Raphael's plate to see how renaming the existing bitmanip bit extraction to extzv affects code generation. I'm not offhand sure where it is on his priority list yet. I guess the wider point is the ext and ins expanders should probably be accepting single bit extractions/insertions when ZBS is enabled. Jeff