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From: Andrew Stubbs <ams@codesourcery.com>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>, <gcc-patches@gcc.gnu.org>
Cc: <rguenther@suse.de>, <jeffreyalaw@gmail.com>
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV
Date: Tue, 10 Oct 2023 10:40:27 +0100	[thread overview]
Message-ID: <b12e8119-3425-49e9-988b-9d0d7bc3079f@codesourcery.com> (raw)
In-Reply-To: <20231010013904.105336-1-juzhe.zhong@rivai.ai>

On 10/10/2023 02:39, Juzhe-Zhong wrote:
> Here is the reference comparing dump IR between ARM SVE and RVV.
> 
> https://godbolt.org/z/zqess8Gss
> 
> We can see RVV has one more dump IR:
> optimized: basic block part vectorized using 128 byte vectors
> since RVV has 1024 bit vectors.
> 
> The codegen is reasonable good.
> 
> However, I saw GCN also has 1024 bit vector.
> This patch may cause this case FAIL in GCN port ?
> 
> Hi, GCN folk, could you check this patch in GCN port for me ?

This patch *fixes* an existing test fail on GCN. :)

It's probably one of the many I've never had time to analyze (and 
optimizing more than expected makes it low priority).

LGTM

Andrew

  reply	other threads:[~2023-10-10  9:40 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-10  1:39 Juzhe-Zhong
2023-10-10  9:40 ` Andrew Stubbs [this message]
2023-10-10  9:43   ` juzhe.zhong
2023-10-10 10:17 ` Richard Biener

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