[PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 1014 bytes --]

Hi.

This introduces new ForceHelp option flag that helps to
print valid option enum values that are not directly
used as a type of an option.

May I please ask ARM folks to test the patch?
Thanks,
Martin

gcc/ChangeLog:

2018-07-18  Martin Liska  <mliska@suse.cz>

        PR driver/83193
	* config/arm/arm-tables.opt: Add ForceHelp flag for
        processor_type and arch_name enum types.
	* config/arm/parsecpu.awk: Likewise.
	* doc/options.texi: Document new flag ForceHelp.
	* opt-read.awk: Parse ForceHelp and set it in construction.
	* optc-gen.awk: Likewise.
	* opts.c (print_filtered_help): Handle force_help option.
	* opts.h (struct cl_enum): New field force_help.
---
 gcc/config/arm/arm-tables.opt | 6 +++---
 gcc/config/arm/parsecpu.awk   | 6 +++---
 gcc/doc/options.texi          | 4 ++++
 gcc/opt-read.awk              | 3 +++
 gcc/optc-gen.awk              | 3 ++-
 gcc/opts.c                    | 3 ++-
 gcc/opts.h                    | 3 +++
 7 files changed, 20 insertions(+), 8 deletions(-)



[-- Attachment #2: 0001-Show-valid-options-for-march-and-mtune-in-help-targe.patch --]
[-- Type: text/x-patch, Size: 3869 bytes --]

diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index eacee746a39..cbaa67385d7 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -21,8 +21,8 @@
 ; <http://www.gnu.org/licenses/>.
 
 Enum
-Name(processor_type) Type(enum processor_type)
-Known ARM CPUs (for use with the -mcpu= and -mtune= options):
+Name(processor_type) Type(enum processor_type) ForceHelp
+Known ARM CPUs (for use with the -mtune= options):
 
 EnumValue
 Enum(processor_type) String(arm8) Value( TARGET_CPU_arm8)
@@ -298,7 +298,7 @@ EnumValue
 Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
 
 Enum
-Name(arm_arch) Type(int)
+Name(arm_arch) Type(int) ForceHelp
 Known ARM architectures (for use with the -march= option):
 
 EnumValue
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
index aabe1b0c64c..162712acb0e 100644
--- a/gcc/config/arm/parsecpu.awk
+++ b/gcc/config/arm/parsecpu.awk
@@ -441,8 +441,8 @@ function gen_opt () {
     boilerplate("md")
 
     print "Enum"
-    print "Name(processor_type) Type(enum processor_type)"
-    print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
+    print "Name(processor_type) Type(enum processor_type) ForceHelp"
+    print "Known ARM CPUs (for use with the -mtune= options):\n"
 
     ncpus = split (cpu_list, cpus)
 
@@ -454,7 +454,7 @@ function gen_opt () {
     }
 
     print "Enum"
-    print "Name(arm_arch) Type(int)"
+    print "Name(arm_arch) Type(int) ForceHelp"
     print "Known ARM architectures (for use with the -march= option):\n"
 
     narchs = split (arch_list, archs)
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index b3ca9f6fce6..1c9abac0b36 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -120,6 +120,10 @@ being described by this record.
 This property is required; it says what value (representable as
 @code{int}) should be used for the given string.
 
+@item ForceHelp
+This property is optional.  If present, enum values is printed
+in @option{--help} output.
+
 @item Canonical
 This property is optional.  If present, it says the present string is
 the canonical one among all those with the given value.  Other strings
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index 2072958e6ba..6d2be9e99d7 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -89,6 +89,9 @@ BEGIN {
 			enum_index[name] = n_enums
 			enum_unknown_error[name] = unknown_error
 			enum_help[name] = $3
+			enum_force_help[name] = test_flag("ForceHelp", props, "true")
+			if (enum_force_help[name] == "")
+			  enum_force_help[name] = "false"
 			n_enums++
 		}
 		else if ($1 == "EnumValue")  {
diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
index bf177e86330..5c4f4239db0 100644
--- a/gcc/optc-gen.awk
+++ b/gcc/optc-gen.awk
@@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
 	print "    cl_enum_" name "_data,"
 	print "    sizeof (" enum_type[name] "),"
 	print "    cl_enum_" name "_set,"
-	print "    cl_enum_" name "_get"
+	print "    cl_enum_" name "_get,"
+	print "    " enum_force_help[name]
 	print "  },"
 }
 print "};"
diff --git a/gcc/opts.c b/gcc/opts.c
index b8ae8756b4f..214ef806cd5 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
     {
       unsigned int j, pos;
 
-      if (opts->x_help_enum_printed[i] != 1)
+      if (opts->x_help_enum_printed[i] != 1
+	  && !cl_enums[i].force_help)
 	continue;
       if (cl_enums[i].help == NULL)
 	continue;
diff --git a/gcc/opts.h b/gcc/opts.h
index 3723bdbf95b..c8777b3cd6a 100644
--- a/gcc/opts.h
+++ b/gcc/opts.h
@@ -193,6 +193,9 @@ struct cl_enum
 
   /* Function to get the value of a variable of this type.  */
   int (*get) (const void *var);
+
+  /* Force enum to be printed in help.  */
+  bool force_help;
 };
 
 extern const struct cl_enum cl_enums[];

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Thomas Preudhomme]

Hi Martin,

Why is this needed when -mfpu does not seem to need it for instance?
Regarding the patch:

> -    print "Name(processor_type) Type(enum processor_type)"
> -    print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
> +    print "Known ARM CPUs (for use with the -mtune= options):\n"

Why changing the text beyond adding ForceHelp?

> +@item ForceHelp
> +This property is optional.  If present, enum values is printed
> +in @option{--help} output.
> +

are printed

Thanks,

Thomas
On Wed, 18 Jul 2018 at 16:50, Martin Liška <mliska@suse.cz> wrote:
>
> Hi.
>
> This introduces new ForceHelp option flag that helps to
> print valid option enum values that are not directly
> used as a type of an option.
>
> May I please ask ARM folks to test the patch?
> Thanks,
> Martin
>
> gcc/ChangeLog:
>
> 2018-07-18  Martin Liska  <mliska@suse.cz>
>
>         PR driver/83193
>         * config/arm/arm-tables.opt: Add ForceHelp flag for
>         processor_type and arch_name enum types.
>         * config/arm/parsecpu.awk: Likewise.
>         * doc/options.texi: Document new flag ForceHelp.
>         * opt-read.awk: Parse ForceHelp and set it in construction.
>         * optc-gen.awk: Likewise.
>         * opts.c (print_filtered_help): Handle force_help option.
>         * opts.h (struct cl_enum): New field force_help.
> ---
>  gcc/config/arm/arm-tables.opt | 6 +++---
>  gcc/config/arm/parsecpu.awk   | 6 +++---
>  gcc/doc/options.texi          | 4 ++++
>  gcc/opt-read.awk              | 3 +++
>  gcc/optc-gen.awk              | 3 ++-
>  gcc/opts.c                    | 3 ++-
>  gcc/opts.h                    | 3 +++
>  7 files changed, 20 insertions(+), 8 deletions(-)
>
>

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 2478 bytes --]

On 07/18/2018 06:28 PM, Thomas Preudhomme wrote:
> Hi Martin,
> 
> Why is this needed when -mfpu does not seem to need it for instance?

Because the mfpu is an enum option type:

mfpu=
Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Init(TARGET_FPU_auto) Save
Specify the name of the target floating point hardware/format.

On the contrary mtune is a string option type:

mtune=
Target RejectNegative ToLower Joined Var(arm_tune_string)
Tune code for the given processor.

That's why mtune enum values are automatically printed in --help=target output.

> Regarding the patch:
> 
>> -    print "Name(processor_type) Type(enum processor_type)"
>> -    print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
>> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
>> +    print "Known ARM CPUs (for use with the -mtune= options):\n"
> 
> Why changing the text beyond adding ForceHelp?

That's probably wrong, do you accept the same values for -mcpu as for -mtune, right?

> 
>> +@item ForceHelp
>> +This property is optional.  If present, enum values is printed
>> +in @option{--help} output.
>> +
> 
> are printed

Yep.

I'm sending updated version of the patch.

Martin

> 
> Thanks,
> 
> Thomas
> On Wed, 18 Jul 2018 at 16:50, Martin Liška <mliska@suse.cz> wrote:
>>
>> Hi.
>>
>> This introduces new ForceHelp option flag that helps to
>> print valid option enum values that are not directly
>> used as a type of an option.
>>
>> May I please ask ARM folks to test the patch?
>> Thanks,
>> Martin
>>
>> gcc/ChangeLog:
>>
>> 2018-07-18  Martin Liska  <mliska@suse.cz>
>>
>>         PR driver/83193
>>         * config/arm/arm-tables.opt: Add ForceHelp flag for
>>         processor_type and arch_name enum types.
>>         * config/arm/parsecpu.awk: Likewise.
>>         * doc/options.texi: Document new flag ForceHelp.
>>         * opt-read.awk: Parse ForceHelp and set it in construction.
>>         * optc-gen.awk: Likewise.
>>         * opts.c (print_filtered_help): Handle force_help option.
>>         * opts.h (struct cl_enum): New field force_help.
>> ---
>>  gcc/config/arm/arm-tables.opt | 6 +++---
>>  gcc/config/arm/parsecpu.awk   | 6 +++---
>>  gcc/doc/options.texi          | 4 ++++
>>  gcc/opt-read.awk              | 3 +++
>>  gcc/optc-gen.awk              | 3 ++-
>>  gcc/opts.c                    | 3 ++-
>>  gcc/opts.h                    | 3 +++
>>  7 files changed, 20 insertions(+), 8 deletions(-)
>>
>>


[-- Attachment #2: 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v2.patch --]
[-- Type: text/x-patch, Size: 4863 bytes --]

From af9140854ca089577a54cc12602d75b3cee6a3ad Mon Sep 17 00:00:00 2001
From: marxin <mliska@suse.cz>
Date: Tue, 20 Feb 2018 10:39:09 +0100
Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
 arm32 (PR driver/83193).

gcc/ChangeLog:

2018-07-18  Martin Liska  <mliska@suse.cz>

        PR driver/83193
	* config/arm/arm-tables.opt: Add ForceHelp flag for
        processor_type and arch_name enum types.
	* config/arm/parsecpu.awk: Likewise.
	* doc/options.texi: Document new flag ForceHelp.
	* opt-read.awk: Parse ForceHelp and set it in construction.
	* optc-gen.awk: Likewise.
	* opts.c (print_filtered_help): Handle force_help option.
	* opts.h (struct cl_enum): New field force_help.
---
 gcc/config/arm/arm-tables.opt | 6 +++---
 gcc/config/arm/parsecpu.awk   | 4 ++--
 gcc/doc/options.texi          | 4 ++++
 gcc/opt-read.awk              | 3 +++
 gcc/optc-gen.awk              | 3 ++-
 gcc/opts.c                    | 3 ++-
 gcc/opts.h                    | 3 +++
 7 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index eacee746a39..cbaa67385d7 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -21,8 +21,8 @@
 ; <http://www.gnu.org/licenses/>.
 
 Enum
-Name(processor_type) Type(enum processor_type)
-Known ARM CPUs (for use with the -mcpu= and -mtune= options):
+Name(processor_type) Type(enum processor_type) ForceHelp
+Known ARM CPUs (for use with the -mtune= options):
 
 EnumValue
 Enum(processor_type) String(arm8) Value( TARGET_CPU_arm8)
@@ -298,7 +298,7 @@ EnumValue
 Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
 
 Enum
-Name(arm_arch) Type(int)
+Name(arm_arch) Type(int) ForceHelp
 Known ARM architectures (for use with the -march= option):
 
 EnumValue
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
index aabe1b0c64c..c499a5ed0ce 100644
--- a/gcc/config/arm/parsecpu.awk
+++ b/gcc/config/arm/parsecpu.awk
@@ -441,7 +441,7 @@ function gen_opt () {
     boilerplate("md")
 
     print "Enum"
-    print "Name(processor_type) Type(enum processor_type)"
+    print "Name(processor_type) Type(enum processor_type) ForceHelp"
     print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
 
     ncpus = split (cpu_list, cpus)
@@ -454,7 +454,7 @@ function gen_opt () {
     }
 
     print "Enum"
-    print "Name(arm_arch) Type(int)"
+    print "Name(arm_arch) Type(int) ForceHelp"
     print "Known ARM architectures (for use with the -march= option):\n"
 
     narchs = split (arch_list, archs)
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index b3ca9f6fce6..af77ad78e8c 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -120,6 +120,10 @@ being described by this record.
 This property is required; it says what value (representable as
 @code{int}) should be used for the given string.
 
+@item ForceHelp
+This property is optional.  If present, enum values are printed
+in @option{--help} output.
+
 @item Canonical
 This property is optional.  If present, it says the present string is
 the canonical one among all those with the given value.  Other strings
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index 2072958e6ba..6d2be9e99d7 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -89,6 +89,9 @@ BEGIN {
 			enum_index[name] = n_enums
 			enum_unknown_error[name] = unknown_error
 			enum_help[name] = $3
+			enum_force_help[name] = test_flag("ForceHelp", props, "true")
+			if (enum_force_help[name] == "")
+			  enum_force_help[name] = "false"
 			n_enums++
 		}
 		else if ($1 == "EnumValue")  {
diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
index bf177e86330..5c4f4239db0 100644
--- a/gcc/optc-gen.awk
+++ b/gcc/optc-gen.awk
@@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
 	print "    cl_enum_" name "_data,"
 	print "    sizeof (" enum_type[name] "),"
 	print "    cl_enum_" name "_set,"
-	print "    cl_enum_" name "_get"
+	print "    cl_enum_" name "_get,"
+	print "    " enum_force_help[name]
 	print "  },"
 }
 print "};"
diff --git a/gcc/opts.c b/gcc/opts.c
index b8ae8756b4f..214ef806cd5 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
     {
       unsigned int j, pos;
 
-      if (opts->x_help_enum_printed[i] != 1)
+      if (opts->x_help_enum_printed[i] != 1
+	  && !cl_enums[i].force_help)
 	continue;
       if (cl_enums[i].help == NULL)
 	continue;
diff --git a/gcc/opts.h b/gcc/opts.h
index 3723bdbf95b..c8777b3cd6a 100644
--- a/gcc/opts.h
+++ b/gcc/opts.h
@@ -193,6 +193,9 @@ struct cl_enum
 
   /* Function to get the value of a variable of this type.  */
   int (*get) (const void *var);
+
+  /* Force enum to be printed in help.  */
+  bool force_help;
 };
 
 extern const struct cl_enum cl_enums[];
-- 
2.18.0

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 193 bytes --]

This is correct version of the patch. Anyway, I'm thinking about the ForceHelp
attribute. I may do it in a bit different version. Let me come up with one another
version of the patch.

Martin


[-- Attachment #2: 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v3.patch --]
[-- Type: text/x-patch, Size: 4750 bytes --]

From 9bfc1400213911b4508e90198df7b2dd11efc85c Mon Sep 17 00:00:00 2001
From: marxin <mliska@suse.cz>
Date: Tue, 20 Feb 2018 10:39:09 +0100
Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
 arm32 (PR driver/83193).

gcc/ChangeLog:

2018-07-18  Martin Liska  <mliska@suse.cz>

        PR driver/83193
	* config/arm/arm-tables.opt: Add ForceHelp flag for
        processor_type and arch_name enum types.
	* config/arm/parsecpu.awk: Likewise.
	* doc/options.texi: Document new flag ForceHelp.
	* opt-read.awk: Parse ForceHelp and set it in construction.
	* optc-gen.awk: Likewise.
	* opts.c (print_filtered_help): Handle force_help option.
	* opts.h (struct cl_enum): New field force_help.
---
 gcc/config/arm/arm-tables.opt | 4 ++--
 gcc/config/arm/parsecpu.awk   | 4 ++--
 gcc/doc/options.texi          | 4 ++++
 gcc/opt-read.awk              | 3 +++
 gcc/optc-gen.awk              | 3 ++-
 gcc/opts.c                    | 3 ++-
 gcc/opts.h                    | 3 +++
 7 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index eacee746a39..c74229e27d7 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -21,7 +21,7 @@
 ; <http://www.gnu.org/licenses/>.
 
 Enum
-Name(processor_type) Type(enum processor_type)
+Name(processor_type) Type(enum processor_type) ForceHelp
 Known ARM CPUs (for use with the -mcpu= and -mtune= options):
 
 EnumValue
@@ -298,7 +298,7 @@ EnumValue
 Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
 
 Enum
-Name(arm_arch) Type(int)
+Name(arm_arch) Type(int) ForceHelp
 Known ARM architectures (for use with the -march= option):
 
 EnumValue
diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
index aabe1b0c64c..c499a5ed0ce 100644
--- a/gcc/config/arm/parsecpu.awk
+++ b/gcc/config/arm/parsecpu.awk
@@ -441,7 +441,7 @@ function gen_opt () {
     boilerplate("md")
 
     print "Enum"
-    print "Name(processor_type) Type(enum processor_type)"
+    print "Name(processor_type) Type(enum processor_type) ForceHelp"
     print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
 
     ncpus = split (cpu_list, cpus)
@@ -454,7 +454,7 @@ function gen_opt () {
     }
 
     print "Enum"
-    print "Name(arm_arch) Type(int)"
+    print "Name(arm_arch) Type(int) ForceHelp"
     print "Known ARM architectures (for use with the -march= option):\n"
 
     narchs = split (arch_list, archs)
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index b3ca9f6fce6..af77ad78e8c 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -120,6 +120,10 @@ being described by this record.
 This property is required; it says what value (representable as
 @code{int}) should be used for the given string.
 
+@item ForceHelp
+This property is optional.  If present, enum values are printed
+in @option{--help} output.
+
 @item Canonical
 This property is optional.  If present, it says the present string is
 the canonical one among all those with the given value.  Other strings
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index 2072958e6ba..6d2be9e99d7 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -89,6 +89,9 @@ BEGIN {
 			enum_index[name] = n_enums
 			enum_unknown_error[name] = unknown_error
 			enum_help[name] = $3
+			enum_force_help[name] = test_flag("ForceHelp", props, "true")
+			if (enum_force_help[name] == "")
+			  enum_force_help[name] = "false"
 			n_enums++
 		}
 		else if ($1 == "EnumValue")  {
diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
index bf177e86330..5c4f4239db0 100644
--- a/gcc/optc-gen.awk
+++ b/gcc/optc-gen.awk
@@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
 	print "    cl_enum_" name "_data,"
 	print "    sizeof (" enum_type[name] "),"
 	print "    cl_enum_" name "_set,"
-	print "    cl_enum_" name "_get"
+	print "    cl_enum_" name "_get,"
+	print "    " enum_force_help[name]
 	print "  },"
 }
 print "};"
diff --git a/gcc/opts.c b/gcc/opts.c
index b8ae8756b4f..214ef806cd5 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
     {
       unsigned int j, pos;
 
-      if (opts->x_help_enum_printed[i] != 1)
+      if (opts->x_help_enum_printed[i] != 1
+	  && !cl_enums[i].force_help)
 	continue;
       if (cl_enums[i].help == NULL)
 	continue;
diff --git a/gcc/opts.h b/gcc/opts.h
index 3723bdbf95b..c8777b3cd6a 100644
--- a/gcc/opts.h
+++ b/gcc/opts.h
@@ -193,6 +193,9 @@ struct cl_enum
 
   /* Function to get the value of a variable of this type.  */
   int (*get) (const void *var);
+
+  /* Force enum to be printed in help.  */
+  bool force_help;
 };
 
 extern const struct cl_enum cl_enums[];
-- 
2.18.0

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Richard Earnshaw (lists)]

On 19/07/18 08:30, Martin Liška wrote:
> This is correct version of the patch. Anyway, I'm thinking about the ForceHelp
> attribute. I may do it in a bit different version. Let me come up with one another
> version of the patch.
> 
> Martin
> 

I don't understand how this is supposed to work.  -mcpu, -march and
-mtune all take strings now and have to be parsed to identify various
sub-components of the parameter.  So why do you talk about these being
enum types?

R.

> 
> 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v3.patch
> 
> 
> From 9bfc1400213911b4508e90198df7b2dd11efc85c Mon Sep 17 00:00:00 2001
> From: marxin <mliska@suse.cz>
> Date: Tue, 20 Feb 2018 10:39:09 +0100
> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>  arm32 (PR driver/83193).
> 
> gcc/ChangeLog:
> 
> 2018-07-18  Martin Liska  <mliska@suse.cz>
> 
>         PR driver/83193
> 	* config/arm/arm-tables.opt: Add ForceHelp flag for
>         processor_type and arch_name enum types.
> 	* config/arm/parsecpu.awk: Likewise.
> 	* doc/options.texi: Document new flag ForceHelp.
> 	* opt-read.awk: Parse ForceHelp and set it in construction.
> 	* optc-gen.awk: Likewise.
> 	* opts.c (print_filtered_help): Handle force_help option.
> 	* opts.h (struct cl_enum): New field force_help.
> ---
>  gcc/config/arm/arm-tables.opt | 4 ++--
>  gcc/config/arm/parsecpu.awk   | 4 ++--
>  gcc/doc/options.texi          | 4 ++++
>  gcc/opt-read.awk              | 3 +++
>  gcc/optc-gen.awk              | 3 ++-
>  gcc/opts.c                    | 3 ++-
>  gcc/opts.h                    | 3 +++
>  7 files changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
> index eacee746a39..c74229e27d7 100644
> --- a/gcc/config/arm/arm-tables.opt
> +++ b/gcc/config/arm/arm-tables.opt
> @@ -21,7 +21,7 @@
>  ; <http://www.gnu.org/licenses/>.
>  
>  Enum
> -Name(processor_type) Type(enum processor_type)
> +Name(processor_type) Type(enum processor_type) ForceHelp
>  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
>  
>  EnumValue
> @@ -298,7 +298,7 @@ EnumValue
>  Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
>  
>  Enum
> -Name(arm_arch) Type(int)
> +Name(arm_arch) Type(int) ForceHelp
>  Known ARM architectures (for use with the -march= option):
>  
>  EnumValue
> diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
> index aabe1b0c64c..c499a5ed0ce 100644
> --- a/gcc/config/arm/parsecpu.awk
> +++ b/gcc/config/arm/parsecpu.awk
> @@ -441,7 +441,7 @@ function gen_opt () {
>      boilerplate("md")
>  
>      print "Enum"
> -    print "Name(processor_type) Type(enum processor_type)"
> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
>      print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
>  
>      ncpus = split (cpu_list, cpus)
> @@ -454,7 +454,7 @@ function gen_opt () {
>      }
>  
>      print "Enum"
> -    print "Name(arm_arch) Type(int)"
> +    print "Name(arm_arch) Type(int) ForceHelp"
>      print "Known ARM architectures (for use with the -march= option):\n"
>  
>      narchs = split (arch_list, archs)
> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
> index b3ca9f6fce6..af77ad78e8c 100644
> --- a/gcc/doc/options.texi
> +++ b/gcc/doc/options.texi
> @@ -120,6 +120,10 @@ being described by this record.
>  This property is required; it says what value (representable as
>  @code{int}) should be used for the given string.
>  
> +@item ForceHelp
> +This property is optional.  If present, enum values are printed
> +in @option{--help} output.
> +
>  @item Canonical
>  This property is optional.  If present, it says the present string is
>  the canonical one among all those with the given value.  Other strings
> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
> index 2072958e6ba..6d2be9e99d7 100644
> --- a/gcc/opt-read.awk
> +++ b/gcc/opt-read.awk
> @@ -89,6 +89,9 @@ BEGIN {
>  			enum_index[name] = n_enums
>  			enum_unknown_error[name] = unknown_error
>  			enum_help[name] = $3
> +			enum_force_help[name] = test_flag("ForceHelp", props, "true")
> +			if (enum_force_help[name] == "")
> +			  enum_force_help[name] = "false"
>  			n_enums++
>  		}
>  		else if ($1 == "EnumValue")  {
> diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
> index bf177e86330..5c4f4239db0 100644
> --- a/gcc/optc-gen.awk
> +++ b/gcc/optc-gen.awk
> @@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
>  	print "    cl_enum_" name "_data,"
>  	print "    sizeof (" enum_type[name] "),"
>  	print "    cl_enum_" name "_set,"
> -	print "    cl_enum_" name "_get"
> +	print "    cl_enum_" name "_get,"
> +	print "    " enum_force_help[name]
>  	print "  },"
>  }
>  print "};"
> diff --git a/gcc/opts.c b/gcc/opts.c
> index b8ae8756b4f..214ef806cd5 100644
> --- a/gcc/opts.c
> +++ b/gcc/opts.c
> @@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
>      {
>        unsigned int j, pos;
>  
> -      if (opts->x_help_enum_printed[i] != 1)
> +      if (opts->x_help_enum_printed[i] != 1
> +	  && !cl_enums[i].force_help)
>  	continue;
>        if (cl_enums[i].help == NULL)
>  	continue;
> diff --git a/gcc/opts.h b/gcc/opts.h
> index 3723bdbf95b..c8777b3cd6a 100644
> --- a/gcc/opts.h
> +++ b/gcc/opts.h
> @@ -193,6 +193,9 @@ struct cl_enum
>  
>    /* Function to get the value of a variable of this type.  */
>    int (*get) (const void *var);
> +
> +  /* Force enum to be printed in help.  */
> +  bool force_help;
>  };
>  
>  extern const struct cl_enum cl_enums[];
> 

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 6001 bytes --]

On 07/19/2018 11:28 AM, Richard Earnshaw (lists) wrote:
> On 19/07/18 08:30, Martin Liška wrote:
>> This is correct version of the patch. Anyway, I'm thinking about the ForceHelp
>> attribute. I may do it in a bit different version. Let me come up with one another
>> version of the patch.
>>
>> Martin
>>
> 
> I don't understand how this is supposed to work.  -mcpu, -march and
> -mtune all take strings now and have to be parsed to identify various
> sub-components of the parameter.  So why do you talk about these being
> enum types?

Yes, they are string types. But for purpose of --help output, it's nice
to present to a user a list of possible values. That's the enum type.

Please take a look at attached patch.

Thanks,
Martin

> 
> R.
> 
>>
>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v3.patch
>>
>>
>> From 9bfc1400213911b4508e90198df7b2dd11efc85c Mon Sep 17 00:00:00 2001
>> From: marxin <mliska@suse.cz>
>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>  arm32 (PR driver/83193).
>>
>> gcc/ChangeLog:
>>
>> 2018-07-18  Martin Liska  <mliska@suse.cz>
>>
>>         PR driver/83193
>> 	* config/arm/arm-tables.opt: Add ForceHelp flag for
>>         processor_type and arch_name enum types.
>> 	* config/arm/parsecpu.awk: Likewise.
>> 	* doc/options.texi: Document new flag ForceHelp.
>> 	* opt-read.awk: Parse ForceHelp and set it in construction.
>> 	* optc-gen.awk: Likewise.
>> 	* opts.c (print_filtered_help): Handle force_help option.
>> 	* opts.h (struct cl_enum): New field force_help.
>> ---
>>  gcc/config/arm/arm-tables.opt | 4 ++--
>>  gcc/config/arm/parsecpu.awk   | 4 ++--
>>  gcc/doc/options.texi          | 4 ++++
>>  gcc/opt-read.awk              | 3 +++
>>  gcc/optc-gen.awk              | 3 ++-
>>  gcc/opts.c                    | 3 ++-
>>  gcc/opts.h                    | 3 +++
>>  7 files changed, 18 insertions(+), 6 deletions(-)
>>
>> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
>> index eacee746a39..c74229e27d7 100644
>> --- a/gcc/config/arm/arm-tables.opt
>> +++ b/gcc/config/arm/arm-tables.opt
>> @@ -21,7 +21,7 @@
>>  ; <http://www.gnu.org/licenses/>.
>>  
>>  Enum
>> -Name(processor_type) Type(enum processor_type)
>> +Name(processor_type) Type(enum processor_type) ForceHelp
>>  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
>>  
>>  EnumValue
>> @@ -298,7 +298,7 @@ EnumValue
>>  Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
>>  
>>  Enum
>> -Name(arm_arch) Type(int)
>> +Name(arm_arch) Type(int) ForceHelp
>>  Known ARM architectures (for use with the -march= option):
>>  
>>  EnumValue
>> diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
>> index aabe1b0c64c..c499a5ed0ce 100644
>> --- a/gcc/config/arm/parsecpu.awk
>> +++ b/gcc/config/arm/parsecpu.awk
>> @@ -441,7 +441,7 @@ function gen_opt () {
>>      boilerplate("md")
>>  
>>      print "Enum"
>> -    print "Name(processor_type) Type(enum processor_type)"
>> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
>>      print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
>>  
>>      ncpus = split (cpu_list, cpus)
>> @@ -454,7 +454,7 @@ function gen_opt () {
>>      }
>>  
>>      print "Enum"
>> -    print "Name(arm_arch) Type(int)"
>> +    print "Name(arm_arch) Type(int) ForceHelp"
>>      print "Known ARM architectures (for use with the -march= option):\n"
>>  
>>      narchs = split (arch_list, archs)
>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>> index b3ca9f6fce6..af77ad78e8c 100644
>> --- a/gcc/doc/options.texi
>> +++ b/gcc/doc/options.texi
>> @@ -120,6 +120,10 @@ being described by this record.
>>  This property is required; it says what value (representable as
>>  @code{int}) should be used for the given string.
>>  
>> +@item ForceHelp
>> +This property is optional.  If present, enum values are printed
>> +in @option{--help} output.
>> +
>>  @item Canonical
>>  This property is optional.  If present, it says the present string is
>>  the canonical one among all those with the given value.  Other strings
>> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>> index 2072958e6ba..6d2be9e99d7 100644
>> --- a/gcc/opt-read.awk
>> +++ b/gcc/opt-read.awk
>> @@ -89,6 +89,9 @@ BEGIN {
>>  			enum_index[name] = n_enums
>>  			enum_unknown_error[name] = unknown_error
>>  			enum_help[name] = $3
>> +			enum_force_help[name] = test_flag("ForceHelp", props, "true")
>> +			if (enum_force_help[name] == "")
>> +			  enum_force_help[name] = "false"
>>  			n_enums++
>>  		}
>>  		else if ($1 == "EnumValue")  {
>> diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
>> index bf177e86330..5c4f4239db0 100644
>> --- a/gcc/optc-gen.awk
>> +++ b/gcc/optc-gen.awk
>> @@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
>>  	print "    cl_enum_" name "_data,"
>>  	print "    sizeof (" enum_type[name] "),"
>>  	print "    cl_enum_" name "_set,"
>> -	print "    cl_enum_" name "_get"
>> +	print "    cl_enum_" name "_get,"
>> +	print "    " enum_force_help[name]
>>  	print "  },"
>>  }
>>  print "};"
>> diff --git a/gcc/opts.c b/gcc/opts.c
>> index b8ae8756b4f..214ef806cd5 100644
>> --- a/gcc/opts.c
>> +++ b/gcc/opts.c
>> @@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
>>      {
>>        unsigned int j, pos;
>>  
>> -      if (opts->x_help_enum_printed[i] != 1)
>> +      if (opts->x_help_enum_printed[i] != 1
>> +	  && !cl_enums[i].force_help)
>>  	continue;
>>        if (cl_enums[i].help == NULL)
>>  	continue;
>> diff --git a/gcc/opts.h b/gcc/opts.h
>> index 3723bdbf95b..c8777b3cd6a 100644
>> --- a/gcc/opts.h
>> +++ b/gcc/opts.h
>> @@ -193,6 +193,9 @@ struct cl_enum
>>  
>>    /* Function to get the value of a variable of this type.  */
>>    int (*get) (const void *var);
>> +
>> +  /* Force enum to be printed in help.  */
>> +  bool force_help;
>>  };
>>  
>>  extern const struct cl_enum cl_enums[];
>>
> 


[-- Attachment #2: 0001-Show-valid-options-for-march-and-mtune-in-help-targe.patch --]
[-- Type: text/x-patch, Size: 5700 bytes --]

From dcb80bbe7b82388f5c7147320d509d6e5a687033 Mon Sep 17 00:00:00 2001
From: marxin <mliska@suse.cz>
Date: Tue, 20 Feb 2018 10:39:09 +0100
Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
 arm32 (PR driver/83193).

gcc/ChangeLog:

2018-07-19  Martin Liska  <mliska@suse.cz>

	* config/arm/arm.opt: Use HelpEnum flag.
	* doc/options.texi: Document it.
	* opt-functions.awk: Parse HelpEnum and fill up
        proper index into enum list.
	* opts.c (print_filtered_help): Mention also enums
        that are not directly, but mentioned in HelpEnum.
	* opts.h (struct cl_option): Add new field var_enum_help
        and change var_enum to signed version.
---
 gcc/config/arm/arm.opt |  6 +++---
 gcc/doc/options.texi   |  5 +++++
 gcc/opt-functions.awk  | 25 +++++++++++++++----------
 gcc/opts.c             |  3 +++
 gcc/opts.h             |  5 ++++-
 5 files changed, 30 insertions(+), 14 deletions(-)

diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index a1286a4a861..f182208edd1 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -82,7 +82,7 @@ mapcs-stack-check
 Target Report Mask(APCS_STACK) Undocumented
 
 march=
-Target RejectNegative ToLower Joined Var(arm_arch_string)
+Target RejectNegative ToLower Joined Var(arm_arch_string) HelpEnum(arm_arch)
 Specify the name of the target architecture.
 
 ; Other arm_arch values are loaded from arm-tables.opt
@@ -107,7 +107,7 @@ Target Report Mask(CALLER_INTERWORKING)
 Thumb: Assume function pointers may go to non-Thumb aware code.
 
 mcpu=
-Target RejectNegative ToLower Joined Var(arm_cpu_string)
+Target RejectNegative ToLower Joined Var(arm_cpu_string) HelpEnum(processor_type)
 Specify the name of the target CPU.
 
 mfloat-abi=
@@ -232,7 +232,7 @@ Target Report Mask(TPCS_LEAF_FRAME)
 Thumb: Generate (leaf) stack frames even if not needed.
 
 mtune=
-Target RejectNegative ToLower Joined Var(arm_tune_string)
+Target RejectNegative ToLower Joined Var(arm_tune_string) HelpEnum(processor_type)
 Tune code for the given processor.
 
 mprint-tune-info
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index b3ca9f6fce6..e234cc809d5 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -120,6 +120,11 @@ being described by this record.
 This property is required; it says what value (representable as
 @code{int}) should be used for the given string.
 
+@item EnumHelp(@var{name})
+Some string options accept enum values as arguments.
+When using @samp{EnumHelp}, list of possible values is listed
+in @option{--help} output.
+
 @item Canonical
 This property is optional.  If present, it says the present string is
 the canonical one among all those with the given value.  Other strings
diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
index 2c371e5a23a..9737b6b115b 100644
--- a/gcc/opt-functions.awk
+++ b/gcc/opt-functions.awk
@@ -232,37 +232,42 @@ function var_type_struct(flags)
 }
 
 # Given that an option has flags FLAGS, return an initializer for the
-# "var_enum", "var_type" and "var_value" fields of its cl_options[] entry.
+# "var_enum", "var_enum_help", "var_type" and "var_value" fields of its cl_options[] entry.
 function var_set(flags)
 {
+  help_enum_index = "-1"
+	if (flag_set_p("HelpEnum.*", flags)) {
+		help_enum_index = enum_index[opt_args("HelpEnum", flags)];
+	}
+
 	if (flag_set_p("Defer", flags))
-		return "0, CLVC_DEFER, 0"
+		return "-1, -1, CLVC_DEFER, 0"
 	s = nth_arg(1, opt_args("Var", flags))
 	if (s != "")
-		return "0, CLVC_EQUAL, " s
+		return "-1, -1, CLVC_EQUAL, " s
 	s = opt_args("Mask", flags);
 	if (s != "") {
 		vn = var_name(flags);
 		if (vn)
-			return "0, CLVC_BIT_SET, OPTION_MASK_" s
+			return "-1, -1, CLVC_BIT_SET, OPTION_MASK_" s
 		else
-			return "0, CLVC_BIT_SET, MASK_" s
+			return "-1, -1, CLVC_BIT_SET, MASK_" s
 	}
 	s = nth_arg(0, opt_args("InverseMask", flags));
 	if (s != "") {
 		vn = var_name(flags);
 		if (vn)
-			return "0, CLVC_BIT_CLEAR, OPTION_MASK_" s
+			return "-1, -1, CLVC_BIT_CLEAR, OPTION_MASK_" s
 		else
-			return "0, CLVC_BIT_CLEAR, MASK_" s
+			return "-1, -1, CLVC_BIT_CLEAR, MASK_" s
 	}
 	if (flag_set_p("Enum.*", flags)) {
 		en = opt_args("Enum", flags);
-		return enum_index[en] ", CLVC_ENUM, 0"
+		return enum_index[en] ", -1, CLVC_ENUM, 0"
 	}
 	if (var_type(flags) == "const char *")
-		return "0, CLVC_STRING, 0"
-	return "0, CLVC_BOOLEAN, 0"
+		return "-1, " help_enum_index ", CLVC_STRING, 0"
+	return "-1, -1, CLVC_BOOLEAN, 0"
 }
 
 # Given that an option called NAME has flags FLAGS, return an initializer
diff --git a/gcc/opts.c b/gcc/opts.c
index b8ae8756b4f..37e779e8732 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1303,6 +1303,9 @@ print_filtered_help (unsigned int include_flags,
       if (option->var_type == CLVC_ENUM
 	  && opts->x_help_enum_printed[option->var_enum] != 2)
 	opts->x_help_enum_printed[option->var_enum] = 1;
+      else if (option->var_enum_help != -1
+	       && opts->x_help_enum_printed[option->var_enum_help] != 2)
+	opts->x_help_enum_printed[option->var_enum_help] = 1;
     }
 
   if (! found)
diff --git a/gcc/opts.h b/gcc/opts.h
index 3723bdbf95b..ba79a36d7ab 100644
--- a/gcc/opts.h
+++ b/gcc/opts.h
@@ -107,7 +107,10 @@ struct cl_option
   unsigned short flag_var_offset;
   /* Index in cl_enums of enum used for this option's arguments, for
      CLVC_ENUM options.  */
-  unsigned short var_enum;
+  short var_enum;
+  /* Index in cl_enums of enum used for string options which
+     have strings as possible values.  */
+  short var_enum_help;
   /* How this option's value is determined and sets a field.  */
   enum cl_var_type var_type;
   /* Value or bit-mask with which to set a field.  */
-- 
2.18.0

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Richard Earnshaw (lists)]

On 19/07/18 10:56, Martin Liška wrote:
> On 07/19/2018 11:28 AM, Richard Earnshaw (lists) wrote:
>> On 19/07/18 08:30, Martin Liška wrote:
>>> This is correct version of the patch. Anyway, I'm thinking about the ForceHelp
>>> attribute. I may do it in a bit different version. Let me come up with one another
>>> version of the patch.
>>>
>>> Martin
>>>
>>
>> I don't understand how this is supposed to work.  -mcpu, -march and
>> -mtune all take strings now and have to be parsed to identify various
>> sub-components of the parameter.  So why do you talk about these being
>> enum types?
> 
> Yes, they are string types. But for purpose of --help output, it's nice
> to present to a user a list of possible values. That's the enum type.
> 
> Please take a look at attached patch.
> 

But that isn't the list of possible values.  Please see the manual.  A
valid CPU name can look something like

	cortex-a53+crypto

and architectures names can be even more complex.

You can't get this from that list of enum values.

R.

> Thanks,
> Martin
> 
>>
>> R.
>>
>>>
>>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v3.patch
>>>
>>>
>>> From 9bfc1400213911b4508e90198df7b2dd11efc85c Mon Sep 17 00:00:00 2001
>>> From: marxin <mliska@suse.cz>
>>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>>  arm32 (PR driver/83193).
>>>
>>> gcc/ChangeLog:
>>>
>>> 2018-07-18  Martin Liska  <mliska@suse.cz>
>>>
>>>         PR driver/83193
>>> 	* config/arm/arm-tables.opt: Add ForceHelp flag for
>>>         processor_type and arch_name enum types.
>>> 	* config/arm/parsecpu.awk: Likewise.
>>> 	* doc/options.texi: Document new flag ForceHelp.
>>> 	* opt-read.awk: Parse ForceHelp and set it in construction.
>>> 	* optc-gen.awk: Likewise.
>>> 	* opts.c (print_filtered_help): Handle force_help option.
>>> 	* opts.h (struct cl_enum): New field force_help.
>>> ---
>>>  gcc/config/arm/arm-tables.opt | 4 ++--
>>>  gcc/config/arm/parsecpu.awk   | 4 ++--
>>>  gcc/doc/options.texi          | 4 ++++
>>>  gcc/opt-read.awk              | 3 +++
>>>  gcc/optc-gen.awk              | 3 ++-
>>>  gcc/opts.c                    | 3 ++-
>>>  gcc/opts.h                    | 3 +++
>>>  7 files changed, 18 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
>>> index eacee746a39..c74229e27d7 100644
>>> --- a/gcc/config/arm/arm-tables.opt
>>> +++ b/gcc/config/arm/arm-tables.opt
>>> @@ -21,7 +21,7 @@
>>>  ; <http://www.gnu.org/licenses/>.
>>>  
>>>  Enum
>>> -Name(processor_type) Type(enum processor_type)
>>> +Name(processor_type) Type(enum processor_type) ForceHelp
>>>  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
>>>  
>>>  EnumValue
>>> @@ -298,7 +298,7 @@ EnumValue
>>>  Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
>>>  
>>>  Enum
>>> -Name(arm_arch) Type(int)
>>> +Name(arm_arch) Type(int) ForceHelp
>>>  Known ARM architectures (for use with the -march= option):
>>>  
>>>  EnumValue
>>> diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
>>> index aabe1b0c64c..c499a5ed0ce 100644
>>> --- a/gcc/config/arm/parsecpu.awk
>>> +++ b/gcc/config/arm/parsecpu.awk
>>> @@ -441,7 +441,7 @@ function gen_opt () {
>>>      boilerplate("md")
>>>  
>>>      print "Enum"
>>> -    print "Name(processor_type) Type(enum processor_type)"
>>> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
>>>      print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
>>>  
>>>      ncpus = split (cpu_list, cpus)
>>> @@ -454,7 +454,7 @@ function gen_opt () {
>>>      }
>>>  
>>>      print "Enum"
>>> -    print "Name(arm_arch) Type(int)"
>>> +    print "Name(arm_arch) Type(int) ForceHelp"
>>>      print "Known ARM architectures (for use with the -march= option):\n"
>>>  
>>>      narchs = split (arch_list, archs)
>>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>>> index b3ca9f6fce6..af77ad78e8c 100644
>>> --- a/gcc/doc/options.texi
>>> +++ b/gcc/doc/options.texi
>>> @@ -120,6 +120,10 @@ being described by this record.
>>>  This property is required; it says what value (representable as
>>>  @code{int}) should be used for the given string.
>>>  
>>> +@item ForceHelp
>>> +This property is optional.  If present, enum values are printed
>>> +in @option{--help} output.
>>> +
>>>  @item Canonical
>>>  This property is optional.  If present, it says the present string is
>>>  the canonical one among all those with the given value.  Other strings
>>> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>>> index 2072958e6ba..6d2be9e99d7 100644
>>> --- a/gcc/opt-read.awk
>>> +++ b/gcc/opt-read.awk
>>> @@ -89,6 +89,9 @@ BEGIN {
>>>  			enum_index[name] = n_enums
>>>  			enum_unknown_error[name] = unknown_error
>>>  			enum_help[name] = $3
>>> +			enum_force_help[name] = test_flag("ForceHelp", props, "true")
>>> +			if (enum_force_help[name] == "")
>>> +			  enum_force_help[name] = "false"
>>>  			n_enums++
>>>  		}
>>>  		else if ($1 == "EnumValue")  {
>>> diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
>>> index bf177e86330..5c4f4239db0 100644
>>> --- a/gcc/optc-gen.awk
>>> +++ b/gcc/optc-gen.awk
>>> @@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
>>>  	print "    cl_enum_" name "_data,"
>>>  	print "    sizeof (" enum_type[name] "),"
>>>  	print "    cl_enum_" name "_set,"
>>> -	print "    cl_enum_" name "_get"
>>> +	print "    cl_enum_" name "_get,"
>>> +	print "    " enum_force_help[name]
>>>  	print "  },"
>>>  }
>>>  print "};"
>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>> index b8ae8756b4f..214ef806cd5 100644
>>> --- a/gcc/opts.c
>>> +++ b/gcc/opts.c
>>> @@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
>>>      {
>>>        unsigned int j, pos;
>>>  
>>> -      if (opts->x_help_enum_printed[i] != 1)
>>> +      if (opts->x_help_enum_printed[i] != 1
>>> +	  && !cl_enums[i].force_help)
>>>  	continue;
>>>        if (cl_enums[i].help == NULL)
>>>  	continue;
>>> diff --git a/gcc/opts.h b/gcc/opts.h
>>> index 3723bdbf95b..c8777b3cd6a 100644
>>> --- a/gcc/opts.h
>>> +++ b/gcc/opts.h
>>> @@ -193,6 +193,9 @@ struct cl_enum
>>>  
>>>    /* Function to get the value of a variable of this type.  */
>>>    int (*get) (const void *var);
>>> +
>>> +  /* Force enum to be printed in help.  */
>>> +  bool force_help;
>>>  };
>>>  
>>>  extern const struct cl_enum cl_enums[];
>>>
>>
> 
> 
> 0001-Show-valid-options-for-march-and-mtune-in-help-targe.patch
> 
> 
> From dcb80bbe7b82388f5c7147320d509d6e5a687033 Mon Sep 17 00:00:00 2001
> From: marxin <mliska@suse.cz>
> Date: Tue, 20 Feb 2018 10:39:09 +0100
> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>  arm32 (PR driver/83193).
> 
> gcc/ChangeLog:
> 
> 2018-07-19  Martin Liska  <mliska@suse.cz>
> 
> 	* config/arm/arm.opt: Use HelpEnum flag.
> 	* doc/options.texi: Document it.
> 	* opt-functions.awk: Parse HelpEnum and fill up
>         proper index into enum list.
> 	* opts.c (print_filtered_help): Mention also enums
>         that are not directly, but mentioned in HelpEnum.
> 	* opts.h (struct cl_option): Add new field var_enum_help
>         and change var_enum to signed version.
> ---
>  gcc/config/arm/arm.opt |  6 +++---
>  gcc/doc/options.texi   |  5 +++++
>  gcc/opt-functions.awk  | 25 +++++++++++++++----------
>  gcc/opts.c             |  3 +++
>  gcc/opts.h             |  5 ++++-
>  5 files changed, 30 insertions(+), 14 deletions(-)
> 
> diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
> index a1286a4a861..f182208edd1 100644
> --- a/gcc/config/arm/arm.opt
> +++ b/gcc/config/arm/arm.opt
> @@ -82,7 +82,7 @@ mapcs-stack-check
>  Target Report Mask(APCS_STACK) Undocumented
>  
>  march=
> -Target RejectNegative ToLower Joined Var(arm_arch_string)
> +Target RejectNegative ToLower Joined Var(arm_arch_string) HelpEnum(arm_arch)
>  Specify the name of the target architecture.
>  
>  ; Other arm_arch values are loaded from arm-tables.opt
> @@ -107,7 +107,7 @@ Target Report Mask(CALLER_INTERWORKING)
>  Thumb: Assume function pointers may go to non-Thumb aware code.
>  
>  mcpu=
> -Target RejectNegative ToLower Joined Var(arm_cpu_string)
> +Target RejectNegative ToLower Joined Var(arm_cpu_string) HelpEnum(processor_type)
>  Specify the name of the target CPU.
>  
>  mfloat-abi=
> @@ -232,7 +232,7 @@ Target Report Mask(TPCS_LEAF_FRAME)
>  Thumb: Generate (leaf) stack frames even if not needed.
>  
>  mtune=
> -Target RejectNegative ToLower Joined Var(arm_tune_string)
> +Target RejectNegative ToLower Joined Var(arm_tune_string) HelpEnum(processor_type)
>  Tune code for the given processor.
>  
>  mprint-tune-info
> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
> index b3ca9f6fce6..e234cc809d5 100644
> --- a/gcc/doc/options.texi
> +++ b/gcc/doc/options.texi
> @@ -120,6 +120,11 @@ being described by this record.
>  This property is required; it says what value (representable as
>  @code{int}) should be used for the given string.
>  
> +@item EnumHelp(@var{name})
> +Some string options accept enum values as arguments.
> +When using @samp{EnumHelp}, list of possible values is listed
> +in @option{--help} output.
> +
>  @item Canonical
>  This property is optional.  If present, it says the present string is
>  the canonical one among all those with the given value.  Other strings
> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
> index 2c371e5a23a..9737b6b115b 100644
> --- a/gcc/opt-functions.awk
> +++ b/gcc/opt-functions.awk
> @@ -232,37 +232,42 @@ function var_type_struct(flags)
>  }
>  
>  # Given that an option has flags FLAGS, return an initializer for the
> -# "var_enum", "var_type" and "var_value" fields of its cl_options[] entry.
> +# "var_enum", "var_enum_help", "var_type" and "var_value" fields of its cl_options[] entry.
>  function var_set(flags)
>  {
> +  help_enum_index = "-1"
> +	if (flag_set_p("HelpEnum.*", flags)) {
> +		help_enum_index = enum_index[opt_args("HelpEnum", flags)];
> +	}
> +
>  	if (flag_set_p("Defer", flags))
> -		return "0, CLVC_DEFER, 0"
> +		return "-1, -1, CLVC_DEFER, 0"
>  	s = nth_arg(1, opt_args("Var", flags))
>  	if (s != "")
> -		return "0, CLVC_EQUAL, " s
> +		return "-1, -1, CLVC_EQUAL, " s
>  	s = opt_args("Mask", flags);
>  	if (s != "") {
>  		vn = var_name(flags);
>  		if (vn)
> -			return "0, CLVC_BIT_SET, OPTION_MASK_" s
> +			return "-1, -1, CLVC_BIT_SET, OPTION_MASK_" s
>  		else
> -			return "0, CLVC_BIT_SET, MASK_" s
> +			return "-1, -1, CLVC_BIT_SET, MASK_" s
>  	}
>  	s = nth_arg(0, opt_args("InverseMask", flags));
>  	if (s != "") {
>  		vn = var_name(flags);
>  		if (vn)
> -			return "0, CLVC_BIT_CLEAR, OPTION_MASK_" s
> +			return "-1, -1, CLVC_BIT_CLEAR, OPTION_MASK_" s
>  		else
> -			return "0, CLVC_BIT_CLEAR, MASK_" s
> +			return "-1, -1, CLVC_BIT_CLEAR, MASK_" s
>  	}
>  	if (flag_set_p("Enum.*", flags)) {
>  		en = opt_args("Enum", flags);
> -		return enum_index[en] ", CLVC_ENUM, 0"
> +		return enum_index[en] ", -1, CLVC_ENUM, 0"
>  	}
>  	if (var_type(flags) == "const char *")
> -		return "0, CLVC_STRING, 0"
> -	return "0, CLVC_BOOLEAN, 0"
> +		return "-1, " help_enum_index ", CLVC_STRING, 0"
> +	return "-1, -1, CLVC_BOOLEAN, 0"
>  }
>  
>  # Given that an option called NAME has flags FLAGS, return an initializer
> diff --git a/gcc/opts.c b/gcc/opts.c
> index b8ae8756b4f..37e779e8732 100644
> --- a/gcc/opts.c
> +++ b/gcc/opts.c
> @@ -1303,6 +1303,9 @@ print_filtered_help (unsigned int include_flags,
>        if (option->var_type == CLVC_ENUM
>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>  	opts->x_help_enum_printed[option->var_enum] = 1;
> +      else if (option->var_enum_help != -1
> +	       && opts->x_help_enum_printed[option->var_enum_help] != 2)
> +	opts->x_help_enum_printed[option->var_enum_help] = 1;
>      }
>  
>    if (! found)
> diff --git a/gcc/opts.h b/gcc/opts.h
> index 3723bdbf95b..ba79a36d7ab 100644
> --- a/gcc/opts.h
> +++ b/gcc/opts.h
> @@ -107,7 +107,10 @@ struct cl_option
>    unsigned short flag_var_offset;
>    /* Index in cl_enums of enum used for this option's arguments, for
>       CLVC_ENUM options.  */
> -  unsigned short var_enum;
> +  short var_enum;
> +  /* Index in cl_enums of enum used for string options which
> +     have strings as possible values.  */
> +  short var_enum_help;
>    /* How this option's value is determined and sets a field.  */
>    enum cl_var_type var_type;
>    /* Value or bit-mask with which to set a field.  */
> 

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Martin Liška]

On 07/19/2018 12:01 PM, Richard Earnshaw (lists) wrote:
> On 19/07/18 10:56, Martin Liška wrote:
>> On 07/19/2018 11:28 AM, Richard Earnshaw (lists) wrote:
>>> On 19/07/18 08:30, Martin Liška wrote:
>>>> This is correct version of the patch. Anyway, I'm thinking about the ForceHelp
>>>> attribute. I may do it in a bit different version. Let me come up with one another
>>>> version of the patch.
>>>>
>>>> Martin
>>>>
>>>
>>> I don't understand how this is supposed to work.  -mcpu, -march and
>>> -mtune all take strings now and have to be parsed to identify various
>>> sub-components of the parameter.  So why do you talk about these being
>>> enum types?
>>
>> Yes, they are string types. But for purpose of --help output, it's nice
>> to present to a user a list of possible values. That's the enum type.
>>
>> Please take a look at attached patch.
>>
> 
> But that isn't the list of possible values.  Please see the manual.  A
> valid CPU name can look something like
> 
> 	cortex-a53+crypto
> 
> and architectures names can be even more complex.
> 
> You can't get this from that list of enum values.

I'm fully aware of the limitation, it's questionable whether you want to get:

@@ -56,6 +56,9 @@
   Known ARM ABIs (for use with the -mabi= option):
     aapcs aapcs-linux apcs-gnu atpcs iwmmxt
 
+  Known ARM architectures (for use with the -march= option):
+    armv4 armv4t armv5t armv5te armv5tej armv6 armv6-m armv6j armv6k armv6kz armv6s-m armv6t2 armv6z armv6zk armv7 armv7-a armv7-m armv7-r armv7e-m armv7ve armv8-a armv8-m.base armv8-m.main armv8-r armv8.1-a armv8.2-a armv8.3-a armv8.4-a iwmmxt iwmmxt2 native
+
   Known __fp16 formats (for use with the -mfp16-format= option):
     alternative ieee none
 
@@ -68,6 +71,12 @@
   Known floating-point ABIs (for use with the -mfloat-abi= option):
     hard soft softfp
 
+  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
+    arm1020e arm1020t arm1022e arm1026ej-s arm10e arm10tdmi arm1136j-s arm1136jf-s arm1156t2-s arm1156t2f-s arm1176jz-s arm1176jzf-s arm710t arm720t arm740t arm7tdmi arm7tdmi-s arm8 arm810 arm9 arm920 arm920t arm922t arm926ej-s arm940t arm946e-s arm966e-s arm968e-s arm9e
+    arm9tdmi cortex-a12 cortex-a15 cortex-a15.cortex-a7 cortex-a17 cortex-a17.cortex-a7 cortex-a32 cortex-a35 cortex-a5 cortex-a53 cortex-a55 cortex-a57 cortex-a57.cortex-a53 cortex-a7 cortex-a72 cortex-a72.cortex-a53 cortex-a73 cortex-a73.cortex-a35 cortex-a73.cortex-a53
+    cortex-a75 cortex-a75.cortex-a55 cortex-a76 cortex-a76.cortex-a55 cortex-a8 cortex-a9 cortex-m0 cortex-m0.small-multiply cortex-m0plus cortex-m0plus.small-multiply cortex-m1 cortex-m1.small-multiply cortex-m23 cortex-m3 cortex-m33 cortex-m4 cortex-m7 cortex-r4
+    cortex-r4f cortex-r5 cortex-r52 cortex-r7 cortex-r8 ep9312 exynos-m1 fa526 fa606te fa626 fa626te fa726te fmp626 generic-armv7-a iwmmxt iwmmxt2 marvell-pj4 mpcore mpcorenovfp native strongarm strongarm110 strongarm1100 strongarm1110 xgene1 xscale
+
   TLS dialect to use:
     gnu gnu2

I hope it's still beneficial for users.

Martin

> 
> R.
> 
>> Thanks,
>> Martin
>>
>>>
>>> R.
>>>
>>>>
>>>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v3.patch
>>>>
>>>>
>>>> From 9bfc1400213911b4508e90198df7b2dd11efc85c Mon Sep 17 00:00:00 2001
>>>> From: marxin <mliska@suse.cz>
>>>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>>>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>>>  arm32 (PR driver/83193).
>>>>
>>>> gcc/ChangeLog:
>>>>
>>>> 2018-07-18  Martin Liska  <mliska@suse.cz>
>>>>
>>>>         PR driver/83193
>>>> 	* config/arm/arm-tables.opt: Add ForceHelp flag for
>>>>         processor_type and arch_name enum types.
>>>> 	* config/arm/parsecpu.awk: Likewise.
>>>> 	* doc/options.texi: Document new flag ForceHelp.
>>>> 	* opt-read.awk: Parse ForceHelp and set it in construction.
>>>> 	* optc-gen.awk: Likewise.
>>>> 	* opts.c (print_filtered_help): Handle force_help option.
>>>> 	* opts.h (struct cl_enum): New field force_help.
>>>> ---
>>>>  gcc/config/arm/arm-tables.opt | 4 ++--
>>>>  gcc/config/arm/parsecpu.awk   | 4 ++--
>>>>  gcc/doc/options.texi          | 4 ++++
>>>>  gcc/opt-read.awk              | 3 +++
>>>>  gcc/optc-gen.awk              | 3 ++-
>>>>  gcc/opts.c                    | 3 ++-
>>>>  gcc/opts.h                    | 3 +++
>>>>  7 files changed, 18 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
>>>> index eacee746a39..c74229e27d7 100644
>>>> --- a/gcc/config/arm/arm-tables.opt
>>>> +++ b/gcc/config/arm/arm-tables.opt
>>>> @@ -21,7 +21,7 @@
>>>>  ; <http://www.gnu.org/licenses/>.
>>>>  
>>>>  Enum
>>>> -Name(processor_type) Type(enum processor_type)
>>>> +Name(processor_type) Type(enum processor_type) ForceHelp
>>>>  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
>>>>  
>>>>  EnumValue
>>>> @@ -298,7 +298,7 @@ EnumValue
>>>>  Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
>>>>  
>>>>  Enum
>>>> -Name(arm_arch) Type(int)
>>>> +Name(arm_arch) Type(int) ForceHelp
>>>>  Known ARM architectures (for use with the -march= option):
>>>>  
>>>>  EnumValue
>>>> diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
>>>> index aabe1b0c64c..c499a5ed0ce 100644
>>>> --- a/gcc/config/arm/parsecpu.awk
>>>> +++ b/gcc/config/arm/parsecpu.awk
>>>> @@ -441,7 +441,7 @@ function gen_opt () {
>>>>      boilerplate("md")
>>>>  
>>>>      print "Enum"
>>>> -    print "Name(processor_type) Type(enum processor_type)"
>>>> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
>>>>      print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
>>>>  
>>>>      ncpus = split (cpu_list, cpus)
>>>> @@ -454,7 +454,7 @@ function gen_opt () {
>>>>      }
>>>>  
>>>>      print "Enum"
>>>> -    print "Name(arm_arch) Type(int)"
>>>> +    print "Name(arm_arch) Type(int) ForceHelp"
>>>>      print "Known ARM architectures (for use with the -march= option):\n"
>>>>  
>>>>      narchs = split (arch_list, archs)
>>>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>>>> index b3ca9f6fce6..af77ad78e8c 100644
>>>> --- a/gcc/doc/options.texi
>>>> +++ b/gcc/doc/options.texi
>>>> @@ -120,6 +120,10 @@ being described by this record.
>>>>  This property is required; it says what value (representable as
>>>>  @code{int}) should be used for the given string.
>>>>  
>>>> +@item ForceHelp
>>>> +This property is optional.  If present, enum values are printed
>>>> +in @option{--help} output.
>>>> +
>>>>  @item Canonical
>>>>  This property is optional.  If present, it says the present string is
>>>>  the canonical one among all those with the given value.  Other strings
>>>> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>>>> index 2072958e6ba..6d2be9e99d7 100644
>>>> --- a/gcc/opt-read.awk
>>>> +++ b/gcc/opt-read.awk
>>>> @@ -89,6 +89,9 @@ BEGIN {
>>>>  			enum_index[name] = n_enums
>>>>  			enum_unknown_error[name] = unknown_error
>>>>  			enum_help[name] = $3
>>>> +			enum_force_help[name] = test_flag("ForceHelp", props, "true")
>>>> +			if (enum_force_help[name] == "")
>>>> +			  enum_force_help[name] = "false"
>>>>  			n_enums++
>>>>  		}
>>>>  		else if ($1 == "EnumValue")  {
>>>> diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
>>>> index bf177e86330..5c4f4239db0 100644
>>>> --- a/gcc/optc-gen.awk
>>>> +++ b/gcc/optc-gen.awk
>>>> @@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
>>>>  	print "    cl_enum_" name "_data,"
>>>>  	print "    sizeof (" enum_type[name] "),"
>>>>  	print "    cl_enum_" name "_set,"
>>>> -	print "    cl_enum_" name "_get"
>>>> +	print "    cl_enum_" name "_get,"
>>>> +	print "    " enum_force_help[name]
>>>>  	print "  },"
>>>>  }
>>>>  print "};"
>>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>>> index b8ae8756b4f..214ef806cd5 100644
>>>> --- a/gcc/opts.c
>>>> +++ b/gcc/opts.c
>>>> @@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
>>>>      {
>>>>        unsigned int j, pos;
>>>>  
>>>> -      if (opts->x_help_enum_printed[i] != 1)
>>>> +      if (opts->x_help_enum_printed[i] != 1
>>>> +	  && !cl_enums[i].force_help)
>>>>  	continue;
>>>>        if (cl_enums[i].help == NULL)
>>>>  	continue;
>>>> diff --git a/gcc/opts.h b/gcc/opts.h
>>>> index 3723bdbf95b..c8777b3cd6a 100644
>>>> --- a/gcc/opts.h
>>>> +++ b/gcc/opts.h
>>>> @@ -193,6 +193,9 @@ struct cl_enum
>>>>  
>>>>    /* Function to get the value of a variable of this type.  */
>>>>    int (*get) (const void *var);
>>>> +
>>>> +  /* Force enum to be printed in help.  */
>>>> +  bool force_help;
>>>>  };
>>>>  
>>>>  extern const struct cl_enum cl_enums[];
>>>>
>>>
>>
>>
>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe.patch
>>
>>
>> From dcb80bbe7b82388f5c7147320d509d6e5a687033 Mon Sep 17 00:00:00 2001
>> From: marxin <mliska@suse.cz>
>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>  arm32 (PR driver/83193).
>>
>> gcc/ChangeLog:
>>
>> 2018-07-19  Martin Liska  <mliska@suse.cz>
>>
>> 	* config/arm/arm.opt: Use HelpEnum flag.
>> 	* doc/options.texi: Document it.
>> 	* opt-functions.awk: Parse HelpEnum and fill up
>>         proper index into enum list.
>> 	* opts.c (print_filtered_help): Mention also enums
>>         that are not directly, but mentioned in HelpEnum.
>> 	* opts.h (struct cl_option): Add new field var_enum_help
>>         and change var_enum to signed version.
>> ---
>>  gcc/config/arm/arm.opt |  6 +++---
>>  gcc/doc/options.texi   |  5 +++++
>>  gcc/opt-functions.awk  | 25 +++++++++++++++----------
>>  gcc/opts.c             |  3 +++
>>  gcc/opts.h             |  5 ++++-
>>  5 files changed, 30 insertions(+), 14 deletions(-)
>>
>> diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
>> index a1286a4a861..f182208edd1 100644
>> --- a/gcc/config/arm/arm.opt
>> +++ b/gcc/config/arm/arm.opt
>> @@ -82,7 +82,7 @@ mapcs-stack-check
>>  Target Report Mask(APCS_STACK) Undocumented
>>  
>>  march=
>> -Target RejectNegative ToLower Joined Var(arm_arch_string)
>> +Target RejectNegative ToLower Joined Var(arm_arch_string) HelpEnum(arm_arch)
>>  Specify the name of the target architecture.
>>  
>>  ; Other arm_arch values are loaded from arm-tables.opt
>> @@ -107,7 +107,7 @@ Target Report Mask(CALLER_INTERWORKING)
>>  Thumb: Assume function pointers may go to non-Thumb aware code.
>>  
>>  mcpu=
>> -Target RejectNegative ToLower Joined Var(arm_cpu_string)
>> +Target RejectNegative ToLower Joined Var(arm_cpu_string) HelpEnum(processor_type)
>>  Specify the name of the target CPU.
>>  
>>  mfloat-abi=
>> @@ -232,7 +232,7 @@ Target Report Mask(TPCS_LEAF_FRAME)
>>  Thumb: Generate (leaf) stack frames even if not needed.
>>  
>>  mtune=
>> -Target RejectNegative ToLower Joined Var(arm_tune_string)
>> +Target RejectNegative ToLower Joined Var(arm_tune_string) HelpEnum(processor_type)
>>  Tune code for the given processor.
>>  
>>  mprint-tune-info
>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>> index b3ca9f6fce6..e234cc809d5 100644
>> --- a/gcc/doc/options.texi
>> +++ b/gcc/doc/options.texi
>> @@ -120,6 +120,11 @@ being described by this record.
>>  This property is required; it says what value (representable as
>>  @code{int}) should be used for the given string.
>>  
>> +@item EnumHelp(@var{name})
>> +Some string options accept enum values as arguments.
>> +When using @samp{EnumHelp}, list of possible values is listed
>> +in @option{--help} output.
>> +
>>  @item Canonical
>>  This property is optional.  If present, it says the present string is
>>  the canonical one among all those with the given value.  Other strings
>> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
>> index 2c371e5a23a..9737b6b115b 100644
>> --- a/gcc/opt-functions.awk
>> +++ b/gcc/opt-functions.awk
>> @@ -232,37 +232,42 @@ function var_type_struct(flags)
>>  }
>>  
>>  # Given that an option has flags FLAGS, return an initializer for the
>> -# "var_enum", "var_type" and "var_value" fields of its cl_options[] entry.
>> +# "var_enum", "var_enum_help", "var_type" and "var_value" fields of its cl_options[] entry.
>>  function var_set(flags)
>>  {
>> +  help_enum_index = "-1"
>> +	if (flag_set_p("HelpEnum.*", flags)) {
>> +		help_enum_index = enum_index[opt_args("HelpEnum", flags)];
>> +	}
>> +
>>  	if (flag_set_p("Defer", flags))
>> -		return "0, CLVC_DEFER, 0"
>> +		return "-1, -1, CLVC_DEFER, 0"
>>  	s = nth_arg(1, opt_args("Var", flags))
>>  	if (s != "")
>> -		return "0, CLVC_EQUAL, " s
>> +		return "-1, -1, CLVC_EQUAL, " s
>>  	s = opt_args("Mask", flags);
>>  	if (s != "") {
>>  		vn = var_name(flags);
>>  		if (vn)
>> -			return "0, CLVC_BIT_SET, OPTION_MASK_" s
>> +			return "-1, -1, CLVC_BIT_SET, OPTION_MASK_" s
>>  		else
>> -			return "0, CLVC_BIT_SET, MASK_" s
>> +			return "-1, -1, CLVC_BIT_SET, MASK_" s
>>  	}
>>  	s = nth_arg(0, opt_args("InverseMask", flags));
>>  	if (s != "") {
>>  		vn = var_name(flags);
>>  		if (vn)
>> -			return "0, CLVC_BIT_CLEAR, OPTION_MASK_" s
>> +			return "-1, -1, CLVC_BIT_CLEAR, OPTION_MASK_" s
>>  		else
>> -			return "0, CLVC_BIT_CLEAR, MASK_" s
>> +			return "-1, -1, CLVC_BIT_CLEAR, MASK_" s
>>  	}
>>  	if (flag_set_p("Enum.*", flags)) {
>>  		en = opt_args("Enum", flags);
>> -		return enum_index[en] ", CLVC_ENUM, 0"
>> +		return enum_index[en] ", -1, CLVC_ENUM, 0"
>>  	}
>>  	if (var_type(flags) == "const char *")
>> -		return "0, CLVC_STRING, 0"
>> -	return "0, CLVC_BOOLEAN, 0"
>> +		return "-1, " help_enum_index ", CLVC_STRING, 0"
>> +	return "-1, -1, CLVC_BOOLEAN, 0"
>>  }
>>  
>>  # Given that an option called NAME has flags FLAGS, return an initializer
>> diff --git a/gcc/opts.c b/gcc/opts.c
>> index b8ae8756b4f..37e779e8732 100644
>> --- a/gcc/opts.c
>> +++ b/gcc/opts.c
>> @@ -1303,6 +1303,9 @@ print_filtered_help (unsigned int include_flags,
>>        if (option->var_type == CLVC_ENUM
>>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>>  	opts->x_help_enum_printed[option->var_enum] = 1;
>> +      else if (option->var_enum_help != -1
>> +	       && opts->x_help_enum_printed[option->var_enum_help] != 2)
>> +	opts->x_help_enum_printed[option->var_enum_help] = 1;
>>      }
>>  
>>    if (! found)
>> diff --git a/gcc/opts.h b/gcc/opts.h
>> index 3723bdbf95b..ba79a36d7ab 100644
>> --- a/gcc/opts.h
>> +++ b/gcc/opts.h
>> @@ -107,7 +107,10 @@ struct cl_option
>>    unsigned short flag_var_offset;
>>    /* Index in cl_enums of enum used for this option's arguments, for
>>       CLVC_ENUM options.  */
>> -  unsigned short var_enum;
>> +  short var_enum;
>> +  /* Index in cl_enums of enum used for string options which
>> +     have strings as possible values.  */
>> +  short var_enum_help;
>>    /* How this option's value is determined and sets a field.  */
>>    enum cl_var_type var_type;
>>    /* Value or bit-mask with which to set a field.  */
>>
> 

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Richard Earnshaw (lists)]

On 19/07/18 11:22, Martin Liška wrote:
> On 07/19/2018 12:01 PM, Richard Earnshaw (lists) wrote:
>> On 19/07/18 10:56, Martin Liška wrote:
>>> On 07/19/2018 11:28 AM, Richard Earnshaw (lists) wrote:
>>>> On 19/07/18 08:30, Martin Liška wrote:
>>>>> This is correct version of the patch. Anyway, I'm thinking about the ForceHelp
>>>>> attribute. I may do it in a bit different version. Let me come up with one another
>>>>> version of the patch.
>>>>>
>>>>> Martin
>>>>>
>>>>
>>>> I don't understand how this is supposed to work.  -mcpu, -march and
>>>> -mtune all take strings now and have to be parsed to identify various
>>>> sub-components of the parameter.  So why do you talk about these being
>>>> enum types?
>>>
>>> Yes, they are string types. But for purpose of --help output, it's nice
>>> to present to a user a list of possible values. That's the enum type.
>>>
>>> Please take a look at attached patch.
>>>
>>
>> But that isn't the list of possible values.  Please see the manual.  A
>> valid CPU name can look something like
>>
>> 	cortex-a53+crypto
>>
>> and architectures names can be even more complex.
>>
>> You can't get this from that list of enum values.
> 
> I'm fully aware of the limitation, it's questionable whether you want to get:
> 
> @@ -56,6 +56,9 @@
>    Known ARM ABIs (for use with the -mabi= option):
>      aapcs aapcs-linux apcs-gnu atpcs iwmmxt
>  
> +  Known ARM architectures (for use with the -march= option):
> +    armv4 armv4t armv5t armv5te armv5tej armv6 armv6-m armv6j armv6k armv6kz armv6s-m armv6t2 armv6z armv6zk armv7 armv7-a armv7-m armv7-r armv7e-m armv7ve armv8-a armv8-m.base armv8-m.main armv8-r armv8.1-a armv8.2-a armv8.3-a armv8.4-a iwmmxt iwmmxt2 native
> +
>    Known __fp16 formats (for use with the -mfp16-format= option):
>      alternative ieee none
>  
> @@ -68,6 +71,12 @@
>    Known floating-point ABIs (for use with the -mfloat-abi= option):
>      hard soft softfp
>  
> +  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
> +    arm1020e arm1020t arm1022e arm1026ej-s arm10e arm10tdmi arm1136j-s arm1136jf-s arm1156t2-s arm1156t2f-s arm1176jz-s arm1176jzf-s arm710t arm720t arm740t arm7tdmi arm7tdmi-s arm8 arm810 arm9 arm920 arm920t arm922t arm926ej-s arm940t arm946e-s arm966e-s arm968e-s arm9e
> +    arm9tdmi cortex-a12 cortex-a15 cortex-a15.cortex-a7 cortex-a17 cortex-a17.cortex-a7 cortex-a32 cortex-a35 cortex-a5 cortex-a53 cortex-a55 cortex-a57 cortex-a57.cortex-a53 cortex-a7 cortex-a72 cortex-a72.cortex-a53 cortex-a73 cortex-a73.cortex-a35 cortex-a73.cortex-a53
> +    cortex-a75 cortex-a75.cortex-a55 cortex-a76 cortex-a76.cortex-a55 cortex-a8 cortex-a9 cortex-m0 cortex-m0.small-multiply cortex-m0plus cortex-m0plus.small-multiply cortex-m1 cortex-m1.small-multiply cortex-m23 cortex-m3 cortex-m33 cortex-m4 cortex-m7 cortex-r4
> +    cortex-r4f cortex-r5 cortex-r52 cortex-r7 cortex-r8 ep9312 exynos-m1 fa526 fa606te fa626 fa626te fa726te fmp626 generic-armv7-a iwmmxt iwmmxt2 marvell-pj4 mpcore mpcorenovfp native strongarm strongarm110 strongarm1100 strongarm1110 xgene1 xscale
> +
>    TLS dialect to use:
>      gnu gnu2
> 
> I hope it's still beneficial for users.

Frankly, I find the list too long to be helpful.  I'd also prefer it if
we could come up with a more useful approach.  I've pondered if the
following were possible:

In general target help, print

	For list of supported CPUs [Architectures] use -mcpu=help [-march=help]

And then, invoking the compiler gives that list in a more user-friendly
fashion.  Finally, at the end we could have:

For CPU [Architecture]-specific extensions use -mcpu=<cpuname>+help
[-march=<archname>+help]

and then it would show the specific extensions for that architecture.

It's relatively straight forward to do the back-end plumbing for this,
but the help driver would have to know how to call into the back-end or
for the back-end to be able to report to the midend that this was a help
invocation not a normal run.  I couldn't find a simple way of doing that
when I tried before.

R.

> 
> Martin
> 
>>
>> R.
>>
>>> Thanks,
>>> Martin
>>>
>>>>
>>>> R.
>>>>
>>>>>
>>>>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v3.patch
>>>>>
>>>>>
>>>>> From 9bfc1400213911b4508e90198df7b2dd11efc85c Mon Sep 17 00:00:00 2001
>>>>> From: marxin <mliska@suse.cz>
>>>>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>>>>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>>>>  arm32 (PR driver/83193).
>>>>>
>>>>> gcc/ChangeLog:
>>>>>
>>>>> 2018-07-18  Martin Liska  <mliska@suse.cz>
>>>>>
>>>>>         PR driver/83193
>>>>> 	* config/arm/arm-tables.opt: Add ForceHelp flag for
>>>>>         processor_type and arch_name enum types.
>>>>> 	* config/arm/parsecpu.awk: Likewise.
>>>>> 	* doc/options.texi: Document new flag ForceHelp.
>>>>> 	* opt-read.awk: Parse ForceHelp and set it in construction.
>>>>> 	* optc-gen.awk: Likewise.
>>>>> 	* opts.c (print_filtered_help): Handle force_help option.
>>>>> 	* opts.h (struct cl_enum): New field force_help.
>>>>> ---
>>>>>  gcc/config/arm/arm-tables.opt | 4 ++--
>>>>>  gcc/config/arm/parsecpu.awk   | 4 ++--
>>>>>  gcc/doc/options.texi          | 4 ++++
>>>>>  gcc/opt-read.awk              | 3 +++
>>>>>  gcc/optc-gen.awk              | 3 ++-
>>>>>  gcc/opts.c                    | 3 ++-
>>>>>  gcc/opts.h                    | 3 +++
>>>>>  7 files changed, 18 insertions(+), 6 deletions(-)
>>>>>
>>>>> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
>>>>> index eacee746a39..c74229e27d7 100644
>>>>> --- a/gcc/config/arm/arm-tables.opt
>>>>> +++ b/gcc/config/arm/arm-tables.opt
>>>>> @@ -21,7 +21,7 @@
>>>>>  ; <http://www.gnu.org/licenses/>.
>>>>>  
>>>>>  Enum
>>>>> -Name(processor_type) Type(enum processor_type)
>>>>> +Name(processor_type) Type(enum processor_type) ForceHelp
>>>>>  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
>>>>>  
>>>>>  EnumValue
>>>>> @@ -298,7 +298,7 @@ EnumValue
>>>>>  Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
>>>>>  
>>>>>  Enum
>>>>> -Name(arm_arch) Type(int)
>>>>> +Name(arm_arch) Type(int) ForceHelp
>>>>>  Known ARM architectures (for use with the -march= option):
>>>>>  
>>>>>  EnumValue
>>>>> diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
>>>>> index aabe1b0c64c..c499a5ed0ce 100644
>>>>> --- a/gcc/config/arm/parsecpu.awk
>>>>> +++ b/gcc/config/arm/parsecpu.awk
>>>>> @@ -441,7 +441,7 @@ function gen_opt () {
>>>>>      boilerplate("md")
>>>>>  
>>>>>      print "Enum"
>>>>> -    print "Name(processor_type) Type(enum processor_type)"
>>>>> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
>>>>>      print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
>>>>>  
>>>>>      ncpus = split (cpu_list, cpus)
>>>>> @@ -454,7 +454,7 @@ function gen_opt () {
>>>>>      }
>>>>>  
>>>>>      print "Enum"
>>>>> -    print "Name(arm_arch) Type(int)"
>>>>> +    print "Name(arm_arch) Type(int) ForceHelp"
>>>>>      print "Known ARM architectures (for use with the -march= option):\n"
>>>>>  
>>>>>      narchs = split (arch_list, archs)
>>>>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>>>>> index b3ca9f6fce6..af77ad78e8c 100644
>>>>> --- a/gcc/doc/options.texi
>>>>> +++ b/gcc/doc/options.texi
>>>>> @@ -120,6 +120,10 @@ being described by this record.
>>>>>  This property is required; it says what value (representable as
>>>>>  @code{int}) should be used for the given string.
>>>>>  
>>>>> +@item ForceHelp
>>>>> +This property is optional.  If present, enum values are printed
>>>>> +in @option{--help} output.
>>>>> +
>>>>>  @item Canonical
>>>>>  This property is optional.  If present, it says the present string is
>>>>>  the canonical one among all those with the given value.  Other strings
>>>>> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>>>>> index 2072958e6ba..6d2be9e99d7 100644
>>>>> --- a/gcc/opt-read.awk
>>>>> +++ b/gcc/opt-read.awk
>>>>> @@ -89,6 +89,9 @@ BEGIN {
>>>>>  			enum_index[name] = n_enums
>>>>>  			enum_unknown_error[name] = unknown_error
>>>>>  			enum_help[name] = $3
>>>>> +			enum_force_help[name] = test_flag("ForceHelp", props, "true")
>>>>> +			if (enum_force_help[name] == "")
>>>>> +			  enum_force_help[name] = "false"
>>>>>  			n_enums++
>>>>>  		}
>>>>>  		else if ($1 == "EnumValue")  {
>>>>> diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
>>>>> index bf177e86330..5c4f4239db0 100644
>>>>> --- a/gcc/optc-gen.awk
>>>>> +++ b/gcc/optc-gen.awk
>>>>> @@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
>>>>>  	print "    cl_enum_" name "_data,"
>>>>>  	print "    sizeof (" enum_type[name] "),"
>>>>>  	print "    cl_enum_" name "_set,"
>>>>> -	print "    cl_enum_" name "_get"
>>>>> +	print "    cl_enum_" name "_get,"
>>>>> +	print "    " enum_force_help[name]
>>>>>  	print "  },"
>>>>>  }
>>>>>  print "};"
>>>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>>>> index b8ae8756b4f..214ef806cd5 100644
>>>>> --- a/gcc/opts.c
>>>>> +++ b/gcc/opts.c
>>>>> @@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
>>>>>      {
>>>>>        unsigned int j, pos;
>>>>>  
>>>>> -      if (opts->x_help_enum_printed[i] != 1)
>>>>> +      if (opts->x_help_enum_printed[i] != 1
>>>>> +	  && !cl_enums[i].force_help)
>>>>>  	continue;
>>>>>        if (cl_enums[i].help == NULL)
>>>>>  	continue;
>>>>> diff --git a/gcc/opts.h b/gcc/opts.h
>>>>> index 3723bdbf95b..c8777b3cd6a 100644
>>>>> --- a/gcc/opts.h
>>>>> +++ b/gcc/opts.h
>>>>> @@ -193,6 +193,9 @@ struct cl_enum
>>>>>  
>>>>>    /* Function to get the value of a variable of this type.  */
>>>>>    int (*get) (const void *var);
>>>>> +
>>>>> +  /* Force enum to be printed in help.  */
>>>>> +  bool force_help;
>>>>>  };
>>>>>  
>>>>>  extern const struct cl_enum cl_enums[];
>>>>>
>>>>
>>>
>>>
>>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe.patch
>>>
>>>
>>> From dcb80bbe7b82388f5c7147320d509d6e5a687033 Mon Sep 17 00:00:00 2001
>>> From: marxin <mliska@suse.cz>
>>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>>  arm32 (PR driver/83193).
>>>
>>> gcc/ChangeLog:
>>>
>>> 2018-07-19  Martin Liska  <mliska@suse.cz>
>>>
>>> 	* config/arm/arm.opt: Use HelpEnum flag.
>>> 	* doc/options.texi: Document it.
>>> 	* opt-functions.awk: Parse HelpEnum and fill up
>>>         proper index into enum list.
>>> 	* opts.c (print_filtered_help): Mention also enums
>>>         that are not directly, but mentioned in HelpEnum.
>>> 	* opts.h (struct cl_option): Add new field var_enum_help
>>>         and change var_enum to signed version.
>>> ---
>>>  gcc/config/arm/arm.opt |  6 +++---
>>>  gcc/doc/options.texi   |  5 +++++
>>>  gcc/opt-functions.awk  | 25 +++++++++++++++----------
>>>  gcc/opts.c             |  3 +++
>>>  gcc/opts.h             |  5 ++++-
>>>  5 files changed, 30 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
>>> index a1286a4a861..f182208edd1 100644
>>> --- a/gcc/config/arm/arm.opt
>>> +++ b/gcc/config/arm/arm.opt
>>> @@ -82,7 +82,7 @@ mapcs-stack-check
>>>  Target Report Mask(APCS_STACK) Undocumented
>>>  
>>>  march=
>>> -Target RejectNegative ToLower Joined Var(arm_arch_string)
>>> +Target RejectNegative ToLower Joined Var(arm_arch_string) HelpEnum(arm_arch)
>>>  Specify the name of the target architecture.
>>>  
>>>  ; Other arm_arch values are loaded from arm-tables.opt
>>> @@ -107,7 +107,7 @@ Target Report Mask(CALLER_INTERWORKING)
>>>  Thumb: Assume function pointers may go to non-Thumb aware code.
>>>  
>>>  mcpu=
>>> -Target RejectNegative ToLower Joined Var(arm_cpu_string)
>>> +Target RejectNegative ToLower Joined Var(arm_cpu_string) HelpEnum(processor_type)
>>>  Specify the name of the target CPU.
>>>  
>>>  mfloat-abi=
>>> @@ -232,7 +232,7 @@ Target Report Mask(TPCS_LEAF_FRAME)
>>>  Thumb: Generate (leaf) stack frames even if not needed.
>>>  
>>>  mtune=
>>> -Target RejectNegative ToLower Joined Var(arm_tune_string)
>>> +Target RejectNegative ToLower Joined Var(arm_tune_string) HelpEnum(processor_type)
>>>  Tune code for the given processor.
>>>  
>>>  mprint-tune-info
>>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>>> index b3ca9f6fce6..e234cc809d5 100644
>>> --- a/gcc/doc/options.texi
>>> +++ b/gcc/doc/options.texi
>>> @@ -120,6 +120,11 @@ being described by this record.
>>>  This property is required; it says what value (representable as
>>>  @code{int}) should be used for the given string.
>>>  
>>> +@item EnumHelp(@var{name})
>>> +Some string options accept enum values as arguments.
>>> +When using @samp{EnumHelp}, list of possible values is listed
>>> +in @option{--help} output.
>>> +
>>>  @item Canonical
>>>  This property is optional.  If present, it says the present string is
>>>  the canonical one among all those with the given value.  Other strings
>>> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
>>> index 2c371e5a23a..9737b6b115b 100644
>>> --- a/gcc/opt-functions.awk
>>> +++ b/gcc/opt-functions.awk
>>> @@ -232,37 +232,42 @@ function var_type_struct(flags)
>>>  }
>>>  
>>>  # Given that an option has flags FLAGS, return an initializer for the
>>> -# "var_enum", "var_type" and "var_value" fields of its cl_options[] entry.
>>> +# "var_enum", "var_enum_help", "var_type" and "var_value" fields of its cl_options[] entry.
>>>  function var_set(flags)
>>>  {
>>> +  help_enum_index = "-1"
>>> +	if (flag_set_p("HelpEnum.*", flags)) {
>>> +		help_enum_index = enum_index[opt_args("HelpEnum", flags)];
>>> +	}
>>> +
>>>  	if (flag_set_p("Defer", flags))
>>> -		return "0, CLVC_DEFER, 0"
>>> +		return "-1, -1, CLVC_DEFER, 0"
>>>  	s = nth_arg(1, opt_args("Var", flags))
>>>  	if (s != "")
>>> -		return "0, CLVC_EQUAL, " s
>>> +		return "-1, -1, CLVC_EQUAL, " s
>>>  	s = opt_args("Mask", flags);
>>>  	if (s != "") {
>>>  		vn = var_name(flags);
>>>  		if (vn)
>>> -			return "0, CLVC_BIT_SET, OPTION_MASK_" s
>>> +			return "-1, -1, CLVC_BIT_SET, OPTION_MASK_" s
>>>  		else
>>> -			return "0, CLVC_BIT_SET, MASK_" s
>>> +			return "-1, -1, CLVC_BIT_SET, MASK_" s
>>>  	}
>>>  	s = nth_arg(0, opt_args("InverseMask", flags));
>>>  	if (s != "") {
>>>  		vn = var_name(flags);
>>>  		if (vn)
>>> -			return "0, CLVC_BIT_CLEAR, OPTION_MASK_" s
>>> +			return "-1, -1, CLVC_BIT_CLEAR, OPTION_MASK_" s
>>>  		else
>>> -			return "0, CLVC_BIT_CLEAR, MASK_" s
>>> +			return "-1, -1, CLVC_BIT_CLEAR, MASK_" s
>>>  	}
>>>  	if (flag_set_p("Enum.*", flags)) {
>>>  		en = opt_args("Enum", flags);
>>> -		return enum_index[en] ", CLVC_ENUM, 0"
>>> +		return enum_index[en] ", -1, CLVC_ENUM, 0"
>>>  	}
>>>  	if (var_type(flags) == "const char *")
>>> -		return "0, CLVC_STRING, 0"
>>> -	return "0, CLVC_BOOLEAN, 0"
>>> +		return "-1, " help_enum_index ", CLVC_STRING, 0"
>>> +	return "-1, -1, CLVC_BOOLEAN, 0"
>>>  }
>>>  
>>>  # Given that an option called NAME has flags FLAGS, return an initializer
>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>> index b8ae8756b4f..37e779e8732 100644
>>> --- a/gcc/opts.c
>>> +++ b/gcc/opts.c
>>> @@ -1303,6 +1303,9 @@ print_filtered_help (unsigned int include_flags,
>>>        if (option->var_type == CLVC_ENUM
>>>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>>>  	opts->x_help_enum_printed[option->var_enum] = 1;
>>> +      else if (option->var_enum_help != -1
>>> +	       && opts->x_help_enum_printed[option->var_enum_help] != 2)
>>> +	opts->x_help_enum_printed[option->var_enum_help] = 1;
>>>      }
>>>  
>>>    if (! found)
>>> diff --git a/gcc/opts.h b/gcc/opts.h
>>> index 3723bdbf95b..ba79a36d7ab 100644
>>> --- a/gcc/opts.h
>>> +++ b/gcc/opts.h
>>> @@ -107,7 +107,10 @@ struct cl_option
>>>    unsigned short flag_var_offset;
>>>    /* Index in cl_enums of enum used for this option's arguments, for
>>>       CLVC_ENUM options.  */
>>> -  unsigned short var_enum;
>>> +  short var_enum;
>>> +  /* Index in cl_enums of enum used for string options which
>>> +     have strings as possible values.  */
>>> +  short var_enum_help;
>>>    /* How this option's value is determined and sets a field.  */
>>>    enum cl_var_type var_type;
>>>    /* Value or bit-mask with which to set a field.  */
>>>
>>
> 

Re: [PATCH] Show valid options for -march and -mtune in --help=target for arm32 (PR driver/83193).

[Martin Liška]

On 07/19/2018 12:31 PM, Richard Earnshaw (lists) wrote:
> On 19/07/18 11:22, Martin Liška wrote:
>> On 07/19/2018 12:01 PM, Richard Earnshaw (lists) wrote:
>>> On 19/07/18 10:56, Martin Liška wrote:
>>>> On 07/19/2018 11:28 AM, Richard Earnshaw (lists) wrote:
>>>>> On 19/07/18 08:30, Martin Liška wrote:
>>>>>> This is correct version of the patch. Anyway, I'm thinking about the ForceHelp
>>>>>> attribute. I may do it in a bit different version. Let me come up with one another
>>>>>> version of the patch.
>>>>>>
>>>>>> Martin
>>>>>>
>>>>>
>>>>> I don't understand how this is supposed to work.  -mcpu, -march and
>>>>> -mtune all take strings now and have to be parsed to identify various
>>>>> sub-components of the parameter.  So why do you talk about these being
>>>>> enum types?
>>>>
>>>> Yes, they are string types. But for purpose of --help output, it's nice
>>>> to present to a user a list of possible values. That's the enum type.
>>>>
>>>> Please take a look at attached patch.
>>>>
>>>
>>> But that isn't the list of possible values.  Please see the manual.  A
>>> valid CPU name can look something like
>>>
>>> 	cortex-a53+crypto
>>>
>>> and architectures names can be even more complex.
>>>
>>> You can't get this from that list of enum values.
>>
>> I'm fully aware of the limitation, it's questionable whether you want to get:
>>
>> @@ -56,6 +56,9 @@
>>    Known ARM ABIs (for use with the -mabi= option):
>>      aapcs aapcs-linux apcs-gnu atpcs iwmmxt
>>  
>> +  Known ARM architectures (for use with the -march= option):
>> +    armv4 armv4t armv5t armv5te armv5tej armv6 armv6-m armv6j armv6k armv6kz armv6s-m armv6t2 armv6z armv6zk armv7 armv7-a armv7-m armv7-r armv7e-m armv7ve armv8-a armv8-m.base armv8-m.main armv8-r armv8.1-a armv8.2-a armv8.3-a armv8.4-a iwmmxt iwmmxt2 native
>> +
>>    Known __fp16 formats (for use with the -mfp16-format= option):
>>      alternative ieee none
>>  
>> @@ -68,6 +71,12 @@
>>    Known floating-point ABIs (for use with the -mfloat-abi= option):
>>      hard soft softfp
>>  
>> +  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
>> +    arm1020e arm1020t arm1022e arm1026ej-s arm10e arm10tdmi arm1136j-s arm1136jf-s arm1156t2-s arm1156t2f-s arm1176jz-s arm1176jzf-s arm710t arm720t arm740t arm7tdmi arm7tdmi-s arm8 arm810 arm9 arm920 arm920t arm922t arm926ej-s arm940t arm946e-s arm966e-s arm968e-s arm9e
>> +    arm9tdmi cortex-a12 cortex-a15 cortex-a15.cortex-a7 cortex-a17 cortex-a17.cortex-a7 cortex-a32 cortex-a35 cortex-a5 cortex-a53 cortex-a55 cortex-a57 cortex-a57.cortex-a53 cortex-a7 cortex-a72 cortex-a72.cortex-a53 cortex-a73 cortex-a73.cortex-a35 cortex-a73.cortex-a53
>> +    cortex-a75 cortex-a75.cortex-a55 cortex-a76 cortex-a76.cortex-a55 cortex-a8 cortex-a9 cortex-m0 cortex-m0.small-multiply cortex-m0plus cortex-m0plus.small-multiply cortex-m1 cortex-m1.small-multiply cortex-m23 cortex-m3 cortex-m33 cortex-m4 cortex-m7 cortex-r4
>> +    cortex-r4f cortex-r5 cortex-r52 cortex-r7 cortex-r8 ep9312 exynos-m1 fa526 fa606te fa626 fa626te fa726te fmp626 generic-armv7-a iwmmxt iwmmxt2 marvell-pj4 mpcore mpcorenovfp native strongarm strongarm110 strongarm1100 strongarm1110 xgene1 xscale
>> +
>>    TLS dialect to use:
>>      gnu gnu2
>>
>> I hope it's still beneficial for users.
> 
> Frankly, I find the list too long to be helpful.  I'd also prefer it if

One justification for this can be that with a very simple patch and
can have bash completion to finish a -march option value.

> we could come up with a more useful approach.  I've pondered if the
> following were possible:
> 
> In general target help, print
> 
> 	For list of supported CPUs [Architectures] use -mcpu=help [-march=help]
> 
> And then, invoking the compiler gives that list in a more user-friendly
> fashion.  Finally, at the end we could have:
> 
> For CPU [Architecture]-specific extensions use -mcpu=<cpuname>+help
> [-march=<archname>+help]
> 
> and then it would show the specific extensions for that architecture.
> 
> It's relatively straight forward to do the back-end plumbing for this,
> but the help driver would have to know how to call into the back-end or
> for the back-end to be able to report to the midend that this was a help
> invocation not a normal run.  I couldn't find a simple way of doing that
> when I tried before.

Would you be able to implement that as target_common hook? These are defined
in gcc/common/common-target.def. If so, I can then provide an API that
will use it.

Martin


> 
> R.
> 
>>
>> Martin
>>
>>>
>>> R.
>>>
>>>> Thanks,
>>>> Martin
>>>>
>>>>>
>>>>> R.
>>>>>
>>>>>>
>>>>>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe-v3.patch
>>>>>>
>>>>>>
>>>>>> From 9bfc1400213911b4508e90198df7b2dd11efc85c Mon Sep 17 00:00:00 2001
>>>>>> From: marxin <mliska@suse.cz>
>>>>>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>>>>>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>>>>>  arm32 (PR driver/83193).
>>>>>>
>>>>>> gcc/ChangeLog:
>>>>>>
>>>>>> 2018-07-18  Martin Liska  <mliska@suse.cz>
>>>>>>
>>>>>>         PR driver/83193
>>>>>> 	* config/arm/arm-tables.opt: Add ForceHelp flag for
>>>>>>         processor_type and arch_name enum types.
>>>>>> 	* config/arm/parsecpu.awk: Likewise.
>>>>>> 	* doc/options.texi: Document new flag ForceHelp.
>>>>>> 	* opt-read.awk: Parse ForceHelp and set it in construction.
>>>>>> 	* optc-gen.awk: Likewise.
>>>>>> 	* opts.c (print_filtered_help): Handle force_help option.
>>>>>> 	* opts.h (struct cl_enum): New field force_help.
>>>>>> ---
>>>>>>  gcc/config/arm/arm-tables.opt | 4 ++--
>>>>>>  gcc/config/arm/parsecpu.awk   | 4 ++--
>>>>>>  gcc/doc/options.texi          | 4 ++++
>>>>>>  gcc/opt-read.awk              | 3 +++
>>>>>>  gcc/optc-gen.awk              | 3 ++-
>>>>>>  gcc/opts.c                    | 3 ++-
>>>>>>  gcc/opts.h                    | 3 +++
>>>>>>  7 files changed, 18 insertions(+), 6 deletions(-)
>>>>>>
>>>>>> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
>>>>>> index eacee746a39..c74229e27d7 100644
>>>>>> --- a/gcc/config/arm/arm-tables.opt
>>>>>> +++ b/gcc/config/arm/arm-tables.opt
>>>>>> @@ -21,7 +21,7 @@
>>>>>>  ; <http://www.gnu.org/licenses/>.
>>>>>>  
>>>>>>  Enum
>>>>>> -Name(processor_type) Type(enum processor_type)
>>>>>> +Name(processor_type) Type(enum processor_type) ForceHelp
>>>>>>  Known ARM CPUs (for use with the -mcpu= and -mtune= options):
>>>>>>  
>>>>>>  EnumValue
>>>>>> @@ -298,7 +298,7 @@ EnumValue
>>>>>>  Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
>>>>>>  
>>>>>>  Enum
>>>>>> -Name(arm_arch) Type(int)
>>>>>> +Name(arm_arch) Type(int) ForceHelp
>>>>>>  Known ARM architectures (for use with the -march= option):
>>>>>>  
>>>>>>  EnumValue
>>>>>> diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk
>>>>>> index aabe1b0c64c..c499a5ed0ce 100644
>>>>>> --- a/gcc/config/arm/parsecpu.awk
>>>>>> +++ b/gcc/config/arm/parsecpu.awk
>>>>>> @@ -441,7 +441,7 @@ function gen_opt () {
>>>>>>      boilerplate("md")
>>>>>>  
>>>>>>      print "Enum"
>>>>>> -    print "Name(processor_type) Type(enum processor_type)"
>>>>>> +    print "Name(processor_type) Type(enum processor_type) ForceHelp"
>>>>>>      print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
>>>>>>  
>>>>>>      ncpus = split (cpu_list, cpus)
>>>>>> @@ -454,7 +454,7 @@ function gen_opt () {
>>>>>>      }
>>>>>>  
>>>>>>      print "Enum"
>>>>>> -    print "Name(arm_arch) Type(int)"
>>>>>> +    print "Name(arm_arch) Type(int) ForceHelp"
>>>>>>      print "Known ARM architectures (for use with the -march= option):\n"
>>>>>>  
>>>>>>      narchs = split (arch_list, archs)
>>>>>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>>>>>> index b3ca9f6fce6..af77ad78e8c 100644
>>>>>> --- a/gcc/doc/options.texi
>>>>>> +++ b/gcc/doc/options.texi
>>>>>> @@ -120,6 +120,10 @@ being described by this record.
>>>>>>  This property is required; it says what value (representable as
>>>>>>  @code{int}) should be used for the given string.
>>>>>>  
>>>>>> +@item ForceHelp
>>>>>> +This property is optional.  If present, enum values are printed
>>>>>> +in @option{--help} output.
>>>>>> +
>>>>>>  @item Canonical
>>>>>>  This property is optional.  If present, it says the present string is
>>>>>>  the canonical one among all those with the given value.  Other strings
>>>>>> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>>>>>> index 2072958e6ba..6d2be9e99d7 100644
>>>>>> --- a/gcc/opt-read.awk
>>>>>> +++ b/gcc/opt-read.awk
>>>>>> @@ -89,6 +89,9 @@ BEGIN {
>>>>>>  			enum_index[name] = n_enums
>>>>>>  			enum_unknown_error[name] = unknown_error
>>>>>>  			enum_help[name] = $3
>>>>>> +			enum_force_help[name] = test_flag("ForceHelp", props, "true")
>>>>>> +			if (enum_force_help[name] == "")
>>>>>> +			  enum_force_help[name] = "false"
>>>>>>  			n_enums++
>>>>>>  		}
>>>>>>  		else if ($1 == "EnumValue")  {
>>>>>> diff --git a/gcc/optc-gen.awk b/gcc/optc-gen.awk
>>>>>> index bf177e86330..5c4f4239db0 100644
>>>>>> --- a/gcc/optc-gen.awk
>>>>>> +++ b/gcc/optc-gen.awk
>>>>>> @@ -167,7 +167,8 @@ for (i = 0; i < n_enums; i++) {
>>>>>>  	print "    cl_enum_" name "_data,"
>>>>>>  	print "    sizeof (" enum_type[name] "),"
>>>>>>  	print "    cl_enum_" name "_set,"
>>>>>> -	print "    cl_enum_" name "_get"
>>>>>> +	print "    cl_enum_" name "_get,"
>>>>>> +	print "    " enum_force_help[name]
>>>>>>  	print "  },"
>>>>>>  }
>>>>>>  print "};"
>>>>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>>>>> index b8ae8756b4f..214ef806cd5 100644
>>>>>> --- a/gcc/opts.c
>>>>>> +++ b/gcc/opts.c
>>>>>> @@ -1337,7 +1337,8 @@ print_filtered_help (unsigned int include_flags,
>>>>>>      {
>>>>>>        unsigned int j, pos;
>>>>>>  
>>>>>> -      if (opts->x_help_enum_printed[i] != 1)
>>>>>> +      if (opts->x_help_enum_printed[i] != 1
>>>>>> +	  && !cl_enums[i].force_help)
>>>>>>  	continue;
>>>>>>        if (cl_enums[i].help == NULL)
>>>>>>  	continue;
>>>>>> diff --git a/gcc/opts.h b/gcc/opts.h
>>>>>> index 3723bdbf95b..c8777b3cd6a 100644
>>>>>> --- a/gcc/opts.h
>>>>>> +++ b/gcc/opts.h
>>>>>> @@ -193,6 +193,9 @@ struct cl_enum
>>>>>>  
>>>>>>    /* Function to get the value of a variable of this type.  */
>>>>>>    int (*get) (const void *var);
>>>>>> +
>>>>>> +  /* Force enum to be printed in help.  */
>>>>>> +  bool force_help;
>>>>>>  };
>>>>>>  
>>>>>>  extern const struct cl_enum cl_enums[];
>>>>>>
>>>>>
>>>>
>>>>
>>>> 0001-Show-valid-options-for-march-and-mtune-in-help-targe.patch
>>>>
>>>>
>>>> From dcb80bbe7b82388f5c7147320d509d6e5a687033 Mon Sep 17 00:00:00 2001
>>>> From: marxin <mliska@suse.cz>
>>>> Date: Tue, 20 Feb 2018 10:39:09 +0100
>>>> Subject: [PATCH] Show valid options for -march and -mtune in --help=target for
>>>>  arm32 (PR driver/83193).
>>>>
>>>> gcc/ChangeLog:
>>>>
>>>> 2018-07-19  Martin Liska  <mliska@suse.cz>
>>>>
>>>> 	* config/arm/arm.opt: Use HelpEnum flag.
>>>> 	* doc/options.texi: Document it.
>>>> 	* opt-functions.awk: Parse HelpEnum and fill up
>>>>         proper index into enum list.
>>>> 	* opts.c (print_filtered_help): Mention also enums
>>>>         that are not directly, but mentioned in HelpEnum.
>>>> 	* opts.h (struct cl_option): Add new field var_enum_help
>>>>         and change var_enum to signed version.
>>>> ---
>>>>  gcc/config/arm/arm.opt |  6 +++---
>>>>  gcc/doc/options.texi   |  5 +++++
>>>>  gcc/opt-functions.awk  | 25 +++++++++++++++----------
>>>>  gcc/opts.c             |  3 +++
>>>>  gcc/opts.h             |  5 ++++-
>>>>  5 files changed, 30 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
>>>> index a1286a4a861..f182208edd1 100644
>>>> --- a/gcc/config/arm/arm.opt
>>>> +++ b/gcc/config/arm/arm.opt
>>>> @@ -82,7 +82,7 @@ mapcs-stack-check
>>>>  Target Report Mask(APCS_STACK) Undocumented
>>>>  
>>>>  march=
>>>> -Target RejectNegative ToLower Joined Var(arm_arch_string)
>>>> +Target RejectNegative ToLower Joined Var(arm_arch_string) HelpEnum(arm_arch)
>>>>  Specify the name of the target architecture.
>>>>  
>>>>  ; Other arm_arch values are loaded from arm-tables.opt
>>>> @@ -107,7 +107,7 @@ Target Report Mask(CALLER_INTERWORKING)
>>>>  Thumb: Assume function pointers may go to non-Thumb aware code.
>>>>  
>>>>  mcpu=
>>>> -Target RejectNegative ToLower Joined Var(arm_cpu_string)
>>>> +Target RejectNegative ToLower Joined Var(arm_cpu_string) HelpEnum(processor_type)
>>>>  Specify the name of the target CPU.
>>>>  
>>>>  mfloat-abi=
>>>> @@ -232,7 +232,7 @@ Target Report Mask(TPCS_LEAF_FRAME)
>>>>  Thumb: Generate (leaf) stack frames even if not needed.
>>>>  
>>>>  mtune=
>>>> -Target RejectNegative ToLower Joined Var(arm_tune_string)
>>>> +Target RejectNegative ToLower Joined Var(arm_tune_string) HelpEnum(processor_type)
>>>>  Tune code for the given processor.
>>>>  
>>>>  mprint-tune-info
>>>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>>>> index b3ca9f6fce6..e234cc809d5 100644
>>>> --- a/gcc/doc/options.texi
>>>> +++ b/gcc/doc/options.texi
>>>> @@ -120,6 +120,11 @@ being described by this record.
>>>>  This property is required; it says what value (representable as
>>>>  @code{int}) should be used for the given string.
>>>>  
>>>> +@item EnumHelp(@var{name})
>>>> +Some string options accept enum values as arguments.
>>>> +When using @samp{EnumHelp}, list of possible values is listed
>>>> +in @option{--help} output.
>>>> +
>>>>  @item Canonical
>>>>  This property is optional.  If present, it says the present string is
>>>>  the canonical one among all those with the given value.  Other strings
>>>> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
>>>> index 2c371e5a23a..9737b6b115b 100644
>>>> --- a/gcc/opt-functions.awk
>>>> +++ b/gcc/opt-functions.awk
>>>> @@ -232,37 +232,42 @@ function var_type_struct(flags)
>>>>  }
>>>>  
>>>>  # Given that an option has flags FLAGS, return an initializer for the
>>>> -# "var_enum", "var_type" and "var_value" fields of its cl_options[] entry.
>>>> +# "var_enum", "var_enum_help", "var_type" and "var_value" fields of its cl_options[] entry.
>>>>  function var_set(flags)
>>>>  {
>>>> +  help_enum_index = "-1"
>>>> +	if (flag_set_p("HelpEnum.*", flags)) {
>>>> +		help_enum_index = enum_index[opt_args("HelpEnum", flags)];
>>>> +	}
>>>> +
>>>>  	if (flag_set_p("Defer", flags))
>>>> -		return "0, CLVC_DEFER, 0"
>>>> +		return "-1, -1, CLVC_DEFER, 0"
>>>>  	s = nth_arg(1, opt_args("Var", flags))
>>>>  	if (s != "")
>>>> -		return "0, CLVC_EQUAL, " s
>>>> +		return "-1, -1, CLVC_EQUAL, " s
>>>>  	s = opt_args("Mask", flags);
>>>>  	if (s != "") {
>>>>  		vn = var_name(flags);
>>>>  		if (vn)
>>>> -			return "0, CLVC_BIT_SET, OPTION_MASK_" s
>>>> +			return "-1, -1, CLVC_BIT_SET, OPTION_MASK_" s
>>>>  		else
>>>> -			return "0, CLVC_BIT_SET, MASK_" s
>>>> +			return "-1, -1, CLVC_BIT_SET, MASK_" s
>>>>  	}
>>>>  	s = nth_arg(0, opt_args("InverseMask", flags));
>>>>  	if (s != "") {
>>>>  		vn = var_name(flags);
>>>>  		if (vn)
>>>> -			return "0, CLVC_BIT_CLEAR, OPTION_MASK_" s
>>>> +			return "-1, -1, CLVC_BIT_CLEAR, OPTION_MASK_" s
>>>>  		else
>>>> -			return "0, CLVC_BIT_CLEAR, MASK_" s
>>>> +			return "-1, -1, CLVC_BIT_CLEAR, MASK_" s
>>>>  	}
>>>>  	if (flag_set_p("Enum.*", flags)) {
>>>>  		en = opt_args("Enum", flags);
>>>> -		return enum_index[en] ", CLVC_ENUM, 0"
>>>> +		return enum_index[en] ", -1, CLVC_ENUM, 0"
>>>>  	}
>>>>  	if (var_type(flags) == "const char *")
>>>> -		return "0, CLVC_STRING, 0"
>>>> -	return "0, CLVC_BOOLEAN, 0"
>>>> +		return "-1, " help_enum_index ", CLVC_STRING, 0"
>>>> +	return "-1, -1, CLVC_BOOLEAN, 0"
>>>>  }
>>>>  
>>>>  # Given that an option called NAME has flags FLAGS, return an initializer
>>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>>> index b8ae8756b4f..37e779e8732 100644
>>>> --- a/gcc/opts.c
>>>> +++ b/gcc/opts.c
>>>> @@ -1303,6 +1303,9 @@ print_filtered_help (unsigned int include_flags,
>>>>        if (option->var_type == CLVC_ENUM
>>>>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>>>>  	opts->x_help_enum_printed[option->var_enum] = 1;
>>>> +      else if (option->var_enum_help != -1
>>>> +	       && opts->x_help_enum_printed[option->var_enum_help] != 2)
>>>> +	opts->x_help_enum_printed[option->var_enum_help] = 1;
>>>>      }
>>>>  
>>>>    if (! found)
>>>> diff --git a/gcc/opts.h b/gcc/opts.h
>>>> index 3723bdbf95b..ba79a36d7ab 100644
>>>> --- a/gcc/opts.h
>>>> +++ b/gcc/opts.h
>>>> @@ -107,7 +107,10 @@ struct cl_option
>>>>    unsigned short flag_var_offset;
>>>>    /* Index in cl_enums of enum used for this option's arguments, for
>>>>       CLVC_ENUM options.  */
>>>> -  unsigned short var_enum;
>>>> +  short var_enum;
>>>> +  /* Index in cl_enums of enum used for string options which
>>>> +     have strings as possible values.  */
>>>> +  short var_enum_help;
>>>>    /* How this option's value is determined and sets a field.  */
>>>>    enum cl_var_type var_type;
>>>>    /* Value or bit-mask with which to set a field.  */
>>>>
>>>
>>
> 

[PATCH] Prototype of hook for possible list of option values.

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 358 bytes --]

Hi.

I'm sending patch candidate with suggested target common hook. It allows a target
to list all possible values for an option. Using the API, I implemented -march and
-mtune option listing on i386.

Richard you asked about the values. Yes, target should list all possible values,
mainly because --help=target output needs all of these.

Thoughts?
Martin


[-- Attachment #2: 0001-Prototype-of-hook-for-possible-list-of-option-values.patch --]
[-- Type: text/x-patch, Size: 51268 bytes --]

From b2b40f7ca1f801a318aec661d0128a5adde7cb68 Mon Sep 17 00:00:00 2001
From: marxin <mliska@suse.cz>
Date: Fri, 20 Jul 2018 09:58:16 +0200
Subject: [PATCH] Prototype of hook for possible list of option values.

---
 gcc/common/common-target.def         |   7 +
 gcc/common/common-targhooks.c        |   7 +
 gcc/common/common-targhooks.h        |   1 +
 gcc/common/config/i386/i386-common.c | 264 +++++++++++++++++
 gcc/config/i386/i386.c               | 413 +++------------------------
 gcc/config/i386/i386.h               | 144 ++++++++++
 gcc/doc/tm.texi                      |   4 +
 gcc/doc/tm.texi.in                   |   2 +
 gcc/opt-suggestions.c                |  21 +-
 gcc/opts.c                           |  33 +++
 10 files changed, 524 insertions(+), 372 deletions(-)

diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
index e0afbc6af29..8c98598b015 100644
--- a/gcc/common/common-target.def
+++ b/gcc/common/common-target.def
@@ -80,6 +80,13 @@ DEFHOOK
  bool, (bool report, struct gcc_options *opts),
  hook_bool_bool_gcc_optionsp_false)
 
+DEFHOOK
+(get_valid_option_values,
+"The hook is used for options that have a non-trivial list of\
+ possible option values.",
+ vec<const char *>, (int),
+ default_get_valid_option_values)
+
 /* Leave the boolean fields at the end.  */
 
 /* True if unwinding tables should be generated by default.  */
diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
index b1090190664..3662180f2e0 100644
--- a/gcc/common/common-targhooks.c
+++ b/gcc/common/common-targhooks.c
@@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tm.h"
 #include "common/common-target.h"
 #include "common/common-targhooks.h"
+#include "opts.h"
 
 /* Determine the exception handling mechanism for the target.  */
 
@@ -77,6 +78,12 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
   return true;
 }
 
+vec<const char *>
+default_get_valid_option_values (int option)
+{
+  return vec<const char *> ();
+}
+
 const struct default_options empty_optimization_table[] =
   {
     { OPT_LEVELS_NONE, 0, NULL, 0 }
diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
index d290d7f3e21..f8a7436d9dd 100644
--- a/gcc/common/common-targhooks.h
+++ b/gcc/common/common-targhooks.h
@@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
 					  struct gcc_options *,
 					  const struct cl_decoded_option *,
 					  location_t);
+extern vec<const char *> default_get_valid_option_values (int);
 
 extern const struct default_options empty_optimization_table[];
 
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 70b3c3f2fc3..e7253b60c36 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1459,4 +1459,268 @@ i386_except_unwind_info (struct gcc_options *opts)
 #undef TARGET_SUPPORTS_SPLIT_STACK
 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
 
+/* This table must be in sync with enum processor_type in i386.h.  */
+const struct ptt processor_target_table[PROCESSOR_max] =
+{
+  /* The "0:0:8" label alignment specified for some processors generates
+     secondary 8-byte alignment only for those label/jump/loop targets
+     which have primary alignment.  */
+
+  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"i386",           "4",       "4",       NULL,    "4" },
+  {"i486",           "16",      "16",      "0:0:8", "16"},
+  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
+  {"pentium4",       NULL,      NULL,      NULL,    NULL},
+  {"nocona",         NULL,      NULL,      NULL,    NULL},
+  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
+  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
+  {"geode",          NULL,      NULL,      NULL,    NULL},
+  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
+  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
+  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"znver1",         "16",      "16",      "0:0:8", "16"}
+};
+
+const pta processor_alias_table[] =
+{
+  {"i386", PROCESSOR_I386, CPU_NONE, 0},
+  {"i486", PROCESSOR_I486, CPU_NONE, 0},
+  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
+  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
+  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
+  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
+  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
+  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
+  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
+  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
+    PTA_SKYLAKE_AVX512},
+  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
+  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
+    PTA_ICELAKE_CLIENT},
+  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
+    PTA_ICELAKE_SERVER},
+  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
+  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
+  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
+  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
+  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
+  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+  {"geode", PROCESSOR_GEODE, CPU_GEODE,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
+  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"x86-64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"k8", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"k8-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon-fx", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
+      | PTA_XSAVEOPT | PTA_FSGSBASE},
+  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
+      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
+      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
+      | PTA_MOVBE | PTA_MWAITX},
+  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
+      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
+      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
+      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE},
+  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
+      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+
+  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
+    PTA_64BIT
+      | PTA_HLE /* flags are only used for -march switch.  */ },
+};
+
+int const pta_size = ARRAY_SIZE (processor_alias_table);
+
+vec<const char *>
+ix86_get_valid_option_values (int option)
+{
+  vec<const char *> v;
+  v.create (0);
+  opt_code opt = (opt_code) option;
+
+  switch (opt)
+    {
+    case OPT_march_:
+      for (unsigned i = 0; i < pta_size; i++)
+	v.safe_push (processor_alias_table[i].name);
+      break;
+    case OPT_mtune_:
+      for (unsigned i = 0; i < PROCESSOR_max; i++)
+	v.safe_push (processor_target_table[i].name);
+      break;
+    default:
+      break;
+    }
+
+  return v;
+}
+
+#undef  TARGET_GET_VALID_OPTION_VALUES
+#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2b7e9489ed8..b4d0942188f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -832,63 +832,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
 static tree ix86_veclibabi_svml (combined_fn, tree, tree);
 static tree ix86_veclibabi_acml (combined_fn, tree, tree);
 
-/* Processor target table, indexed by processor number */
-struct ptt
-{
-  const char *const name;			/* processor name  */
-  const struct processor_costs *cost;		/* Processor costs */
-
-  /* Default alignments.  */
-  const char *const align_loop;
-  const char *const align_jump;
-  const char *const align_label;
-  const char *const align_func;
-};
-
 /* This table must be in sync with enum processor_type in i386.h.  */ 
-static const struct ptt processor_target_table[PROCESSOR_max] =
-{
-/* The "0:0:8" label alignment specified for some processors generates
-   secondary 8-byte alignment only for those label/jump/loop targets
-   which have primary alignment.  */
-
-  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
-  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
-  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
-  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
-  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
-  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
-  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
-  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
-  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
-  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
-  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
-  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
+static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
+{
+  &generic_cost,
+  &i386_cost,
+  &i486_cost,
+  &pentium_cost,
+  &lakemont_cost,
+  &pentiumpro_cost,
+  &pentium4_cost,
+  &nocona_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &atom_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &intel_cost,
+  &geode_cost,
+  &k6_cost,
+  &athlon_cost,
+  &k8_cost,
+  &amdfam10_cost,
+  &bdver1_cost,
+  &bdver2_cost,
+  &bdver3_cost,
+  &bdver4_cost,
+  &btver1_cost,
+  &btver2_cost,
+  &znver1_cost,
 };
 \f
 static unsigned int
@@ -3392,6 +3375,8 @@ ix86_override_options_after_change (void)
   ix86_default_align (&global_options);
 }
 
+
+
 /* Override various settings based on options.  If MAIN_ARGS_P, the
    options are from the command line, otherwise they are from
    attributes.  Return true if there's an error related to march
@@ -3406,317 +3391,6 @@ ix86_option_override_internal (bool main_args_p,
   unsigned HOST_WIDE_INT ix86_arch_mask;
   const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
 
-  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
-  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
-  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
-  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
-  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
-  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
-  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
-  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
-  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
-  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
-  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
-  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
-  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
-  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
-  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
-  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
-  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
-  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
-  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
-  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
-  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
-  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
-  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
-  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
-  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
-  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
-  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
-  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
-  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
-  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
-  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
-  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
-  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
-  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
-  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
-  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
-  /* Hole after PTA_MPX was removed.  */
-  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
-  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
-  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
-  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
-  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
-  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
-  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
-  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
-  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
-  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
-  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
-  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
-  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
-  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
-  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
-  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
-  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
-  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
-  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
-  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
-  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
-
-  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
-    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
-  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
-    | PTA_POPCNT;
-  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
-  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
-    | PTA_XSAVEOPT;
-  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
-    | PTA_RDRND | PTA_F16C;
-  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
-    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
-    | PTA_RDSEED;
-  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
-    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
-  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_CLWB;
-  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
-  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
-    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
-    | PTA_RDPID | PTA_CLWB;
-  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
-    | PTA_WBNOINVD;
-  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
-    | PTA_AVX512F | PTA_AVX512CD;
-  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
-  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
-  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
-    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
-    | PTA_FSGSBASE;
-  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
-    | PTA_SGX;
-  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
-    | PTA_GFNI;
-  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
-    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
-
-  static struct pta
-    {
-      const char *const name;		/* processor name or nickname.  */
-      const enum processor_type processor;
-      const enum attr_cpu schedule;
-      const wide_int_bitmask flags;
-    }
-  const processor_alias_table[] =
-    {
-      {"i386", PROCESSOR_I386, CPU_NONE, 0},
-      {"i486", PROCESSOR_I486, CPU_NONE, 0},
-      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
-      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
-      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
-      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
-      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
-      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
-      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
-      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
-      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
-      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
-        PTA_SKYLAKE_AVX512},
-      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
-      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
-	PTA_ICELAKE_CLIENT},
-      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
-	PTA_ICELAKE_SERVER},
-      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
-      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
-      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
-      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
-      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
-      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
-      {"geode", PROCESSOR_GEODE, CPU_GEODE,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
-      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"x86-64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"eden-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nano", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-1000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-2000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-3000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"eden-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"k8", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"k8-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon-fx", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
-	| PTA_XSAVEOPT | PTA_FSGSBASE},
-      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
-	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
-	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
-	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
-	| PTA_MOVBE | PTA_MWAITX},
-      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
-	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
-	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
-	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
-	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
-      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE},
-      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
-	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
-
-      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
-	PTA_64BIT
-	| PTA_HLE /* flags are only used for -march switch.  */ },
-    };
-
   /* -mrecip options.  */
   static struct
     {
@@ -3733,7 +3407,6 @@ ix86_option_override_internal (bool main_args_p,
       { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
     };
 
-  int const pta_size = ARRAY_SIZE (processor_alias_table);
 
   /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
      TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
@@ -4389,7 +4062,7 @@ ix86_option_override_internal (bool main_args_p,
 	}
     }
 
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
@@ -5186,7 +4859,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
   opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
   opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
   opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index fbba598ffd5..cc7fc1fd443 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2283,6 +2283,150 @@ enum processor_type
   PROCESSOR_max
 };
 
+/* Processor target table, indexed by processor number */
+struct ptt
+{
+  const char *const name;			/* processor name  */
+
+  /* Default alignments.  */
+  const char *const align_loop;
+  const char *const align_jump;
+  const char *const align_label;
+  const char *const align_func;
+};
+
+extern const struct ptt processor_target_table[PROCESSOR_max];
+
+#include "wide-int-bitmask.h"
+
+const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
+const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
+const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
+const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
+const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
+const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
+const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
+const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
+const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
+const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+/* Hole after PTA_MPX was removed.  */
+const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
+const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
+const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
+const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
+const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
+
+const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+  | PTA_POPCNT;
+const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+  | PTA_XSAVEOPT;
+const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
+  | PTA_RDRND | PTA_F16C;
+const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
+  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+  | PTA_RDSEED;
+const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
+const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_CLWB;
+const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
+const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
+  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
+  | PTA_RDPID | PTA_CLWB;
+const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
+  | PTA_WBNOINVD;
+const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+  | PTA_AVX512F | PTA_AVX512CD;
+const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
+  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
+  | PTA_FSGSBASE;
+const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
+  | PTA_SGX;
+const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
+  | PTA_GFNI;
+const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
+  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
+
+#include "insn-attr-common.h"
+
+struct pta
+{
+  const char *const name;		/* processor name or nickname.  */
+  const enum processor_type processor;
+  const enum attr_cpu schedule;
+  const wide_int_bitmask flags;
+};
+
+extern const pta processor_alias_table[];
+extern int const pta_size;
+
 extern enum processor_type ix86_tune;
 extern enum processor_type ix86_arch;
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 0ddcd1aa2ac..c743a7d0dc0 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
 Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
 @end deftypefn
 
+@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int)
+The hook is used for options that have a non-trivial list of possible option values.
+@end deftypefn
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index e275aca0eec..3fbcbea820b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3669,6 +3669,8 @@ generic code.
 
 @hook TARGET_SUPPORTS_SPLIT_STACK
 
+@hook TARGET_GET_VALID_OPTION_VALUES
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
index 894eea5f37c..6f3f071a171 100644
--- a/gcc/opt-suggestions.c
+++ b/gcc/opt-suggestions.c
@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "params.h"
 #include "spellcheck.h"
 #include "opt-suggestions.h"
+#include "common/common-target.h"
 #include "selftest.h"
 
 option_proposer::~option_proposer ()
@@ -135,8 +136,24 @@ option_proposer::build_option_suggestions (void)
 		}
 	    }
 	  else
-	    add_misspelling_candidates (m_option_suggestions, option,
-					opt_text);
+	    {
+	      vec<const char *> option_values
+		= targetm_common.get_valid_option_values (i);
+	      if (!option_values.is_empty ())
+		{
+		  for (unsigned j = 0; j < option_values.length (); j++)
+		    {
+		      char *with_arg = concat (opt_text, option_values[j],
+					       NULL);
+		      add_misspelling_candidates (m_option_suggestions, option,
+						  with_arg);
+		      free (with_arg);
+		    }
+		}
+	      else
+		add_misspelling_candidates (m_option_suggestions, option,
+					    opt_text);
+	    }
 	  break;
 
 	case OPT_fsanitize_:
diff --git a/gcc/opts.c b/gcc/opts.c
index b8ae8756b4f..97cfd8f455c 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1090,6 +1090,21 @@ wrap_help (const char *help,
   while (remaining);
 }
 
+/* Data structure used to print list of valid option values.  */
+
+struct option_help_tuple
+{
+  option_help_tuple (int code, vec<const char *> values):
+    m_code (code), m_values (values)
+  {}
+
+  /* Code of an option.  */
+  int m_code;
+
+  /* List of possible values.  */
+  vec<const char *> m_values;
+};
+
 /* Print help for a specific front-end, etc.  */
 static void
 print_filtered_help (unsigned int include_flags,
@@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
   if (!opts->x_help_enum_printed)
     opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
 
+  auto_vec<option_help_tuple> help_tuples;
+
   for (i = 0; i < cl_options_count; i++)
     {
       const struct cl_option *option = cl_options + i;
@@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
       if (option->var_type == CLVC_ENUM
 	  && opts->x_help_enum_printed[option->var_enum] != 2)
 	opts->x_help_enum_printed[option->var_enum] = 1;
+      else
+	{
+	  vec<const char *> option_values
+	    = targetm_common.get_valid_option_values (i);
+	  if (!option_values.is_empty ())
+	    help_tuples.safe_push (option_help_tuple (i, option_values));
+	}
     }
 
   if (! found)
@@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
       printf ("\n\n");
       opts->x_help_enum_printed[i] = 2;
     }
+
+  for (unsigned i = 0; i < help_tuples.length (); i++)
+    {
+      const struct cl_option *option = cl_options + help_tuples[i].m_code;
+      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
+      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
+	printf (" %s", help_tuples[i].m_values[j]);
+      printf ("\n\n");
+    }
 }
 
 /* Display help for a specified type of option.
-- 
2.18.0

Re: [PATCH] Prototype of hook for possible list of option values.

[Richard Earnshaw (lists)]

On 20/07/18 09:04, Martin Liška wrote:
> Hi.
> 
> I'm sending patch candidate with suggested target common hook. It allows a target
> to list all possible values for an option. Using the API, I implemented -march and
> -mtune option listing on i386.
> 
> Richard you asked about the values. Yes, target should list all possible values,
> mainly because --help=target output needs all of these.
> 
> Thoughts?
> Martin
> 

I don't think anyone can reasonably write an implementation of this hook
based on this specification:

+@deftypefn {Common Target Hook} {vec<const char *>}
TARGET_GET_VALID_OPTION_VALUES (int)
+The hook is used for options that have a non-trivial list of possible
option values.
+@end deftypefn
+

What's the int parameter for?  What's the lifetime of the result (who
cleans it up)?  If I need to allocation memory strings in the vector,
where do I do that?  Can I assume GC memory in the driver, for example?

Frankly though, I don't really want to enumerate every possible
permutation of the options for the architecture like this, though.  It's
just too brute force and the answer is likely to be hundreds (haven't
sat down to count it).  What's more, the extensions might have meaning
in the order in which they appear.  So, for example,

	-march=armv8-a+crypto+nosimd

would be very different from

	-march=armv8-a+nosimd+crypto

since the extensions are applied from left to right (the first collapses
to armv8-a+nosimd, the latter to armv8-a+crypto, but there are more
complex cases as well which I don't want to dig into here).

It would be a practical impossibility to list all of these.

R.

> 
> 0001-Prototype-of-hook-for-possible-list-of-option-values.patch
> 
> 
> From b2b40f7ca1f801a318aec661d0128a5adde7cb68 Mon Sep 17 00:00:00 2001
> From: marxin <mliska@suse.cz>
> Date: Fri, 20 Jul 2018 09:58:16 +0200
> Subject: [PATCH] Prototype of hook for possible list of option values.
> 
> ---
>  gcc/common/common-target.def         |   7 +
>  gcc/common/common-targhooks.c        |   7 +
>  gcc/common/common-targhooks.h        |   1 +
>  gcc/common/config/i386/i386-common.c | 264 +++++++++++++++++
>  gcc/config/i386/i386.c               | 413 +++------------------------
>  gcc/config/i386/i386.h               | 144 ++++++++++
>  gcc/doc/tm.texi                      |   4 +
>  gcc/doc/tm.texi.in                   |   2 +
>  gcc/opt-suggestions.c                |  21 +-
>  gcc/opts.c                           |  33 +++
>  10 files changed, 524 insertions(+), 372 deletions(-)
> 
> diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
> index e0afbc6af29..8c98598b015 100644
> --- a/gcc/common/common-target.def
> +++ b/gcc/common/common-target.def
> @@ -80,6 +80,13 @@ DEFHOOK
>   bool, (bool report, struct gcc_options *opts),
>   hook_bool_bool_gcc_optionsp_false)
>  
> +DEFHOOK
> +(get_valid_option_values,
> +"The hook is used for options that have a non-trivial list of\
> + possible option values.",
> + vec<const char *>, (int),
> + default_get_valid_option_values)
> +
>  /* Leave the boolean fields at the end.  */
>  
>  /* True if unwinding tables should be generated by default.  */
> diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
> index b1090190664..3662180f2e0 100644
> --- a/gcc/common/common-targhooks.c
> +++ b/gcc/common/common-targhooks.c
> @@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
>  #include "tm.h"
>  #include "common/common-target.h"
>  #include "common/common-targhooks.h"
> +#include "opts.h"
>  
>  /* Determine the exception handling mechanism for the target.  */
>  
> @@ -77,6 +78,12 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
>    return true;
>  }
>  
> +vec<const char *>
> +default_get_valid_option_values (int option)
> +{
> +  return vec<const char *> ();
> +}
> +
>  const struct default_options empty_optimization_table[] =
>    {
>      { OPT_LEVELS_NONE, 0, NULL, 0 }
> diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
> index d290d7f3e21..f8a7436d9dd 100644
> --- a/gcc/common/common-targhooks.h
> +++ b/gcc/common/common-targhooks.h
> @@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
>  					  struct gcc_options *,
>  					  const struct cl_decoded_option *,
>  					  location_t);
> +extern vec<const char *> default_get_valid_option_values (int);
>  
>  extern const struct default_options empty_optimization_table[];
>  
> diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
> index 70b3c3f2fc3..e7253b60c36 100644
> --- a/gcc/common/config/i386/i386-common.c
> +++ b/gcc/common/config/i386/i386-common.c
> @@ -1459,4 +1459,268 @@ i386_except_unwind_info (struct gcc_options *opts)
>  #undef TARGET_SUPPORTS_SPLIT_STACK
>  #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
>  
> +/* This table must be in sync with enum processor_type in i386.h.  */
> +const struct ptt processor_target_table[PROCESSOR_max] =
> +{
> +  /* The "0:0:8" label alignment specified for some processors generates
> +     secondary 8-byte alignment only for those label/jump/loop targets
> +     which have primary alignment.  */
> +
> +  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"i386",           "4",       "4",       NULL,    "4" },
> +  {"i486",           "16",      "16",      "0:0:8", "16"},
> +  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
> +  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
> +  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
> +  {"pentium4",       NULL,      NULL,      NULL,    NULL},
> +  {"nocona",         NULL,      NULL,      NULL,    NULL},
> +  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
> +  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
> +  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
> +  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
> +  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
> +  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
> +  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
> +  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
> +  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
> +  {"geode",          NULL,      NULL,      NULL,    NULL},
> +  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
> +  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
> +  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
> +  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
> +  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
> +  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
> +  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
> +  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
> +  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
> +  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
> +  {"znver1",         "16",      "16",      "0:0:8", "16"}
> +};
> +
> +const pta processor_alias_table[] =
> +{
> +  {"i386", PROCESSOR_I386, CPU_NONE, 0},
> +  {"i486", PROCESSOR_I486, CPU_NONE, 0},
> +  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
> +  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
> +  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
> +  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
> +  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
> +  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
> +  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
> +  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
> +  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> +    PTA_MMX | PTA_SSE | PTA_FXSR},
> +  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> +    PTA_MMX | PTA_SSE | PTA_FXSR},
> +  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> +  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> +  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
> +  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
> +  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
> +  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> +    PTA_MMX | PTA_SSE | PTA_FXSR},
> +  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> +    PTA_MMX | PTA_SSE | PTA_FXSR},
> +  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
> +  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
> +    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
> +  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
> +  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> +  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
> +  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
> +  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
> +  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
> +  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
> +  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> +    PTA_SANDYBRIDGE},
> +  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> +    PTA_SANDYBRIDGE},
> +  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> +    PTA_IVYBRIDGE},
> +  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> +    PTA_IVYBRIDGE},
> +  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
> +  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
> +  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
> +  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
> +  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
> +    PTA_SKYLAKE_AVX512},
> +  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
> +  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
> +    PTA_ICELAKE_CLIENT},
> +  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
> +    PTA_ICELAKE_SERVER},
> +  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
> +  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
> +  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
> +  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
> +  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
> +  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
> +  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
> +  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
> +  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
> +  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
> +  {"geode", PROCESSOR_GEODE, CPU_GEODE,
> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
> +  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
> +  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
> +  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
> +  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
> +  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
> +  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
> +  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
> +  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
> +  {"x86-64", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> +  {"eden-x2", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> +  {"nano", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_FXSR},
> +  {"nano-1000", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_FXSR},
> +  {"nano-2000", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_FXSR},
> +  {"nano-3000", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> +  {"nano-x2", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> +  {"eden-x4", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> +  {"nano-x4", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> +  {"k8", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> +  {"k8-sse3", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
> +  {"opteron", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> +  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
> +  {"athlon64", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> +  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
> +  {"athlon-fx", PROCESSOR_K8, CPU_K8,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> +  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
> +  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
> +  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
> +      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
> +  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
> +  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
> +      | PTA_XSAVEOPT | PTA_FSGSBASE},
> +  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
> +      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
> +      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
> +      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
> +      | PTA_MOVBE | PTA_MWAITX},
> +  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
> +      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
> +      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
> +      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
> +      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
> +  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
> +      | PTA_FXSR | PTA_XSAVE},
> +  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
> +      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
> +
> +  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
> +    PTA_64BIT
> +      | PTA_HLE /* flags are only used for -march switch.  */ },
> +};
> +
> +int const pta_size = ARRAY_SIZE (processor_alias_table);
> +
> +vec<const char *>
> +ix86_get_valid_option_values (int option)
> +{
> +  vec<const char *> v;
> +  v.create (0);
> +  opt_code opt = (opt_code) option;
> +
> +  switch (opt)
> +    {
> +    case OPT_march_:
> +      for (unsigned i = 0; i < pta_size; i++)
> +	v.safe_push (processor_alias_table[i].name);
> +      break;
> +    case OPT_mtune_:
> +      for (unsigned i = 0; i < PROCESSOR_max; i++)
> +	v.safe_push (processor_target_table[i].name);
> +      break;
> +    default:
> +      break;
> +    }
> +
> +  return v;
> +}
> +
> +#undef  TARGET_GET_VALID_OPTION_VALUES
> +#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
> +
>  struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 2b7e9489ed8..b4d0942188f 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -832,63 +832,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
>  static tree ix86_veclibabi_svml (combined_fn, tree, tree);
>  static tree ix86_veclibabi_acml (combined_fn, tree, tree);
>  
> -/* Processor target table, indexed by processor number */
> -struct ptt
> -{
> -  const char *const name;			/* processor name  */
> -  const struct processor_costs *cost;		/* Processor costs */
> -
> -  /* Default alignments.  */
> -  const char *const align_loop;
> -  const char *const align_jump;
> -  const char *const align_label;
> -  const char *const align_func;
> -};
> -
>  /* This table must be in sync with enum processor_type in i386.h.  */ 
> -static const struct ptt processor_target_table[PROCESSOR_max] =
> -{
> -/* The "0:0:8" label alignment specified for some processors generates
> -   secondary 8-byte alignment only for those label/jump/loop targets
> -   which have primary alignment.  */
> -
> -  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
> -  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
> -  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
> -  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
> -  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
> -  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
> -  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
> -  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
> -  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
> -  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
> -  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
> -  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
> -  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
> -  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
> -  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
> -  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
> -  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
> -  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
> -  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
> -  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
> -  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
> -  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
> -  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
> -  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
> -  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
> -  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
> -  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
> -  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
> +static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
> +{
> +  &generic_cost,
> +  &i386_cost,
> +  &i486_cost,
> +  &pentium_cost,
> +  &lakemont_cost,
> +  &pentiumpro_cost,
> +  &pentium4_cost,
> +  &nocona_cost,
> +  &core_cost,
> +  &core_cost,
> +  &core_cost,
> +  &core_cost,
> +  &atom_cost,
> +  &slm_cost,
> +  &slm_cost,
> +  &slm_cost,
> +  &slm_cost,
> +  &slm_cost,
> +  &slm_cost,
> +  &skylake_cost,
> +  &skylake_cost,
> +  &skylake_cost,
> +  &skylake_cost,
> +  &skylake_cost,
> +  &intel_cost,
> +  &geode_cost,
> +  &k6_cost,
> +  &athlon_cost,
> +  &k8_cost,
> +  &amdfam10_cost,
> +  &bdver1_cost,
> +  &bdver2_cost,
> +  &bdver3_cost,
> +  &bdver4_cost,
> +  &btver1_cost,
> +  &btver2_cost,
> +  &znver1_cost,
>  };
>  \f
>  static unsigned int
> @@ -3392,6 +3375,8 @@ ix86_override_options_after_change (void)
>    ix86_default_align (&global_options);
>  }
>  
> +
> +
>  /* Override various settings based on options.  If MAIN_ARGS_P, the
>     options are from the command line, otherwise they are from
>     attributes.  Return true if there's an error related to march
> @@ -3406,317 +3391,6 @@ ix86_option_override_internal (bool main_args_p,
>    unsigned HOST_WIDE_INT ix86_arch_mask;
>    const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
>  
> -  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
> -  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
> -  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
> -  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
> -  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
> -  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
> -  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
> -  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
> -  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
> -  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
> -  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
> -  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
> -  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
> -  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
> -  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
> -  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
> -  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
> -  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
> -  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
> -  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
> -  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
> -  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
> -  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
> -  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
> -  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
> -  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
> -  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
> -  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
> -  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
> -  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
> -  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
> -  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
> -  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
> -  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
> -  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
> -  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
> -  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
> -  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
> -  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
> -  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
> -  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
> -  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
> -  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
> -  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
> -  /* Hole after PTA_MPX was removed.  */
> -  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
> -  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
> -  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
> -  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
> -  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
> -  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
> -  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
> -  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
> -  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
> -  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
> -  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
> -  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
> -  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
> -  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
> -  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
> -  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
> -  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
> -  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
> -  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
> -  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
> -  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
> -  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
> -  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
> -  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
> -  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
> -  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
> -  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
> -  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
> -  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
> -
> -  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
> -    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
> -  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
> -    | PTA_POPCNT;
> -  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
> -  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
> -    | PTA_XSAVEOPT;
> -  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
> -    | PTA_RDRND | PTA_F16C;
> -  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
> -    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
> -  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
> -    | PTA_RDSEED;
> -  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
> -    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
> -  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
> -    | PTA_CLWB;
> -  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
> -    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
> -  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
> -    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
> -    | PTA_RDPID | PTA_CLWB;
> -  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
> -    | PTA_WBNOINVD;
> -  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
> -    | PTA_AVX512F | PTA_AVX512CD;
> -  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
> -  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
> -  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
> -    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
> -    | PTA_FSGSBASE;
> -  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
> -    | PTA_SGX;
> -  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
> -    | PTA_GFNI;
> -  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
> -    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
> -
> -  static struct pta
> -    {
> -      const char *const name;		/* processor name or nickname.  */
> -      const enum processor_type processor;
> -      const enum attr_cpu schedule;
> -      const wide_int_bitmask flags;
> -    }
> -  const processor_alias_table[] =
> -    {
> -      {"i386", PROCESSOR_I386, CPU_NONE, 0},
> -      {"i486", PROCESSOR_I486, CPU_NONE, 0},
> -      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
> -      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
> -      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
> -      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
> -      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
> -      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
> -      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
> -      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
> -      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> -	PTA_MMX | PTA_SSE | PTA_FXSR},
> -      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> -        PTA_MMX | PTA_SSE | PTA_FXSR},
> -      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> -      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> -      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
> -      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
> -      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
> -      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> -	PTA_MMX | PTA_SSE | PTA_FXSR},
> -      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> -	PTA_MMX | PTA_SSE | PTA_FXSR},
> -      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
> -      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
> -	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
> -      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
> -      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> -      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
> -      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
> -      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
> -      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
> -      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
> -      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> -	PTA_SANDYBRIDGE},
> -      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> -	PTA_SANDYBRIDGE},
> -      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> -	PTA_IVYBRIDGE},
> -      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
> -	PTA_IVYBRIDGE},
> -      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
> -      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
> -      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
> -      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
> -      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
> -        PTA_SKYLAKE_AVX512},
> -      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
> -      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
> -	PTA_ICELAKE_CLIENT},
> -      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
> -	PTA_ICELAKE_SERVER},
> -      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
> -      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
> -      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
> -      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
> -      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
> -      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
> -      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
> -      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
> -      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
> -      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
> -      {"geode", PROCESSOR_GEODE, CPU_GEODE,
> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
> -      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
> -      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
> -      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
> -      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
> -      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
> -      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
> -      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
> -      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
> -      {"x86-64", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> -      {"eden-x2", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
> -      {"nano", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -        | PTA_SSSE3 | PTA_FXSR},
> -      {"nano-1000", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -        | PTA_SSSE3 | PTA_FXSR},
> -      {"nano-2000", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -        | PTA_SSSE3 | PTA_FXSR},
> -      {"nano-3000", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> -      {"nano-x2", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> -      {"eden-x4", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> -      {"nano-x4", PROCESSOR_K8, CPU_K8,
> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
> -      {"k8", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> -      {"k8-sse3", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
> -      {"opteron", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> -      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
> -      {"athlon64", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> -      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
> -      {"athlon-fx", PROCESSOR_K8, CPU_K8,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
> -      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
> -      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
> -      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
> -	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
> -      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
> -      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
> -	| PTA_XSAVEOPT | PTA_FSGSBASE},
> -      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
> -	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
> -	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
> -	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
> -	| PTA_MOVBE | PTA_MWAITX},
> -      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
> -	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
> -	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
> -	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
> -	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
> -      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
> -	| PTA_FXSR | PTA_XSAVE},
> -      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
> -	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
> -
> -      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
> -	PTA_64BIT
> -	| PTA_HLE /* flags are only used for -march switch.  */ },
> -    };
> -
>    /* -mrecip options.  */
>    static struct
>      {
> @@ -3733,7 +3407,6 @@ ix86_option_override_internal (bool main_args_p,
>        { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
>      };
>  
> -  int const pta_size = ARRAY_SIZE (processor_alias_table);
>  
>    /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
>       TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
> @@ -4389,7 +4062,7 @@ ix86_option_override_internal (bool main_args_p,
>  	}
>      }
>  
> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>       so for cold code we use size_cost even in !optimize_size compilation.  */
>    if (opts->x_optimize_size)
> @@ -5186,7 +4859,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
>    opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
>    opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
>    opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>       so for cold code we use size_cost even in !optimize_size compilation.  */
>    if (opts->x_optimize_size)
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index fbba598ffd5..cc7fc1fd443 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2283,6 +2283,150 @@ enum processor_type
>    PROCESSOR_max
>  };
>  
> +/* Processor target table, indexed by processor number */
> +struct ptt
> +{
> +  const char *const name;			/* processor name  */
> +
> +  /* Default alignments.  */
> +  const char *const align_loop;
> +  const char *const align_jump;
> +  const char *const align_label;
> +  const char *const align_func;
> +};
> +
> +extern const struct ptt processor_target_table[PROCESSOR_max];
> +
> +#include "wide-int-bitmask.h"
> +
> +const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
> +const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
> +const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
> +const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
> +const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
> +const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
> +const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
> +const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
> +const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
> +const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
> +const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
> +const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
> +const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
> +const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
> +const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
> +const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
> +const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
> +const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
> +const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
> +const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
> +const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
> +const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
> +const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
> +const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
> +const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
> +const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
> +const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
> +const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
> +const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
> +const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
> +const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
> +const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
> +const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
> +const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
> +const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
> +const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
> +const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
> +const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
> +const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
> +const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
> +const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
> +const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
> +const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
> +const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
> +/* Hole after PTA_MPX was removed.  */
> +const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
> +const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
> +const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
> +const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
> +const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
> +const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
> +const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
> +const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
> +const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
> +const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
> +const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
> +const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
> +const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
> +const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
> +const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
> +const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
> +const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
> +const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
> +const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
> +const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
> +const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
> +const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
> +const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
> +const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
> +const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
> +const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
> +const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
> +const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
> +const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
> +
> +const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
> +  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
> +const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
> +  | PTA_POPCNT;
> +const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
> +const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
> +  | PTA_XSAVEOPT;
> +const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
> +  | PTA_RDRND | PTA_F16C;
> +const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
> +  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
> +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
> +  | PTA_RDSEED;
> +const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
> +  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
> +const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
> +  | PTA_CLWB;
> +const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
> +  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
> +const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
> +  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
> +  | PTA_RDPID | PTA_CLWB;
> +const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
> +  | PTA_WBNOINVD;
> +const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
> +  | PTA_AVX512F | PTA_AVX512CD;
> +const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
> +const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
> +const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
> +  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
> +  | PTA_FSGSBASE;
> +const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
> +  | PTA_SGX;
> +const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
> +  | PTA_GFNI;
> +const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
> +  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
> +
> +#include "insn-attr-common.h"
> +
> +struct pta
> +{
> +  const char *const name;		/* processor name or nickname.  */
> +  const enum processor_type processor;
> +  const enum attr_cpu schedule;
> +  const wide_int_bitmask flags;
> +};
> +
> +extern const pta processor_alias_table[];
> +extern int const pta_size;
> +
>  extern enum processor_type ix86_tune;
>  extern enum processor_type ix86_arch;
>  
> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
> index 0ddcd1aa2ac..c743a7d0dc0 100644
> --- a/gcc/doc/tm.texi
> +++ b/gcc/doc/tm.texi
> @@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
>  Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
>  @end deftypefn
>  
> +@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int)
> +The hook is used for options that have a non-trivial list of possible option values.
> +@end deftypefn
> +
>  @node Miscellaneous Register Hooks
>  @subsection Miscellaneous register hooks
>  @cindex miscellaneous register hooks
> diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
> index e275aca0eec..3fbcbea820b 100644
> --- a/gcc/doc/tm.texi.in
> +++ b/gcc/doc/tm.texi.in
> @@ -3669,6 +3669,8 @@ generic code.
>  
>  @hook TARGET_SUPPORTS_SPLIT_STACK
>  
> +@hook TARGET_GET_VALID_OPTION_VALUES
> +
>  @node Miscellaneous Register Hooks
>  @subsection Miscellaneous register hooks
>  @cindex miscellaneous register hooks
> diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
> index 894eea5f37c..6f3f071a171 100644
> --- a/gcc/opt-suggestions.c
> +++ b/gcc/opt-suggestions.c
> @@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
>  #include "params.h"
>  #include "spellcheck.h"
>  #include "opt-suggestions.h"
> +#include "common/common-target.h"
>  #include "selftest.h"
>  
>  option_proposer::~option_proposer ()
> @@ -135,8 +136,24 @@ option_proposer::build_option_suggestions (void)
>  		}
>  	    }
>  	  else
> -	    add_misspelling_candidates (m_option_suggestions, option,
> -					opt_text);
> +	    {
> +	      vec<const char *> option_values
> +		= targetm_common.get_valid_option_values (i);
> +	      if (!option_values.is_empty ())
> +		{
> +		  for (unsigned j = 0; j < option_values.length (); j++)
> +		    {
> +		      char *with_arg = concat (opt_text, option_values[j],
> +					       NULL);
> +		      add_misspelling_candidates (m_option_suggestions, option,
> +						  with_arg);
> +		      free (with_arg);
> +		    }
> +		}
> +	      else
> +		add_misspelling_candidates (m_option_suggestions, option,
> +					    opt_text);
> +	    }
>  	  break;
>  
>  	case OPT_fsanitize_:
> diff --git a/gcc/opts.c b/gcc/opts.c
> index b8ae8756b4f..97cfd8f455c 100644
> --- a/gcc/opts.c
> +++ b/gcc/opts.c
> @@ -1090,6 +1090,21 @@ wrap_help (const char *help,
>    while (remaining);
>  }
>  
> +/* Data structure used to print list of valid option values.  */
> +
> +struct option_help_tuple
> +{
> +  option_help_tuple (int code, vec<const char *> values):
> +    m_code (code), m_values (values)
> +  {}
> +
> +  /* Code of an option.  */
> +  int m_code;
> +
> +  /* List of possible values.  */
> +  vec<const char *> m_values;
> +};
> +
>  /* Print help for a specific front-end, etc.  */
>  static void
>  print_filtered_help (unsigned int include_flags,
> @@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
>    if (!opts->x_help_enum_printed)
>      opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
>  
> +  auto_vec<option_help_tuple> help_tuples;
> +
>    for (i = 0; i < cl_options_count; i++)
>      {
>        const struct cl_option *option = cl_options + i;
> @@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
>        if (option->var_type == CLVC_ENUM
>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>  	opts->x_help_enum_printed[option->var_enum] = 1;
> +      else
> +	{
> +	  vec<const char *> option_values
> +	    = targetm_common.get_valid_option_values (i);
> +	  if (!option_values.is_empty ())
> +	    help_tuples.safe_push (option_help_tuple (i, option_values));
> +	}
>      }
>  
>    if (! found)
> @@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
>        printf ("\n\n");
>        opts->x_help_enum_printed[i] = 2;
>      }
> +
> +  for (unsigned i = 0; i < help_tuples.length (); i++)
> +    {
> +      const struct cl_option *option = cl_options + help_tuples[i].m_code;
> +      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
> +      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
> +	printf (" %s", help_tuples[i].m_values[j]);
> +      printf ("\n\n");
> +    }
>  }
>  
>  /* Display help for a specified type of option.
> 

Re: [PATCH] Prototype of hook for possible list of option values.

[Martin Liška]

On 07/20/2018 11:48 AM, Richard Earnshaw (lists) wrote:
> On 20/07/18 09:04, Martin Liška wrote:
>> Hi.
>>
>> I'm sending patch candidate with suggested target common hook. It allows a target
>> to list all possible values for an option. Using the API, I implemented -march and
>> -mtune option listing on i386.
>>
>> Richard you asked about the values. Yes, target should list all possible values,
>> mainly because --help=target output needs all of these.
>>
>> Thoughts?
>> Martin
>>
> 
> I don't think anyone can reasonably write an implementation of this hook
> based on this specification:
> 
> +@deftypefn {Common Target Hook} {vec<const char *>}
> TARGET_GET_VALID_OPTION_VALUES (int)
> +The hook is used for options that have a non-trivial list of possible
> option values.
> +@end deftypefn
> +
> 
> What's the int parameter for?  What's the lifetime of the result (who
> cleans it up)?  If I need to allocation memory strings in the vector,
> where do I do that?  Can I assume GC memory in the driver, for example?

Sure, can be improved, please take it as prototype.

> 
> Frankly though, I don't really want to enumerate every possible
> permutation of the options for the architecture like this, though.  It's
> just too brute force and the answer is likely to be hundreds (haven't

That's why I recommended you to list in --help=target content of
arm_arch enum. You replied that it's not complete list of all possible values.
Note that we are talking about content of --help option, it's not a documentation,
it should just help users. Similar to bash completion, it should not be 100% perfect.

> sat down to count it).  What's more, the extensions might have meaning
> in the order in which they appear.  So, for example,
> 
> 	-march=armv8-a+crypto+nosimd
> 
> would be very different from
> 
> 	-march=armv8-a+nosimd+crypto
> 
> since the extensions are applied from left to right (the first collapses
> to armv8-a+nosimd, the latter to armv8-a+crypto, but there are more
> complex cases as well which I don't want to dig into here).
> 
> It would be a practical impossibility to list all of these.

Yes, that's why I recommended to list only base march values. Modifiers can be mentioned
aside if desired.

Martin

> 
> R.
> 
>>
>> 0001-Prototype-of-hook-for-possible-list-of-option-values.patch
>>
>>
>> From b2b40f7ca1f801a318aec661d0128a5adde7cb68 Mon Sep 17 00:00:00 2001
>> From: marxin <mliska@suse.cz>
>> Date: Fri, 20 Jul 2018 09:58:16 +0200
>> Subject: [PATCH] Prototype of hook for possible list of option values.
>>
>> ---
>>  gcc/common/common-target.def         |   7 +
>>  gcc/common/common-targhooks.c        |   7 +
>>  gcc/common/common-targhooks.h        |   1 +
>>  gcc/common/config/i386/i386-common.c | 264 +++++++++++++++++
>>  gcc/config/i386/i386.c               | 413 +++------------------------
>>  gcc/config/i386/i386.h               | 144 ++++++++++
>>  gcc/doc/tm.texi                      |   4 +
>>  gcc/doc/tm.texi.in                   |   2 +
>>  gcc/opt-suggestions.c                |  21 +-
>>  gcc/opts.c                           |  33 +++
>>  10 files changed, 524 insertions(+), 372 deletions(-)
>>
>> diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
>> index e0afbc6af29..8c98598b015 100644
>> --- a/gcc/common/common-target.def
>> +++ b/gcc/common/common-target.def
>> @@ -80,6 +80,13 @@ DEFHOOK
>>   bool, (bool report, struct gcc_options *opts),
>>   hook_bool_bool_gcc_optionsp_false)
>>  
>> +DEFHOOK
>> +(get_valid_option_values,
>> +"The hook is used for options that have a non-trivial list of\
>> + possible option values.",
>> + vec<const char *>, (int),
>> + default_get_valid_option_values)
>> +
>>  /* Leave the boolean fields at the end.  */
>>  
>>  /* True if unwinding tables should be generated by default.  */
>> diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
>> index b1090190664..3662180f2e0 100644
>> --- a/gcc/common/common-targhooks.c
>> +++ b/gcc/common/common-targhooks.c
>> @@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
>>  #include "tm.h"
>>  #include "common/common-target.h"
>>  #include "common/common-targhooks.h"
>> +#include "opts.h"
>>  
>>  /* Determine the exception handling mechanism for the target.  */
>>  
>> @@ -77,6 +78,12 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
>>    return true;
>>  }
>>  
>> +vec<const char *>
>> +default_get_valid_option_values (int option)
>> +{
>> +  return vec<const char *> ();
>> +}
>> +
>>  const struct default_options empty_optimization_table[] =
>>    {
>>      { OPT_LEVELS_NONE, 0, NULL, 0 }
>> diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
>> index d290d7f3e21..f8a7436d9dd 100644
>> --- a/gcc/common/common-targhooks.h
>> +++ b/gcc/common/common-targhooks.h
>> @@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
>>  					  struct gcc_options *,
>>  					  const struct cl_decoded_option *,
>>  					  location_t);
>> +extern vec<const char *> default_get_valid_option_values (int);
>>  
>>  extern const struct default_options empty_optimization_table[];
>>  
>> diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
>> index 70b3c3f2fc3..e7253b60c36 100644
>> --- a/gcc/common/config/i386/i386-common.c
>> +++ b/gcc/common/config/i386/i386-common.c
>> @@ -1459,4 +1459,268 @@ i386_except_unwind_info (struct gcc_options *opts)
>>  #undef TARGET_SUPPORTS_SPLIT_STACK
>>  #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
>>  
>> +/* This table must be in sync with enum processor_type in i386.h.  */
>> +const struct ptt processor_target_table[PROCESSOR_max] =
>> +{
>> +  /* The "0:0:8" label alignment specified for some processors generates
>> +     secondary 8-byte alignment only for those label/jump/loop targets
>> +     which have primary alignment.  */
>> +
>> +  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"i386",           "4",       "4",       NULL,    "4" },
>> +  {"i486",           "16",      "16",      "0:0:8", "16"},
>> +  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> +  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> +  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
>> +  {"pentium4",       NULL,      NULL,      NULL,    NULL},
>> +  {"nocona",         NULL,      NULL,      NULL,    NULL},
>> +  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
>> +  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
>> +  {"geode",          NULL,      NULL,      NULL,    NULL},
>> +  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
>> +  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> +  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> +  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
>> +  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>> +  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>> +  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>> +  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>> +  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>> +  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>> +  {"znver1",         "16",      "16",      "0:0:8", "16"}
>> +};
>> +
>> +const pta processor_alias_table[] =
>> +{
>> +  {"i386", PROCESSOR_I386, CPU_NONE, 0},
>> +  {"i486", PROCESSOR_I486, CPU_NONE, 0},
>> +  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>> +  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>> +  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>> +  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>> +  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>> +  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>> +  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>> +  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>> +  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>> +  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>> +  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> +  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> +  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>> +  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>> +  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>> +  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>> +  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>> +  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>> +  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>> +    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>> +  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>> +  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> +  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>> +  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>> +  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>> +  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>> +  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> +    PTA_SANDYBRIDGE},
>> +  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> +    PTA_SANDYBRIDGE},
>> +  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> +    PTA_IVYBRIDGE},
>> +  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> +    PTA_IVYBRIDGE},
>> +  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>> +  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>> +  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>> +  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>> +  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>> +    PTA_SKYLAKE_AVX512},
>> +  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>> +  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>> +    PTA_ICELAKE_CLIENT},
>> +  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>> +    PTA_ICELAKE_SERVER},
>> +  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>> +  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>> +  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>> +  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>> +  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>> +  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>> +  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>> +  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>> +  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>> +  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>> +  {"geode", PROCESSOR_GEODE, CPU_GEODE,
>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>> +  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>> +  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>> +  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>> +  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>> +  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>> +  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>> +  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>> +  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>> +  {"x86-64", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"eden-x2", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> +  {"nano", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_FXSR},
>> +  {"nano-1000", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_FXSR},
>> +  {"nano-2000", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_FXSR},
>> +  {"nano-3000", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> +  {"nano-x2", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> +  {"eden-x4", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> +  {"nano-x4", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> +  {"k8", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"k8-sse3", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"opteron", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"athlon64", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"athlon-fx", PROCESSOR_K8, CPU_K8,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> +  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>> +  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>> +  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>> +      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>> +  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>> +  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
>> +      | PTA_XSAVEOPT | PTA_FSGSBASE},
>> +  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>> +      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
>> +      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
>> +      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>> +      | PTA_MOVBE | PTA_MWAITX},
>> +  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>> +      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>> +      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>> +      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>> +      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>> +  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>> +      | PTA_FXSR | PTA_XSAVE},
>> +  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>> +      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>> +
>> +  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>> +    PTA_64BIT
>> +      | PTA_HLE /* flags are only used for -march switch.  */ },
>> +};
>> +
>> +int const pta_size = ARRAY_SIZE (processor_alias_table);
>> +
>> +vec<const char *>
>> +ix86_get_valid_option_values (int option)
>> +{
>> +  vec<const char *> v;
>> +  v.create (0);
>> +  opt_code opt = (opt_code) option;
>> +
>> +  switch (opt)
>> +    {
>> +    case OPT_march_:
>> +      for (unsigned i = 0; i < pta_size; i++)
>> +	v.safe_push (processor_alias_table[i].name);
>> +      break;
>> +    case OPT_mtune_:
>> +      for (unsigned i = 0; i < PROCESSOR_max; i++)
>> +	v.safe_push (processor_target_table[i].name);
>> +      break;
>> +    default:
>> +      break;
>> +    }
>> +
>> +  return v;
>> +}
>> +
>> +#undef  TARGET_GET_VALID_OPTION_VALUES
>> +#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
>> +
>>  struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
>> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
>> index 2b7e9489ed8..b4d0942188f 100644
>> --- a/gcc/config/i386/i386.c
>> +++ b/gcc/config/i386/i386.c
>> @@ -832,63 +832,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
>>  static tree ix86_veclibabi_svml (combined_fn, tree, tree);
>>  static tree ix86_veclibabi_acml (combined_fn, tree, tree);
>>  
>> -/* Processor target table, indexed by processor number */
>> -struct ptt
>> -{
>> -  const char *const name;			/* processor name  */
>> -  const struct processor_costs *cost;		/* Processor costs */
>> -
>> -  /* Default alignments.  */
>> -  const char *const align_loop;
>> -  const char *const align_jump;
>> -  const char *const align_label;
>> -  const char *const align_func;
>> -};
>> -
>>  /* This table must be in sync with enum processor_type in i386.h.  */ 
>> -static const struct ptt processor_target_table[PROCESSOR_max] =
>> -{
>> -/* The "0:0:8" label alignment specified for some processors generates
>> -   secondary 8-byte alignment only for those label/jump/loop targets
>> -   which have primary alignment.  */
>> -
>> -  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
>> -  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
>> -  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> -  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> -  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
>> -  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
>> -  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
>> -  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
>> -  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>> -  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>> -  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>> -  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
>> -  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>> -  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>> -  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>> -  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
>> -  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
>> -  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
>> -  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> -  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>> -  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
>> -  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>> -  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>> -  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>> -  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>> -  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>> -  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>> -  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
>> +static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
>> +{
>> +  &generic_cost,
>> +  &i386_cost,
>> +  &i486_cost,
>> +  &pentium_cost,
>> +  &lakemont_cost,
>> +  &pentiumpro_cost,
>> +  &pentium4_cost,
>> +  &nocona_cost,
>> +  &core_cost,
>> +  &core_cost,
>> +  &core_cost,
>> +  &core_cost,
>> +  &atom_cost,
>> +  &slm_cost,
>> +  &slm_cost,
>> +  &slm_cost,
>> +  &slm_cost,
>> +  &slm_cost,
>> +  &slm_cost,
>> +  &skylake_cost,
>> +  &skylake_cost,
>> +  &skylake_cost,
>> +  &skylake_cost,
>> +  &skylake_cost,
>> +  &intel_cost,
>> +  &geode_cost,
>> +  &k6_cost,
>> +  &athlon_cost,
>> +  &k8_cost,
>> +  &amdfam10_cost,
>> +  &bdver1_cost,
>> +  &bdver2_cost,
>> +  &bdver3_cost,
>> +  &bdver4_cost,
>> +  &btver1_cost,
>> +  &btver2_cost,
>> +  &znver1_cost,
>>  };
>>  \f
>>  static unsigned int
>> @@ -3392,6 +3375,8 @@ ix86_override_options_after_change (void)
>>    ix86_default_align (&global_options);
>>  }
>>  
>> +
>> +
>>  /* Override various settings based on options.  If MAIN_ARGS_P, the
>>     options are from the command line, otherwise they are from
>>     attributes.  Return true if there's an error related to march
>> @@ -3406,317 +3391,6 @@ ix86_option_override_internal (bool main_args_p,
>>    unsigned HOST_WIDE_INT ix86_arch_mask;
>>    const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
>>  
>> -  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>> -  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>> -  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>> -  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>> -  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>> -  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>> -  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>> -  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>> -  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>> -  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>> -  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>> -  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>> -  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>> -  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>> -  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>> -  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>> -  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>> -  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>> -  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>> -  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>> -  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>> -  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>> -  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>> -  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>> -  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>> -  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>> -  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>> -  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>> -  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>> -  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>> -  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>> -  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>> -  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>> -  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>> -  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>> -  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>> -  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>> -  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>> -  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>> -  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>> -  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>> -  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>> -  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>> -  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>> -  /* Hole after PTA_MPX was removed.  */
>> -  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>> -  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>> -  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>> -  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>> -  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>> -  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>> -  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>> -  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>> -  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>> -  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>> -  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>> -  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>> -  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>> -  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>> -  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>> -  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>> -  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>> -  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>> -  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>> -  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>> -  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>> -  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>> -  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>> -  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>> -  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>> -  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>> -  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>> -  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>> -  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>> -
>> -  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>> -    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>> -  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>> -    | PTA_POPCNT;
>> -  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>> -  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>> -    | PTA_XSAVEOPT;
>> -  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>> -    | PTA_RDRND | PTA_F16C;
>> -  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>> -    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>> -  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>> -    | PTA_RDSEED;
>> -  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>> -    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>> -  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>> -    | PTA_CLWB;
>> -  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>> -    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>> -  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>> -    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>> -    | PTA_RDPID | PTA_CLWB;
>> -  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>> -    | PTA_WBNOINVD;
>> -  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>> -    | PTA_AVX512F | PTA_AVX512CD;
>> -  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>> -  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>> -  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>> -    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>> -    | PTA_FSGSBASE;
>> -  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>> -    | PTA_SGX;
>> -  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>> -    | PTA_GFNI;
>> -  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>> -    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>> -
>> -  static struct pta
>> -    {
>> -      const char *const name;		/* processor name or nickname.  */
>> -      const enum processor_type processor;
>> -      const enum attr_cpu schedule;
>> -      const wide_int_bitmask flags;
>> -    }
>> -  const processor_alias_table[] =
>> -    {
>> -      {"i386", PROCESSOR_I386, CPU_NONE, 0},
>> -      {"i486", PROCESSOR_I486, CPU_NONE, 0},
>> -      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>> -      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>> -      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>> -      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>> -      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>> -      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>> -      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>> -      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>> -      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>> -      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> -        PTA_MMX | PTA_SSE | PTA_FXSR},
>> -      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> -      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> -      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>> -      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>> -      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>> -      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>> -      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>> -      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>> -      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>> -	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>> -      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>> -      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> -      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>> -      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>> -      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>> -      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>> -      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> -	PTA_SANDYBRIDGE},
>> -      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> -	PTA_SANDYBRIDGE},
>> -      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> -	PTA_IVYBRIDGE},
>> -      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>> -	PTA_IVYBRIDGE},
>> -      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>> -      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>> -      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>> -      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>> -      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>> -        PTA_SKYLAKE_AVX512},
>> -      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>> -      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>> -	PTA_ICELAKE_CLIENT},
>> -      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>> -	PTA_ICELAKE_SERVER},
>> -      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>> -      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>> -      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>> -      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>> -      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>> -      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>> -      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>> -      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>> -      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>> -      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>> -      {"geode", PROCESSOR_GEODE, CPU_GEODE,
>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>> -      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>> -      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>> -      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>> -      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>> -      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>> -      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>> -      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>> -      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>> -      {"x86-64", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"eden-x2", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>> -      {"nano", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -        | PTA_SSSE3 | PTA_FXSR},
>> -      {"nano-1000", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -        | PTA_SSSE3 | PTA_FXSR},
>> -      {"nano-2000", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -        | PTA_SSSE3 | PTA_FXSR},
>> -      {"nano-3000", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> -      {"nano-x2", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> -      {"eden-x4", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> -      {"nano-x4", PROCESSOR_K8, CPU_K8,
>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>> -      {"k8", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"k8-sse3", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"opteron", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"athlon64", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"athlon-fx", PROCESSOR_K8, CPU_K8,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>> -      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>> -      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>> -      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>> -	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>> -      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>> -      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
>> -	| PTA_XSAVEOPT | PTA_FSGSBASE},
>> -      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
>> -	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
>> -	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
>> -	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>> -	| PTA_MOVBE | PTA_MWAITX},
>> -      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>> -	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>> -	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>> -	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>> -	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>> -      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>> -	| PTA_FXSR | PTA_XSAVE},
>> -      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>> -	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>> -
>> -      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>> -	PTA_64BIT
>> -	| PTA_HLE /* flags are only used for -march switch.  */ },
>> -    };
>> -
>>    /* -mrecip options.  */
>>    static struct
>>      {
>> @@ -3733,7 +3407,6 @@ ix86_option_override_internal (bool main_args_p,
>>        { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
>>      };
>>  
>> -  int const pta_size = ARRAY_SIZE (processor_alias_table);
>>  
>>    /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
>>       TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
>> @@ -4389,7 +4062,7 @@ ix86_option_override_internal (bool main_args_p,
>>  	}
>>      }
>>  
>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>    if (opts->x_optimize_size)
>> @@ -5186,7 +4859,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
>>    opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
>>    opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
>>    opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>    if (opts->x_optimize_size)
>> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
>> index fbba598ffd5..cc7fc1fd443 100644
>> --- a/gcc/config/i386/i386.h
>> +++ b/gcc/config/i386/i386.h
>> @@ -2283,6 +2283,150 @@ enum processor_type
>>    PROCESSOR_max
>>  };
>>  
>> +/* Processor target table, indexed by processor number */
>> +struct ptt
>> +{
>> +  const char *const name;			/* processor name  */
>> +
>> +  /* Default alignments.  */
>> +  const char *const align_loop;
>> +  const char *const align_jump;
>> +  const char *const align_label;
>> +  const char *const align_func;
>> +};
>> +
>> +extern const struct ptt processor_target_table[PROCESSOR_max];
>> +
>> +#include "wide-int-bitmask.h"
>> +
>> +const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>> +const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>> +const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>> +const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>> +const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>> +const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>> +const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>> +const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>> +const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>> +const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>> +const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>> +const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>> +const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>> +const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>> +const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>> +const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>> +const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>> +const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>> +const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>> +const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>> +const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>> +const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>> +const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>> +const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>> +const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>> +const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>> +const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>> +const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>> +const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>> +const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>> +const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>> +const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>> +const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>> +const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>> +const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>> +const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>> +const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>> +const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>> +const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>> +const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>> +const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>> +const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>> +const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>> +const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>> +/* Hole after PTA_MPX was removed.  */
>> +const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>> +const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>> +const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>> +const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>> +const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>> +const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>> +const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>> +const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>> +const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>> +const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>> +const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>> +const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>> +const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>> +const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>> +const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>> +const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>> +const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>> +const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>> +const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>> +const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>> +const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>> +const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>> +const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>> +const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>> +const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>> +const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>> +const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>> +const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>> +const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>> +
>> +const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>> +  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>> +const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>> +  | PTA_POPCNT;
>> +const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>> +const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>> +  | PTA_XSAVEOPT;
>> +const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>> +  | PTA_RDRND | PTA_F16C;
>> +const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>> +  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>> +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>> +  | PTA_RDSEED;
>> +const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>> +  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>> +const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>> +  | PTA_CLWB;
>> +const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>> +  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>> +const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>> +  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>> +  | PTA_RDPID | PTA_CLWB;
>> +const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>> +  | PTA_WBNOINVD;
>> +const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>> +  | PTA_AVX512F | PTA_AVX512CD;
>> +const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>> +const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>> +const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>> +  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>> +  | PTA_FSGSBASE;
>> +const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>> +  | PTA_SGX;
>> +const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>> +  | PTA_GFNI;
>> +const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>> +  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>> +
>> +#include "insn-attr-common.h"
>> +
>> +struct pta
>> +{
>> +  const char *const name;		/* processor name or nickname.  */
>> +  const enum processor_type processor;
>> +  const enum attr_cpu schedule;
>> +  const wide_int_bitmask flags;
>> +};
>> +
>> +extern const pta processor_alias_table[];
>> +extern int const pta_size;
>> +
>>  extern enum processor_type ix86_tune;
>>  extern enum processor_type ix86_arch;
>>  
>> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
>> index 0ddcd1aa2ac..c743a7d0dc0 100644
>> --- a/gcc/doc/tm.texi
>> +++ b/gcc/doc/tm.texi
>> @@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
>>  Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
>>  @end deftypefn
>>  
>> +@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int)
>> +The hook is used for options that have a non-trivial list of possible option values.
>> +@end deftypefn
>> +
>>  @node Miscellaneous Register Hooks
>>  @subsection Miscellaneous register hooks
>>  @cindex miscellaneous register hooks
>> diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
>> index e275aca0eec..3fbcbea820b 100644
>> --- a/gcc/doc/tm.texi.in
>> +++ b/gcc/doc/tm.texi.in
>> @@ -3669,6 +3669,8 @@ generic code.
>>  
>>  @hook TARGET_SUPPORTS_SPLIT_STACK
>>  
>> +@hook TARGET_GET_VALID_OPTION_VALUES
>> +
>>  @node Miscellaneous Register Hooks
>>  @subsection Miscellaneous register hooks
>>  @cindex miscellaneous register hooks
>> diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
>> index 894eea5f37c..6f3f071a171 100644
>> --- a/gcc/opt-suggestions.c
>> +++ b/gcc/opt-suggestions.c
>> @@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
>>  #include "params.h"
>>  #include "spellcheck.h"
>>  #include "opt-suggestions.h"
>> +#include "common/common-target.h"
>>  #include "selftest.h"
>>  
>>  option_proposer::~option_proposer ()
>> @@ -135,8 +136,24 @@ option_proposer::build_option_suggestions (void)
>>  		}
>>  	    }
>>  	  else
>> -	    add_misspelling_candidates (m_option_suggestions, option,
>> -					opt_text);
>> +	    {
>> +	      vec<const char *> option_values
>> +		= targetm_common.get_valid_option_values (i);
>> +	      if (!option_values.is_empty ())
>> +		{
>> +		  for (unsigned j = 0; j < option_values.length (); j++)
>> +		    {
>> +		      char *with_arg = concat (opt_text, option_values[j],
>> +					       NULL);
>> +		      add_misspelling_candidates (m_option_suggestions, option,
>> +						  with_arg);
>> +		      free (with_arg);
>> +		    }
>> +		}
>> +	      else
>> +		add_misspelling_candidates (m_option_suggestions, option,
>> +					    opt_text);
>> +	    }
>>  	  break;
>>  
>>  	case OPT_fsanitize_:
>> diff --git a/gcc/opts.c b/gcc/opts.c
>> index b8ae8756b4f..97cfd8f455c 100644
>> --- a/gcc/opts.c
>> +++ b/gcc/opts.c
>> @@ -1090,6 +1090,21 @@ wrap_help (const char *help,
>>    while (remaining);
>>  }
>>  
>> +/* Data structure used to print list of valid option values.  */
>> +
>> +struct option_help_tuple
>> +{
>> +  option_help_tuple (int code, vec<const char *> values):
>> +    m_code (code), m_values (values)
>> +  {}
>> +
>> +  /* Code of an option.  */
>> +  int m_code;
>> +
>> +  /* List of possible values.  */
>> +  vec<const char *> m_values;
>> +};
>> +
>>  /* Print help for a specific front-end, etc.  */
>>  static void
>>  print_filtered_help (unsigned int include_flags,
>> @@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
>>    if (!opts->x_help_enum_printed)
>>      opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
>>  
>> +  auto_vec<option_help_tuple> help_tuples;
>> +
>>    for (i = 0; i < cl_options_count; i++)
>>      {
>>        const struct cl_option *option = cl_options + i;
>> @@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
>>        if (option->var_type == CLVC_ENUM
>>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>>  	opts->x_help_enum_printed[option->var_enum] = 1;
>> +      else
>> +	{
>> +	  vec<const char *> option_values
>> +	    = targetm_common.get_valid_option_values (i);
>> +	  if (!option_values.is_empty ())
>> +	    help_tuples.safe_push (option_help_tuple (i, option_values));
>> +	}
>>      }
>>  
>>    if (! found)
>> @@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
>>        printf ("\n\n");
>>        opts->x_help_enum_printed[i] = 2;
>>      }
>> +
>> +  for (unsigned i = 0; i < help_tuples.length (); i++)
>> +    {
>> +      const struct cl_option *option = cl_options + help_tuples[i].m_code;
>> +      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
>> +      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
>> +	printf (" %s", help_tuples[i].m_values[j]);
>> +      printf ("\n\n");
>> +    }
>>  }
>>  
>>  /* Display help for a specified type of option.
>>
> 

Re: [PATCH] Prototype of hook for possible list of option values.

[Richard Earnshaw (lists)]

On 20/07/18 11:14, Martin Liška wrote:
> On 07/20/2018 11:48 AM, Richard Earnshaw (lists) wrote:
>> On 20/07/18 09:04, Martin Liška wrote:
>>> Hi.
>>>
>>> I'm sending patch candidate with suggested target common hook. It allows a target
>>> to list all possible values for an option. Using the API, I implemented -march and
>>> -mtune option listing on i386.
>>>
>>> Richard you asked about the values. Yes, target should list all possible values,
>>> mainly because --help=target output needs all of these.
>>>
>>> Thoughts?
>>> Martin
>>>
>>
>> I don't think anyone can reasonably write an implementation of this hook
>> based on this specification:
>>
>> +@deftypefn {Common Target Hook} {vec<const char *>}
>> TARGET_GET_VALID_OPTION_VALUES (int)
>> +The hook is used for options that have a non-trivial list of possible
>> option values.
>> +@end deftypefn
>> +
>>
>> What's the int parameter for?  What's the lifetime of the result (who
>> cleans it up)?  If I need to allocation memory strings in the vector,
>> where do I do that?  Can I assume GC memory in the driver, for example?
> 
> Sure, can be improved, please take it as prototype.
> 
>>
>> Frankly though, I don't really want to enumerate every possible
>> permutation of the options for the architecture like this, though.  It's
>> just too brute force and the answer is likely to be hundreds (haven't
> 
> That's why I recommended you to list in --help=target content of
> arm_arch enum. You replied that it's not complete list of all possible values.
> Note that we are talking about content of --help option, it's not a documentation,
> it should just help users. Similar to bash completion, it should not be 100% perfect.
> 
>> sat down to count it).  What's more, the extensions might have meaning
>> in the order in which they appear.  So, for example,
>>
>> 	-march=armv8-a+crypto+nosimd
>>
>> would be very different from
>>
>> 	-march=armv8-a+nosimd+crypto
>>
>> since the extensions are applied from left to right (the first collapses
>> to armv8-a+nosimd, the latter to armv8-a+crypto, but there are more
>> complex cases as well which I don't want to dig into here).
>>
>> It would be a practical impossibility to list all of these.
> 
> Yes, that's why I recommended to list only base march values. Modifiers can be mentioned
> aside if desired.

So it might be feasible to print something like:

  arch1[+ext1|+ext2]*
  arch2[+ext1|+ext3|...]*

etc.  That at least would be a concise summary of the options.  Whether
or not automated tools could handle that is another matter.

R.

> 
> Martin
> 
>>
>> R.
>>
>>>
>>> 0001-Prototype-of-hook-for-possible-list-of-option-values.patch
>>>
>>>
>>> From b2b40f7ca1f801a318aec661d0128a5adde7cb68 Mon Sep 17 00:00:00 2001
>>> From: marxin <mliska@suse.cz>
>>> Date: Fri, 20 Jul 2018 09:58:16 +0200
>>> Subject: [PATCH] Prototype of hook for possible list of option values.
>>>
>>> ---
>>>  gcc/common/common-target.def         |   7 +
>>>  gcc/common/common-targhooks.c        |   7 +
>>>  gcc/common/common-targhooks.h        |   1 +
>>>  gcc/common/config/i386/i386-common.c | 264 +++++++++++++++++
>>>  gcc/config/i386/i386.c               | 413 +++------------------------
>>>  gcc/config/i386/i386.h               | 144 ++++++++++
>>>  gcc/doc/tm.texi                      |   4 +
>>>  gcc/doc/tm.texi.in                   |   2 +
>>>  gcc/opt-suggestions.c                |  21 +-
>>>  gcc/opts.c                           |  33 +++
>>>  10 files changed, 524 insertions(+), 372 deletions(-)
>>>
>>> diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
>>> index e0afbc6af29..8c98598b015 100644
>>> --- a/gcc/common/common-target.def
>>> +++ b/gcc/common/common-target.def
>>> @@ -80,6 +80,13 @@ DEFHOOK
>>>   bool, (bool report, struct gcc_options *opts),
>>>   hook_bool_bool_gcc_optionsp_false)
>>>  
>>> +DEFHOOK
>>> +(get_valid_option_values,
>>> +"The hook is used for options that have a non-trivial list of\
>>> + possible option values.",
>>> + vec<const char *>, (int),
>>> + default_get_valid_option_values)
>>> +
>>>  /* Leave the boolean fields at the end.  */
>>>  
>>>  /* True if unwinding tables should be generated by default.  */
>>> diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
>>> index b1090190664..3662180f2e0 100644
>>> --- a/gcc/common/common-targhooks.c
>>> +++ b/gcc/common/common-targhooks.c
>>> @@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
>>>  #include "tm.h"
>>>  #include "common/common-target.h"
>>>  #include "common/common-targhooks.h"
>>> +#include "opts.h"
>>>  
>>>  /* Determine the exception handling mechanism for the target.  */
>>>  
>>> @@ -77,6 +78,12 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
>>>    return true;
>>>  }
>>>  
>>> +vec<const char *>
>>> +default_get_valid_option_values (int option)
>>> +{
>>> +  return vec<const char *> ();
>>> +}
>>> +
>>>  const struct default_options empty_optimization_table[] =
>>>    {
>>>      { OPT_LEVELS_NONE, 0, NULL, 0 }
>>> diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
>>> index d290d7f3e21..f8a7436d9dd 100644
>>> --- a/gcc/common/common-targhooks.h
>>> +++ b/gcc/common/common-targhooks.h
>>> @@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
>>>  					  struct gcc_options *,
>>>  					  const struct cl_decoded_option *,
>>>  					  location_t);
>>> +extern vec<const char *> default_get_valid_option_values (int);
>>>  
>>>  extern const struct default_options empty_optimization_table[];
>>>  
>>> diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
>>> index 70b3c3f2fc3..e7253b60c36 100644
>>> --- a/gcc/common/config/i386/i386-common.c
>>> +++ b/gcc/common/config/i386/i386-common.c
>>> @@ -1459,4 +1459,268 @@ i386_except_unwind_info (struct gcc_options *opts)
>>>  #undef TARGET_SUPPORTS_SPLIT_STACK
>>>  #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
>>>  
>>> +/* This table must be in sync with enum processor_type in i386.h.  */
>>> +const struct ptt processor_target_table[PROCESSOR_max] =
>>> +{
>>> +  /* The "0:0:8" label alignment specified for some processors generates
>>> +     secondary 8-byte alignment only for those label/jump/loop targets
>>> +     which have primary alignment.  */
>>> +
>>> +  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"i386",           "4",       "4",       NULL,    "4" },
>>> +  {"i486",           "16",      "16",      "0:0:8", "16"},
>>> +  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> +  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> +  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
>>> +  {"pentium4",       NULL,      NULL,      NULL,    NULL},
>>> +  {"nocona",         NULL,      NULL,      NULL,    NULL},
>>> +  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
>>> +  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
>>> +  {"geode",          NULL,      NULL,      NULL,    NULL},
>>> +  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
>>> +  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> +  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> +  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
>>> +  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> +  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> +  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> +  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> +  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> +  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> +  {"znver1",         "16",      "16",      "0:0:8", "16"}
>>> +};
>>> +
>>> +const pta processor_alias_table[] =
>>> +{
>>> +  {"i386", PROCESSOR_I386, CPU_NONE, 0},
>>> +  {"i486", PROCESSOR_I486, CPU_NONE, 0},
>>> +  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>> +  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>> +  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>>> +  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>>> +  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>>> +  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>> +  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>> +  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>> +  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>> +  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>> +  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> +  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> +  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>> +  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>> +  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>>> +  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>> +  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>> +  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>> +  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>>> +    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>> +  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>> +  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> +  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>>> +  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>> +  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>> +  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>>> +  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> +    PTA_SANDYBRIDGE},
>>> +  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> +    PTA_SANDYBRIDGE},
>>> +  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> +    PTA_IVYBRIDGE},
>>> +  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> +    PTA_IVYBRIDGE},
>>> +  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>> +  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>> +  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>>> +  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>>> +  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>>> +    PTA_SKYLAKE_AVX512},
>>> +  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>>> +  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>>> +    PTA_ICELAKE_CLIENT},
>>> +  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>>> +    PTA_ICELAKE_SERVER},
>>> +  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>> +  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>> +  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>> +  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>> +  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>>> +  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>>> +  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>>> +  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>>> +  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>>> +  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>>> +  {"geode", PROCESSOR_GEODE, CPU_GEODE,
>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>> +  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>>> +  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>> +  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>> +  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>> +  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>> +  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>> +  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>> +  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>> +  {"x86-64", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"eden-x2", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> +  {"nano", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_FXSR},
>>> +  {"nano-1000", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_FXSR},
>>> +  {"nano-2000", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_FXSR},
>>> +  {"nano-3000", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> +  {"nano-x2", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> +  {"eden-x4", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> +  {"nano-x4", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> +  {"k8", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"k8-sse3", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"opteron", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"athlon64", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"athlon-fx", PROCESSOR_K8, CPU_K8,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> +  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>> +  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>> +  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>> +      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>> +  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>> +  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
>>> +      | PTA_XSAVEOPT | PTA_FSGSBASE},
>>> +  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>> +      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
>>> +      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
>>> +      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>>> +      | PTA_MOVBE | PTA_MWAITX},
>>> +  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>> +      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>>> +      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>>> +      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>>> +      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>>> +  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>>> +      | PTA_FXSR | PTA_XSAVE},
>>> +  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>>> +      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>> +
>>> +  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>>> +    PTA_64BIT
>>> +      | PTA_HLE /* flags are only used for -march switch.  */ },
>>> +};
>>> +
>>> +int const pta_size = ARRAY_SIZE (processor_alias_table);
>>> +
>>> +vec<const char *>
>>> +ix86_get_valid_option_values (int option)
>>> +{
>>> +  vec<const char *> v;
>>> +  v.create (0);
>>> +  opt_code opt = (opt_code) option;
>>> +
>>> +  switch (opt)
>>> +    {
>>> +    case OPT_march_:
>>> +      for (unsigned i = 0; i < pta_size; i++)
>>> +	v.safe_push (processor_alias_table[i].name);
>>> +      break;
>>> +    case OPT_mtune_:
>>> +      for (unsigned i = 0; i < PROCESSOR_max; i++)
>>> +	v.safe_push (processor_target_table[i].name);
>>> +      break;
>>> +    default:
>>> +      break;
>>> +    }
>>> +
>>> +  return v;
>>> +}
>>> +
>>> +#undef  TARGET_GET_VALID_OPTION_VALUES
>>> +#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
>>> +
>>>  struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
>>> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
>>> index 2b7e9489ed8..b4d0942188f 100644
>>> --- a/gcc/config/i386/i386.c
>>> +++ b/gcc/config/i386/i386.c
>>> @@ -832,63 +832,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
>>>  static tree ix86_veclibabi_svml (combined_fn, tree, tree);
>>>  static tree ix86_veclibabi_acml (combined_fn, tree, tree);
>>>  
>>> -/* Processor target table, indexed by processor number */
>>> -struct ptt
>>> -{
>>> -  const char *const name;			/* processor name  */
>>> -  const struct processor_costs *cost;		/* Processor costs */
>>> -
>>> -  /* Default alignments.  */
>>> -  const char *const align_loop;
>>> -  const char *const align_jump;
>>> -  const char *const align_label;
>>> -  const char *const align_func;
>>> -};
>>> -
>>>  /* This table must be in sync with enum processor_type in i386.h.  */ 
>>> -static const struct ptt processor_target_table[PROCESSOR_max] =
>>> -{
>>> -/* The "0:0:8" label alignment specified for some processors generates
>>> -   secondary 8-byte alignment only for those label/jump/loop targets
>>> -   which have primary alignment.  */
>>> -
>>> -  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
>>> -  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
>>> -  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> -  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> -  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
>>> -  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
>>> -  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
>>> -  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
>>> -  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>> -  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>> -  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>> -  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
>>> -  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>> -  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>> -  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>> -  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
>>> -  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
>>> -  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
>>> -  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> -  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>> -  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
>>> -  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> -  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> -  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> -  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> -  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> -  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>> -  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
>>> +static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
>>> +{
>>> +  &generic_cost,
>>> +  &i386_cost,
>>> +  &i486_cost,
>>> +  &pentium_cost,
>>> +  &lakemont_cost,
>>> +  &pentiumpro_cost,
>>> +  &pentium4_cost,
>>> +  &nocona_cost,
>>> +  &core_cost,
>>> +  &core_cost,
>>> +  &core_cost,
>>> +  &core_cost,
>>> +  &atom_cost,
>>> +  &slm_cost,
>>> +  &slm_cost,
>>> +  &slm_cost,
>>> +  &slm_cost,
>>> +  &slm_cost,
>>> +  &slm_cost,
>>> +  &skylake_cost,
>>> +  &skylake_cost,
>>> +  &skylake_cost,
>>> +  &skylake_cost,
>>> +  &skylake_cost,
>>> +  &intel_cost,
>>> +  &geode_cost,
>>> +  &k6_cost,
>>> +  &athlon_cost,
>>> +  &k8_cost,
>>> +  &amdfam10_cost,
>>> +  &bdver1_cost,
>>> +  &bdver2_cost,
>>> +  &bdver3_cost,
>>> +  &bdver4_cost,
>>> +  &btver1_cost,
>>> +  &btver2_cost,
>>> +  &znver1_cost,
>>>  };
>>>  \f
>>>  static unsigned int
>>> @@ -3392,6 +3375,8 @@ ix86_override_options_after_change (void)
>>>    ix86_default_align (&global_options);
>>>  }
>>>  
>>> +
>>> +
>>>  /* Override various settings based on options.  If MAIN_ARGS_P, the
>>>     options are from the command line, otherwise they are from
>>>     attributes.  Return true if there's an error related to march
>>> @@ -3406,317 +3391,6 @@ ix86_option_override_internal (bool main_args_p,
>>>    unsigned HOST_WIDE_INT ix86_arch_mask;
>>>    const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
>>>  
>>> -  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>>> -  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>>> -  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>>> -  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>>> -  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>>> -  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>>> -  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>>> -  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>>> -  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>>> -  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>>> -  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>>> -  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>>> -  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>>> -  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>>> -  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>>> -  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>>> -  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>>> -  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>>> -  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>>> -  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>>> -  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>>> -  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>>> -  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>>> -  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>>> -  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>>> -  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>>> -  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>>> -  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>>> -  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>>> -  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>>> -  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>>> -  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>>> -  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>>> -  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>>> -  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>>> -  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>>> -  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>>> -  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>>> -  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>>> -  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>>> -  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>>> -  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>>> -  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>>> -  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>>> -  /* Hole after PTA_MPX was removed.  */
>>> -  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>>> -  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>>> -  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>>> -  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>>> -  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>>> -  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>>> -  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>>> -  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>>> -  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>>> -  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>>> -  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>>> -  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>>> -  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>>> -  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>>> -  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>>> -  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>>> -  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>>> -  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>>> -  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>>> -  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>>> -  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>>> -  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>>> -  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>>> -  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>>> -  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>>> -  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>>> -  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>>> -  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>>> -  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>>> -
>>> -  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>>> -    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>>> -  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>>> -    | PTA_POPCNT;
>>> -  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>>> -  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>>> -    | PTA_XSAVEOPT;
>>> -  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>>> -    | PTA_RDRND | PTA_F16C;
>>> -  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>>> -    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>>> -  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>>> -    | PTA_RDSEED;
>>> -  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>>> -    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>>> -  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>> -    | PTA_CLWB;
>>> -  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>> -    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>>> -  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>>> -    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>>> -    | PTA_RDPID | PTA_CLWB;
>>> -  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>>> -    | PTA_WBNOINVD;
>>> -  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>>> -    | PTA_AVX512F | PTA_AVX512CD;
>>> -  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>>> -  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>>> -  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>>> -    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>>> -    | PTA_FSGSBASE;
>>> -  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>>> -    | PTA_SGX;
>>> -  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>>> -    | PTA_GFNI;
>>> -  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>>> -    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>>> -
>>> -  static struct pta
>>> -    {
>>> -      const char *const name;		/* processor name or nickname.  */
>>> -      const enum processor_type processor;
>>> -      const enum attr_cpu schedule;
>>> -      const wide_int_bitmask flags;
>>> -    }
>>> -  const processor_alias_table[] =
>>> -    {
>>> -      {"i386", PROCESSOR_I386, CPU_NONE, 0},
>>> -      {"i486", PROCESSOR_I486, CPU_NONE, 0},
>>> -      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>> -      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>> -      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>>> -      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>>> -      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>>> -      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>> -      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>> -      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>> -      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>> -      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> -        PTA_MMX | PTA_SSE | PTA_FXSR},
>>> -      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> -      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> -      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>> -      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>> -      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>>> -      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>> -      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>> -      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>> -      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>>> -	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>> -      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>> -      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> -      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>>> -      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>> -      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>> -      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>>> -      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> -	PTA_SANDYBRIDGE},
>>> -      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> -	PTA_SANDYBRIDGE},
>>> -      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> -	PTA_IVYBRIDGE},
>>> -      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>> -	PTA_IVYBRIDGE},
>>> -      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>> -      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>> -      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>>> -      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>>> -      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>>> -        PTA_SKYLAKE_AVX512},
>>> -      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>>> -      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>>> -	PTA_ICELAKE_CLIENT},
>>> -      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>>> -	PTA_ICELAKE_SERVER},
>>> -      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>> -      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>> -      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>> -      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>> -      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>>> -      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>>> -      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>>> -      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>>> -      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>>> -      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>>> -      {"geode", PROCESSOR_GEODE, CPU_GEODE,
>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>> -      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>>> -      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>> -      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>> -      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>> -      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>> -      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>> -      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>> -      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>> -      {"x86-64", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"eden-x2", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>> -      {"nano", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -        | PTA_SSSE3 | PTA_FXSR},
>>> -      {"nano-1000", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -        | PTA_SSSE3 | PTA_FXSR},
>>> -      {"nano-2000", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -        | PTA_SSSE3 | PTA_FXSR},
>>> -      {"nano-3000", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> -      {"nano-x2", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> -      {"eden-x4", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> -      {"nano-x4", PROCESSOR_K8, CPU_K8,
>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>> -      {"k8", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"k8-sse3", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"opteron", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"athlon64", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"athlon-fx", PROCESSOR_K8, CPU_K8,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>> -      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>> -      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>> -      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>> -	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>> -      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>> -      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
>>> -	| PTA_XSAVEOPT | PTA_FSGSBASE},
>>> -      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
>>> -	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
>>> -	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
>>> -	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>>> -	| PTA_MOVBE | PTA_MWAITX},
>>> -      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>> -	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>>> -	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>>> -	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>>> -	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>>> -      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>>> -	| PTA_FXSR | PTA_XSAVE},
>>> -      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>>> -	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>> -
>>> -      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>>> -	PTA_64BIT
>>> -	| PTA_HLE /* flags are only used for -march switch.  */ },
>>> -    };
>>> -
>>>    /* -mrecip options.  */
>>>    static struct
>>>      {
>>> @@ -3733,7 +3407,6 @@ ix86_option_override_internal (bool main_args_p,
>>>        { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
>>>      };
>>>  
>>> -  int const pta_size = ARRAY_SIZE (processor_alias_table);
>>>  
>>>    /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
>>>       TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
>>> @@ -4389,7 +4062,7 @@ ix86_option_override_internal (bool main_args_p,
>>>  	}
>>>      }
>>>  
>>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>>    if (opts->x_optimize_size)
>>> @@ -5186,7 +4859,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
>>>    opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
>>>    opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
>>>    opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
>>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>>    if (opts->x_optimize_size)
>>> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
>>> index fbba598ffd5..cc7fc1fd443 100644
>>> --- a/gcc/config/i386/i386.h
>>> +++ b/gcc/config/i386/i386.h
>>> @@ -2283,6 +2283,150 @@ enum processor_type
>>>    PROCESSOR_max
>>>  };
>>>  
>>> +/* Processor target table, indexed by processor number */
>>> +struct ptt
>>> +{
>>> +  const char *const name;			/* processor name  */
>>> +
>>> +  /* Default alignments.  */
>>> +  const char *const align_loop;
>>> +  const char *const align_jump;
>>> +  const char *const align_label;
>>> +  const char *const align_func;
>>> +};
>>> +
>>> +extern const struct ptt processor_target_table[PROCESSOR_max];
>>> +
>>> +#include "wide-int-bitmask.h"
>>> +
>>> +const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>>> +const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>>> +const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>>> +const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>>> +const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>>> +const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>>> +const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>>> +const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>>> +const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>>> +const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>>> +const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>>> +const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>>> +const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>>> +const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>>> +const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>>> +const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>>> +const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>>> +const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>>> +const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>>> +const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>>> +const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>>> +const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>>> +const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>>> +const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>>> +const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>>> +const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>>> +const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>>> +const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>>> +const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>>> +const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>>> +const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>>> +const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>>> +const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>>> +const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>>> +const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>>> +const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>>> +const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>>> +const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>>> +const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>>> +const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>>> +const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>>> +const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>>> +const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>>> +const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>>> +/* Hole after PTA_MPX was removed.  */
>>> +const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>>> +const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>>> +const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>>> +const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>>> +const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>>> +const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>>> +const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>>> +const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>>> +const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>>> +const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>>> +const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>>> +const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>>> +const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>>> +const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>>> +const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>>> +const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>>> +const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>>> +const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>>> +const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>>> +const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>>> +const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>>> +const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>>> +const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>>> +const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>>> +const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>>> +const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>>> +const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>>> +const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>>> +const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>>> +
>>> +const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>>> +  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>>> +const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>>> +  | PTA_POPCNT;
>>> +const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>>> +const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>>> +  | PTA_XSAVEOPT;
>>> +const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>>> +  | PTA_RDRND | PTA_F16C;
>>> +const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>>> +  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>>> +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>>> +  | PTA_RDSEED;
>>> +const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>>> +  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>>> +const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>> +  | PTA_CLWB;
>>> +const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>> +  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>>> +const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>>> +  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>>> +  | PTA_RDPID | PTA_CLWB;
>>> +const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>>> +  | PTA_WBNOINVD;
>>> +const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>>> +  | PTA_AVX512F | PTA_AVX512CD;
>>> +const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>>> +const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>>> +const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>>> +  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>>> +  | PTA_FSGSBASE;
>>> +const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>>> +  | PTA_SGX;
>>> +const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>>> +  | PTA_GFNI;
>>> +const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>>> +  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>>> +
>>> +#include "insn-attr-common.h"
>>> +
>>> +struct pta
>>> +{
>>> +  const char *const name;		/* processor name or nickname.  */
>>> +  const enum processor_type processor;
>>> +  const enum attr_cpu schedule;
>>> +  const wide_int_bitmask flags;
>>> +};
>>> +
>>> +extern const pta processor_alias_table[];
>>> +extern int const pta_size;
>>> +
>>>  extern enum processor_type ix86_tune;
>>>  extern enum processor_type ix86_arch;
>>>  
>>> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
>>> index 0ddcd1aa2ac..c743a7d0dc0 100644
>>> --- a/gcc/doc/tm.texi
>>> +++ b/gcc/doc/tm.texi
>>> @@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
>>>  Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
>>>  @end deftypefn
>>>  
>>> +@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int)
>>> +The hook is used for options that have a non-trivial list of possible option values.
>>> +@end deftypefn
>>> +
>>>  @node Miscellaneous Register Hooks
>>>  @subsection Miscellaneous register hooks
>>>  @cindex miscellaneous register hooks
>>> diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
>>> index e275aca0eec..3fbcbea820b 100644
>>> --- a/gcc/doc/tm.texi.in
>>> +++ b/gcc/doc/tm.texi.in
>>> @@ -3669,6 +3669,8 @@ generic code.
>>>  
>>>  @hook TARGET_SUPPORTS_SPLIT_STACK
>>>  
>>> +@hook TARGET_GET_VALID_OPTION_VALUES
>>> +
>>>  @node Miscellaneous Register Hooks
>>>  @subsection Miscellaneous register hooks
>>>  @cindex miscellaneous register hooks
>>> diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
>>> index 894eea5f37c..6f3f071a171 100644
>>> --- a/gcc/opt-suggestions.c
>>> +++ b/gcc/opt-suggestions.c
>>> @@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
>>>  #include "params.h"
>>>  #include "spellcheck.h"
>>>  #include "opt-suggestions.h"
>>> +#include "common/common-target.h"
>>>  #include "selftest.h"
>>>  
>>>  option_proposer::~option_proposer ()
>>> @@ -135,8 +136,24 @@ option_proposer::build_option_suggestions (void)
>>>  		}
>>>  	    }
>>>  	  else
>>> -	    add_misspelling_candidates (m_option_suggestions, option,
>>> -					opt_text);
>>> +	    {
>>> +	      vec<const char *> option_values
>>> +		= targetm_common.get_valid_option_values (i);
>>> +	      if (!option_values.is_empty ())
>>> +		{
>>> +		  for (unsigned j = 0; j < option_values.length (); j++)
>>> +		    {
>>> +		      char *with_arg = concat (opt_text, option_values[j],
>>> +					       NULL);
>>> +		      add_misspelling_candidates (m_option_suggestions, option,
>>> +						  with_arg);
>>> +		      free (with_arg);
>>> +		    }
>>> +		}
>>> +	      else
>>> +		add_misspelling_candidates (m_option_suggestions, option,
>>> +					    opt_text);
>>> +	    }
>>>  	  break;
>>>  
>>>  	case OPT_fsanitize_:
>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>> index b8ae8756b4f..97cfd8f455c 100644
>>> --- a/gcc/opts.c
>>> +++ b/gcc/opts.c
>>> @@ -1090,6 +1090,21 @@ wrap_help (const char *help,
>>>    while (remaining);
>>>  }
>>>  
>>> +/* Data structure used to print list of valid option values.  */
>>> +
>>> +struct option_help_tuple
>>> +{
>>> +  option_help_tuple (int code, vec<const char *> values):
>>> +    m_code (code), m_values (values)
>>> +  {}
>>> +
>>> +  /* Code of an option.  */
>>> +  int m_code;
>>> +
>>> +  /* List of possible values.  */
>>> +  vec<const char *> m_values;
>>> +};
>>> +
>>>  /* Print help for a specific front-end, etc.  */
>>>  static void
>>>  print_filtered_help (unsigned int include_flags,
>>> @@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
>>>    if (!opts->x_help_enum_printed)
>>>      opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
>>>  
>>> +  auto_vec<option_help_tuple> help_tuples;
>>> +
>>>    for (i = 0; i < cl_options_count; i++)
>>>      {
>>>        const struct cl_option *option = cl_options + i;
>>> @@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
>>>        if (option->var_type == CLVC_ENUM
>>>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>>>  	opts->x_help_enum_printed[option->var_enum] = 1;
>>> +      else
>>> +	{
>>> +	  vec<const char *> option_values
>>> +	    = targetm_common.get_valid_option_values (i);
>>> +	  if (!option_values.is_empty ())
>>> +	    help_tuples.safe_push (option_help_tuple (i, option_values));
>>> +	}
>>>      }
>>>  
>>>    if (! found)
>>> @@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
>>>        printf ("\n\n");
>>>        opts->x_help_enum_printed[i] = 2;
>>>      }
>>> +
>>> +  for (unsigned i = 0; i < help_tuples.length (); i++)
>>> +    {
>>> +      const struct cl_option *option = cl_options + help_tuples[i].m_code;
>>> +      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
>>> +      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
>>> +	printf (" %s", help_tuples[i].m_values[j]);
>>> +      printf ("\n\n");
>>> +    }
>>>  }
>>>  
>>>  /* Display help for a specified type of option.
>>>
>>
> 

Re: [PATCH] Prototype of hook for possible list of option values.

[Martin Liška]

On 07/20/2018 12:25 PM, Richard Earnshaw (lists) wrote:
> On 20/07/18 11:14, Martin Liška wrote:
>> On 07/20/2018 11:48 AM, Richard Earnshaw (lists) wrote:
>>> On 20/07/18 09:04, Martin Liška wrote:
>>>> Hi.
>>>>
>>>> I'm sending patch candidate with suggested target common hook. It allows a target
>>>> to list all possible values for an option. Using the API, I implemented -march and
>>>> -mtune option listing on i386.
>>>>
>>>> Richard you asked about the values. Yes, target should list all possible values,
>>>> mainly because --help=target output needs all of these.
>>>>
>>>> Thoughts?
>>>> Martin
>>>>
>>>
>>> I don't think anyone can reasonably write an implementation of this hook
>>> based on this specification:
>>>
>>> +@deftypefn {Common Target Hook} {vec<const char *>}
>>> TARGET_GET_VALID_OPTION_VALUES (int)
>>> +The hook is used for options that have a non-trivial list of possible
>>> option values.
>>> +@end deftypefn
>>> +
>>>
>>> What's the int parameter for?  What's the lifetime of the result (who
>>> cleans it up)?  If I need to allocation memory strings in the vector,
>>> where do I do that?  Can I assume GC memory in the driver, for example?
>>
>> Sure, can be improved, please take it as prototype.
>>
>>>
>>> Frankly though, I don't really want to enumerate every possible
>>> permutation of the options for the architecture like this, though.  It's
>>> just too brute force and the answer is likely to be hundreds (haven't
>>
>> That's why I recommended you to list in --help=target content of
>> arm_arch enum. You replied that it's not complete list of all possible values.
>> Note that we are talking about content of --help option, it's not a documentation,
>> it should just help users. Similar to bash completion, it should not be 100% perfect.
>>
>>> sat down to count it).  What's more, the extensions might have meaning
>>> in the order in which they appear.  So, for example,
>>>
>>> 	-march=armv8-a+crypto+nosimd
>>>
>>> would be very different from
>>>
>>> 	-march=armv8-a+nosimd+crypto
>>>
>>> since the extensions are applied from left to right (the first collapses
>>> to armv8-a+nosimd, the latter to armv8-a+crypto, but there are more
>>> complex cases as well which I don't want to dig into here).
>>>
>>> It would be a practical impossibility to list all of these.
>>
>> Yes, that's why I recommended to list only base march values. Modifiers can be mentioned
>> aside if desired.
> 
> So it might be feasible to print something like:
> 
>   arch1[+ext1|+ext2]*
>   arch2[+ext1|+ext3|...]*

This is not feasible for --completion= option (bash completion).

Just for sure, are we talking only about aarch64 feature modifiers. Or do you have any other
special suffixes used in -march, -mtune, -mcpu option values?

What about listing all possible modifiers after possible values for -march?

Martin


> 
> etc.  That at least would be a concise summary of the options.  Whether
> or not automated tools could handle that is another matter.



> 
> R.
> 
>>
>> Martin
>>
>>>
>>> R.
>>>
>>>>
>>>> 0001-Prototype-of-hook-for-possible-list-of-option-values.patch
>>>>
>>>>
>>>> From b2b40f7ca1f801a318aec661d0128a5adde7cb68 Mon Sep 17 00:00:00 2001
>>>> From: marxin <mliska@suse.cz>
>>>> Date: Fri, 20 Jul 2018 09:58:16 +0200
>>>> Subject: [PATCH] Prototype of hook for possible list of option values.
>>>>
>>>> ---
>>>>  gcc/common/common-target.def         |   7 +
>>>>  gcc/common/common-targhooks.c        |   7 +
>>>>  gcc/common/common-targhooks.h        |   1 +
>>>>  gcc/common/config/i386/i386-common.c | 264 +++++++++++++++++
>>>>  gcc/config/i386/i386.c               | 413 +++------------------------
>>>>  gcc/config/i386/i386.h               | 144 ++++++++++
>>>>  gcc/doc/tm.texi                      |   4 +
>>>>  gcc/doc/tm.texi.in                   |   2 +
>>>>  gcc/opt-suggestions.c                |  21 +-
>>>>  gcc/opts.c                           |  33 +++
>>>>  10 files changed, 524 insertions(+), 372 deletions(-)
>>>>
>>>> diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
>>>> index e0afbc6af29..8c98598b015 100644
>>>> --- a/gcc/common/common-target.def
>>>> +++ b/gcc/common/common-target.def
>>>> @@ -80,6 +80,13 @@ DEFHOOK
>>>>   bool, (bool report, struct gcc_options *opts),
>>>>   hook_bool_bool_gcc_optionsp_false)
>>>>  
>>>> +DEFHOOK
>>>> +(get_valid_option_values,
>>>> +"The hook is used for options that have a non-trivial list of\
>>>> + possible option values.",
>>>> + vec<const char *>, (int),
>>>> + default_get_valid_option_values)
>>>> +
>>>>  /* Leave the boolean fields at the end.  */
>>>>  
>>>>  /* True if unwinding tables should be generated by default.  */
>>>> diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
>>>> index b1090190664..3662180f2e0 100644
>>>> --- a/gcc/common/common-targhooks.c
>>>> +++ b/gcc/common/common-targhooks.c
>>>> @@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
>>>>  #include "tm.h"
>>>>  #include "common/common-target.h"
>>>>  #include "common/common-targhooks.h"
>>>> +#include "opts.h"
>>>>  
>>>>  /* Determine the exception handling mechanism for the target.  */
>>>>  
>>>> @@ -77,6 +78,12 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
>>>>    return true;
>>>>  }
>>>>  
>>>> +vec<const char *>
>>>> +default_get_valid_option_values (int option)
>>>> +{
>>>> +  return vec<const char *> ();
>>>> +}
>>>> +
>>>>  const struct default_options empty_optimization_table[] =
>>>>    {
>>>>      { OPT_LEVELS_NONE, 0, NULL, 0 }
>>>> diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
>>>> index d290d7f3e21..f8a7436d9dd 100644
>>>> --- a/gcc/common/common-targhooks.h
>>>> +++ b/gcc/common/common-targhooks.h
>>>> @@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
>>>>  					  struct gcc_options *,
>>>>  					  const struct cl_decoded_option *,
>>>>  					  location_t);
>>>> +extern vec<const char *> default_get_valid_option_values (int);
>>>>  
>>>>  extern const struct default_options empty_optimization_table[];
>>>>  
>>>> diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
>>>> index 70b3c3f2fc3..e7253b60c36 100644
>>>> --- a/gcc/common/config/i386/i386-common.c
>>>> +++ b/gcc/common/config/i386/i386-common.c
>>>> @@ -1459,4 +1459,268 @@ i386_except_unwind_info (struct gcc_options *opts)
>>>>  #undef TARGET_SUPPORTS_SPLIT_STACK
>>>>  #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
>>>>  
>>>> +/* This table must be in sync with enum processor_type in i386.h.  */
>>>> +const struct ptt processor_target_table[PROCESSOR_max] =
>>>> +{
>>>> +  /* The "0:0:8" label alignment specified for some processors generates
>>>> +     secondary 8-byte alignment only for those label/jump/loop targets
>>>> +     which have primary alignment.  */
>>>> +
>>>> +  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"i386",           "4",       "4",       NULL,    "4" },
>>>> +  {"i486",           "16",      "16",      "0:0:8", "16"},
>>>> +  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> +  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> +  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
>>>> +  {"pentium4",       NULL,      NULL,      NULL,    NULL},
>>>> +  {"nocona",         NULL,      NULL,      NULL,    NULL},
>>>> +  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> +  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
>>>> +  {"geode",          NULL,      NULL,      NULL,    NULL},
>>>> +  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
>>>> +  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> +  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> +  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
>>>> +  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> +  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> +  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> +  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> +  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> +  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> +  {"znver1",         "16",      "16",      "0:0:8", "16"}
>>>> +};
>>>> +
>>>> +const pta processor_alias_table[] =
>>>> +{
>>>> +  {"i386", PROCESSOR_I386, CPU_NONE, 0},
>>>> +  {"i486", PROCESSOR_I486, CPU_NONE, 0},
>>>> +  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>> +  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>> +  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>>>> +  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>>>> +  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>>>> +  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>> +  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>> +  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>> +  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> +  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> +  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> +  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> +  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>> +  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>> +  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>>>> +  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> +  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> +  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>> +  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>>>> +    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>> +  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>> +  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> +  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>>>> +  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>> +  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>> +  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>>>> +  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> +    PTA_SANDYBRIDGE},
>>>> +  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> +    PTA_SANDYBRIDGE},
>>>> +  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> +    PTA_IVYBRIDGE},
>>>> +  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> +    PTA_IVYBRIDGE},
>>>> +  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>> +  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>> +  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>>>> +  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>>>> +  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>>>> +    PTA_SKYLAKE_AVX512},
>>>> +  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>>>> +  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>>>> +    PTA_ICELAKE_CLIENT},
>>>> +  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>>>> +    PTA_ICELAKE_SERVER},
>>>> +  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>> +  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>> +  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>> +  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>> +  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>>>> +  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>>>> +  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>>>> +  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>>>> +  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>>>> +  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>>>> +  {"geode", PROCESSOR_GEODE, CPU_GEODE,
>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>> +  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>>>> +  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>> +  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>> +  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>> +  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>> +  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>> +  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>> +  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>> +  {"x86-64", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"eden-x2", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> +  {"nano", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_FXSR},
>>>> +  {"nano-1000", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_FXSR},
>>>> +  {"nano-2000", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_FXSR},
>>>> +  {"nano-3000", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> +  {"nano-x2", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> +  {"eden-x4", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> +  {"nano-x4", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> +  {"k8", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"k8-sse3", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"opteron", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"athlon64", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"athlon-fx", PROCESSOR_K8, CPU_K8,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> +  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>> +  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>> +  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>> +      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>> +  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>> +  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
>>>> +      | PTA_XSAVEOPT | PTA_FSGSBASE},
>>>> +  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>>> +      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
>>>> +      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
>>>> +      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>>>> +      | PTA_MOVBE | PTA_MWAITX},
>>>> +  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>>> +      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>>>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>>>> +      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>>>> +      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>>>> +      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>>>> +  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>>>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>>>> +      | PTA_FXSR | PTA_XSAVE},
>>>> +  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>>>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>>>> +      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>>>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>>> +
>>>> +  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>>>> +    PTA_64BIT
>>>> +      | PTA_HLE /* flags are only used for -march switch.  */ },
>>>> +};
>>>> +
>>>> +int const pta_size = ARRAY_SIZE (processor_alias_table);
>>>> +
>>>> +vec<const char *>
>>>> +ix86_get_valid_option_values (int option)
>>>> +{
>>>> +  vec<const char *> v;
>>>> +  v.create (0);
>>>> +  opt_code opt = (opt_code) option;
>>>> +
>>>> +  switch (opt)
>>>> +    {
>>>> +    case OPT_march_:
>>>> +      for (unsigned i = 0; i < pta_size; i++)
>>>> +	v.safe_push (processor_alias_table[i].name);
>>>> +      break;
>>>> +    case OPT_mtune_:
>>>> +      for (unsigned i = 0; i < PROCESSOR_max; i++)
>>>> +	v.safe_push (processor_target_table[i].name);
>>>> +      break;
>>>> +    default:
>>>> +      break;
>>>> +    }
>>>> +
>>>> +  return v;
>>>> +}
>>>> +
>>>> +#undef  TARGET_GET_VALID_OPTION_VALUES
>>>> +#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
>>>> +
>>>>  struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
>>>> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
>>>> index 2b7e9489ed8..b4d0942188f 100644
>>>> --- a/gcc/config/i386/i386.c
>>>> +++ b/gcc/config/i386/i386.c
>>>> @@ -832,63 +832,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
>>>>  static tree ix86_veclibabi_svml (combined_fn, tree, tree);
>>>>  static tree ix86_veclibabi_acml (combined_fn, tree, tree);
>>>>  
>>>> -/* Processor target table, indexed by processor number */
>>>> -struct ptt
>>>> -{
>>>> -  const char *const name;			/* processor name  */
>>>> -  const struct processor_costs *cost;		/* Processor costs */
>>>> -
>>>> -  /* Default alignments.  */
>>>> -  const char *const align_loop;
>>>> -  const char *const align_jump;
>>>> -  const char *const align_label;
>>>> -  const char *const align_func;
>>>> -};
>>>> -
>>>>  /* This table must be in sync with enum processor_type in i386.h.  */ 
>>>> -static const struct ptt processor_target_table[PROCESSOR_max] =
>>>> -{
>>>> -/* The "0:0:8" label alignment specified for some processors generates
>>>> -   secondary 8-byte alignment only for those label/jump/loop targets
>>>> -   which have primary alignment.  */
>>>> -
>>>> -  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
>>>> -  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
>>>> -  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> -  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> -  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
>>>> -  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
>>>> -  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
>>>> -  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
>>>> -  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>> -  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>> -  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>> -  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
>>>> -  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>> -  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>> -  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>> -  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
>>>> -  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
>>>> -  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
>>>> -  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> -  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>> -  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
>>>> -  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> -  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> -  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> -  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> -  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> -  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>> -  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
>>>> +static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
>>>> +{
>>>> +  &generic_cost,
>>>> +  &i386_cost,
>>>> +  &i486_cost,
>>>> +  &pentium_cost,
>>>> +  &lakemont_cost,
>>>> +  &pentiumpro_cost,
>>>> +  &pentium4_cost,
>>>> +  &nocona_cost,
>>>> +  &core_cost,
>>>> +  &core_cost,
>>>> +  &core_cost,
>>>> +  &core_cost,
>>>> +  &atom_cost,
>>>> +  &slm_cost,
>>>> +  &slm_cost,
>>>> +  &slm_cost,
>>>> +  &slm_cost,
>>>> +  &slm_cost,
>>>> +  &slm_cost,
>>>> +  &skylake_cost,
>>>> +  &skylake_cost,
>>>> +  &skylake_cost,
>>>> +  &skylake_cost,
>>>> +  &skylake_cost,
>>>> +  &intel_cost,
>>>> +  &geode_cost,
>>>> +  &k6_cost,
>>>> +  &athlon_cost,
>>>> +  &k8_cost,
>>>> +  &amdfam10_cost,
>>>> +  &bdver1_cost,
>>>> +  &bdver2_cost,
>>>> +  &bdver3_cost,
>>>> +  &bdver4_cost,
>>>> +  &btver1_cost,
>>>> +  &btver2_cost,
>>>> +  &znver1_cost,
>>>>  };
>>>>  \f
>>>>  static unsigned int
>>>> @@ -3392,6 +3375,8 @@ ix86_override_options_after_change (void)
>>>>    ix86_default_align (&global_options);
>>>>  }
>>>>  
>>>> +
>>>> +
>>>>  /* Override various settings based on options.  If MAIN_ARGS_P, the
>>>>     options are from the command line, otherwise they are from
>>>>     attributes.  Return true if there's an error related to march
>>>> @@ -3406,317 +3391,6 @@ ix86_option_override_internal (bool main_args_p,
>>>>    unsigned HOST_WIDE_INT ix86_arch_mask;
>>>>    const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
>>>>  
>>>> -  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>>>> -  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>>>> -  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>>>> -  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>>>> -  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>>>> -  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>>>> -  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>>>> -  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>>>> -  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>>>> -  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>>>> -  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>>>> -  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>>>> -  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>>>> -  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>>>> -  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>>>> -  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>>>> -  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>>>> -  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>>>> -  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>>>> -  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>>>> -  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>>>> -  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>>>> -  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>>>> -  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>>>> -  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>>>> -  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>>>> -  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>>>> -  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>>>> -  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>>>> -  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>>>> -  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>>>> -  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>>>> -  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>>>> -  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>>>> -  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>>>> -  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>>>> -  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>>>> -  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>>>> -  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>>>> -  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>>>> -  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>>>> -  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>>>> -  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>>>> -  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>>>> -  /* Hole after PTA_MPX was removed.  */
>>>> -  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>>>> -  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>>>> -  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>>>> -  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>>>> -  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>>>> -  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>>>> -  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>>>> -  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>>>> -  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>>>> -  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>>>> -  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>>>> -  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>>>> -  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>>>> -  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>>>> -  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>>>> -  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>>>> -  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>>>> -  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>>>> -  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>>>> -  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>>>> -  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>>>> -  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>>>> -  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>>>> -  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>>>> -  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>>>> -  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>>>> -  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>>>> -  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>>>> -  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>>>> -
>>>> -  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>>>> -    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>>>> -  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>>>> -    | PTA_POPCNT;
>>>> -  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>>>> -  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>>>> -    | PTA_XSAVEOPT;
>>>> -  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>>>> -    | PTA_RDRND | PTA_F16C;
>>>> -  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>>>> -    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>>>> -  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>>>> -    | PTA_RDSEED;
>>>> -  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>>>> -    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>>>> -  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>>>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>> -    | PTA_CLWB;
>>>> -  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>>>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>> -    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>>>> -  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>>>> -    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>>>> -    | PTA_RDPID | PTA_CLWB;
>>>> -  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>>>> -    | PTA_WBNOINVD;
>>>> -  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>>>> -    | PTA_AVX512F | PTA_AVX512CD;
>>>> -  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>>>> -  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>>>> -  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>>>> -    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>>>> -    | PTA_FSGSBASE;
>>>> -  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>>>> -    | PTA_SGX;
>>>> -  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>>>> -    | PTA_GFNI;
>>>> -  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>>>> -    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>>>> -
>>>> -  static struct pta
>>>> -    {
>>>> -      const char *const name;		/* processor name or nickname.  */
>>>> -      const enum processor_type processor;
>>>> -      const enum attr_cpu schedule;
>>>> -      const wide_int_bitmask flags;
>>>> -    }
>>>> -  const processor_alias_table[] =
>>>> -    {
>>>> -      {"i386", PROCESSOR_I386, CPU_NONE, 0},
>>>> -      {"i486", PROCESSOR_I486, CPU_NONE, 0},
>>>> -      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>> -      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>> -      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>>>> -      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>>>> -      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>>>> -      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>> -      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>> -      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>> -      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> -      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> -        PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> -      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> -      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> -      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>> -      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>> -      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>>>> -      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> -      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>>> -      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>> -      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>>>> -	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>> -      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>> -      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> -      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>>>> -      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>> -      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>> -      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>>>> -      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> -	PTA_SANDYBRIDGE},
>>>> -      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> -	PTA_SANDYBRIDGE},
>>>> -      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> -	PTA_IVYBRIDGE},
>>>> -      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>> -	PTA_IVYBRIDGE},
>>>> -      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>> -      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>> -      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>>>> -      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>>>> -      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>>>> -        PTA_SKYLAKE_AVX512},
>>>> -      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>>>> -      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>>>> -	PTA_ICELAKE_CLIENT},
>>>> -      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>>>> -	PTA_ICELAKE_SERVER},
>>>> -      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>> -      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>> -      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>> -      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>> -      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>>>> -      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>>>> -      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>>>> -      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>>>> -      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>>>> -      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>>>> -      {"geode", PROCESSOR_GEODE, CPU_GEODE,
>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>> -      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>>>> -      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>> -      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>> -      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>> -      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>> -      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>> -      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>> -      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>> -      {"x86-64", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"eden-x2", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>> -      {"nano", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -        | PTA_SSSE3 | PTA_FXSR},
>>>> -      {"nano-1000", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -        | PTA_SSSE3 | PTA_FXSR},
>>>> -      {"nano-2000", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -        | PTA_SSSE3 | PTA_FXSR},
>>>> -      {"nano-3000", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> -      {"nano-x2", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> -      {"eden-x4", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> -      {"nano-x4", PROCESSOR_K8, CPU_K8,
>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>> -      {"k8", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"k8-sse3", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"opteron", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"athlon64", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"athlon-fx", PROCESSOR_K8, CPU_K8,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>> -      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>> -      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>> -      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>> -	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>> -      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>> -      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
>>>> -	| PTA_XSAVEOPT | PTA_FSGSBASE},
>>>> -      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
>>>> -	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
>>>> -	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
>>>> -	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>>>> -	| PTA_MOVBE | PTA_MWAITX},
>>>> -      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>>> -	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>>>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>>>> -	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>>>> -	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>>>> -	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>>>> -      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>>>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>>>> -	| PTA_FXSR | PTA_XSAVE},
>>>> -      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>>>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>>>> -	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>>>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>>> -
>>>> -      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>>>> -	PTA_64BIT
>>>> -	| PTA_HLE /* flags are only used for -march switch.  */ },
>>>> -    };
>>>> -
>>>>    /* -mrecip options.  */
>>>>    static struct
>>>>      {
>>>> @@ -3733,7 +3407,6 @@ ix86_option_override_internal (bool main_args_p,
>>>>        { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
>>>>      };
>>>>  
>>>> -  int const pta_size = ARRAY_SIZE (processor_alias_table);
>>>>  
>>>>    /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
>>>>       TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
>>>> @@ -4389,7 +4062,7 @@ ix86_option_override_internal (bool main_args_p,
>>>>  	}
>>>>      }
>>>>  
>>>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>>>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>>>    if (opts->x_optimize_size)
>>>> @@ -5186,7 +4859,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
>>>>    opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
>>>>    opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
>>>>    opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
>>>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>>>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>>>    if (opts->x_optimize_size)
>>>> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
>>>> index fbba598ffd5..cc7fc1fd443 100644
>>>> --- a/gcc/config/i386/i386.h
>>>> +++ b/gcc/config/i386/i386.h
>>>> @@ -2283,6 +2283,150 @@ enum processor_type
>>>>    PROCESSOR_max
>>>>  };
>>>>  
>>>> +/* Processor target table, indexed by processor number */
>>>> +struct ptt
>>>> +{
>>>> +  const char *const name;			/* processor name  */
>>>> +
>>>> +  /* Default alignments.  */
>>>> +  const char *const align_loop;
>>>> +  const char *const align_jump;
>>>> +  const char *const align_label;
>>>> +  const char *const align_func;
>>>> +};
>>>> +
>>>> +extern const struct ptt processor_target_table[PROCESSOR_max];
>>>> +
>>>> +#include "wide-int-bitmask.h"
>>>> +
>>>> +const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>>>> +const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>>>> +const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>>>> +const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>>>> +const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>>>> +const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>>>> +const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>>>> +const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>>>> +const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>>>> +const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>>>> +const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>>>> +const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>>>> +const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>>>> +const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>>>> +const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>>>> +const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>>>> +const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>>>> +const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>>>> +const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>>>> +const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>>>> +const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>>>> +const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>>>> +const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>>>> +const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>>>> +const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>>>> +const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>>>> +const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>>>> +const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>>>> +const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>>>> +const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>>>> +const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>>>> +const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>>>> +const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>>>> +const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>>>> +const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>>>> +const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>>>> +const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>>>> +const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>>>> +const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>>>> +const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>>>> +const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>>>> +const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>>>> +const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>>>> +const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>>>> +/* Hole after PTA_MPX was removed.  */
>>>> +const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>>>> +const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>>>> +const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>>>> +const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>>>> +const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>>>> +const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>>>> +const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>>>> +const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>>>> +const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>>>> +const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>>>> +const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>>>> +const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>>>> +const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>>>> +const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>>>> +const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>>>> +const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>>>> +const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>>>> +const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>>>> +const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>>>> +const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>>>> +const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>>>> +const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>>>> +const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>>>> +const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>>>> +const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>>>> +const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>>>> +const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>>>> +const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>>>> +const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>>>> +
>>>> +const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>>>> +  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>>>> +const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>>>> +  | PTA_POPCNT;
>>>> +const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>>>> +const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>>>> +  | PTA_XSAVEOPT;
>>>> +const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>>>> +  | PTA_RDRND | PTA_F16C;
>>>> +const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>>>> +  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>>>> +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>>>> +  | PTA_RDSEED;
>>>> +const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>>>> +  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>>>> +const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>>>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>> +  | PTA_CLWB;
>>>> +const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>>>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>> +  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>>>> +const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>>>> +  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>>>> +  | PTA_RDPID | PTA_CLWB;
>>>> +const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>>>> +  | PTA_WBNOINVD;
>>>> +const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>>>> +  | PTA_AVX512F | PTA_AVX512CD;
>>>> +const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>>>> +const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>>>> +const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>>>> +  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>>>> +  | PTA_FSGSBASE;
>>>> +const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>>>> +  | PTA_SGX;
>>>> +const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>>>> +  | PTA_GFNI;
>>>> +const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>>>> +  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>>>> +
>>>> +#include "insn-attr-common.h"
>>>> +
>>>> +struct pta
>>>> +{
>>>> +  const char *const name;		/* processor name or nickname.  */
>>>> +  const enum processor_type processor;
>>>> +  const enum attr_cpu schedule;
>>>> +  const wide_int_bitmask flags;
>>>> +};
>>>> +
>>>> +extern const pta processor_alias_table[];
>>>> +extern int const pta_size;
>>>> +
>>>>  extern enum processor_type ix86_tune;
>>>>  extern enum processor_type ix86_arch;
>>>>  
>>>> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
>>>> index 0ddcd1aa2ac..c743a7d0dc0 100644
>>>> --- a/gcc/doc/tm.texi
>>>> +++ b/gcc/doc/tm.texi
>>>> @@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
>>>>  Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
>>>>  @end deftypefn
>>>>  
>>>> +@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int)
>>>> +The hook is used for options that have a non-trivial list of possible option values.
>>>> +@end deftypefn
>>>> +
>>>>  @node Miscellaneous Register Hooks
>>>>  @subsection Miscellaneous register hooks
>>>>  @cindex miscellaneous register hooks
>>>> diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
>>>> index e275aca0eec..3fbcbea820b 100644
>>>> --- a/gcc/doc/tm.texi.in
>>>> +++ b/gcc/doc/tm.texi.in
>>>> @@ -3669,6 +3669,8 @@ generic code.
>>>>  
>>>>  @hook TARGET_SUPPORTS_SPLIT_STACK
>>>>  
>>>> +@hook TARGET_GET_VALID_OPTION_VALUES
>>>> +
>>>>  @node Miscellaneous Register Hooks
>>>>  @subsection Miscellaneous register hooks
>>>>  @cindex miscellaneous register hooks
>>>> diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
>>>> index 894eea5f37c..6f3f071a171 100644
>>>> --- a/gcc/opt-suggestions.c
>>>> +++ b/gcc/opt-suggestions.c
>>>> @@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
>>>>  #include "params.h"
>>>>  #include "spellcheck.h"
>>>>  #include "opt-suggestions.h"
>>>> +#include "common/common-target.h"
>>>>  #include "selftest.h"
>>>>  
>>>>  option_proposer::~option_proposer ()
>>>> @@ -135,8 +136,24 @@ option_proposer::build_option_suggestions (void)
>>>>  		}
>>>>  	    }
>>>>  	  else
>>>> -	    add_misspelling_candidates (m_option_suggestions, option,
>>>> -					opt_text);
>>>> +	    {
>>>> +	      vec<const char *> option_values
>>>> +		= targetm_common.get_valid_option_values (i);
>>>> +	      if (!option_values.is_empty ())
>>>> +		{
>>>> +		  for (unsigned j = 0; j < option_values.length (); j++)
>>>> +		    {
>>>> +		      char *with_arg = concat (opt_text, option_values[j],
>>>> +					       NULL);
>>>> +		      add_misspelling_candidates (m_option_suggestions, option,
>>>> +						  with_arg);
>>>> +		      free (with_arg);
>>>> +		    }
>>>> +		}
>>>> +	      else
>>>> +		add_misspelling_candidates (m_option_suggestions, option,
>>>> +					    opt_text);
>>>> +	    }
>>>>  	  break;
>>>>  
>>>>  	case OPT_fsanitize_:
>>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>>> index b8ae8756b4f..97cfd8f455c 100644
>>>> --- a/gcc/opts.c
>>>> +++ b/gcc/opts.c
>>>> @@ -1090,6 +1090,21 @@ wrap_help (const char *help,
>>>>    while (remaining);
>>>>  }
>>>>  
>>>> +/* Data structure used to print list of valid option values.  */
>>>> +
>>>> +struct option_help_tuple
>>>> +{
>>>> +  option_help_tuple (int code, vec<const char *> values):
>>>> +    m_code (code), m_values (values)
>>>> +  {}
>>>> +
>>>> +  /* Code of an option.  */
>>>> +  int m_code;
>>>> +
>>>> +  /* List of possible values.  */
>>>> +  vec<const char *> m_values;
>>>> +};
>>>> +
>>>>  /* Print help for a specific front-end, etc.  */
>>>>  static void
>>>>  print_filtered_help (unsigned int include_flags,
>>>> @@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
>>>>    if (!opts->x_help_enum_printed)
>>>>      opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
>>>>  
>>>> +  auto_vec<option_help_tuple> help_tuples;
>>>> +
>>>>    for (i = 0; i < cl_options_count; i++)
>>>>      {
>>>>        const struct cl_option *option = cl_options + i;
>>>> @@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
>>>>        if (option->var_type == CLVC_ENUM
>>>>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>>>>  	opts->x_help_enum_printed[option->var_enum] = 1;
>>>> +      else
>>>> +	{
>>>> +	  vec<const char *> option_values
>>>> +	    = targetm_common.get_valid_option_values (i);
>>>> +	  if (!option_values.is_empty ())
>>>> +	    help_tuples.safe_push (option_help_tuple (i, option_values));
>>>> +	}
>>>>      }
>>>>  
>>>>    if (! found)
>>>> @@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
>>>>        printf ("\n\n");
>>>>        opts->x_help_enum_printed[i] = 2;
>>>>      }
>>>> +
>>>> +  for (unsigned i = 0; i < help_tuples.length (); i++)
>>>> +    {
>>>> +      const struct cl_option *option = cl_options + help_tuples[i].m_code;
>>>> +      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
>>>> +      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
>>>> +	printf (" %s", help_tuples[i].m_values[j]);
>>>> +      printf ("\n\n");
>>>> +    }
>>>>  }
>>>>  
>>>>  /* Display help for a specified type of option.
>>>>
>>>
>>
> 

Re: [PATCH] Prototype of hook for possible list of option values.

[Richard Earnshaw (lists)]

On 20/07/18 11:54, Martin Liška wrote:
> On 07/20/2018 12:25 PM, Richard Earnshaw (lists) wrote:
>> On 20/07/18 11:14, Martin Liška wrote:
>>> On 07/20/2018 11:48 AM, Richard Earnshaw (lists) wrote:
>>>> On 20/07/18 09:04, Martin Liška wrote:
>>>>> Hi.
>>>>>
>>>>> I'm sending patch candidate with suggested target common hook. It allows a target
>>>>> to list all possible values for an option. Using the API, I implemented -march and
>>>>> -mtune option listing on i386.
>>>>>
>>>>> Richard you asked about the values. Yes, target should list all possible values,
>>>>> mainly because --help=target output needs all of these.
>>>>>
>>>>> Thoughts?
>>>>> Martin
>>>>>
>>>>
>>>> I don't think anyone can reasonably write an implementation of this hook
>>>> based on this specification:
>>>>
>>>> +@deftypefn {Common Target Hook} {vec<const char *>}
>>>> TARGET_GET_VALID_OPTION_VALUES (int)
>>>> +The hook is used for options that have a non-trivial list of possible
>>>> option values.
>>>> +@end deftypefn
>>>> +
>>>>
>>>> What's the int parameter for?  What's the lifetime of the result (who
>>>> cleans it up)?  If I need to allocation memory strings in the vector,
>>>> where do I do that?  Can I assume GC memory in the driver, for example?
>>>
>>> Sure, can be improved, please take it as prototype.
>>>
>>>>
>>>> Frankly though, I don't really want to enumerate every possible
>>>> permutation of the options for the architecture like this, though.  It's
>>>> just too brute force and the answer is likely to be hundreds (haven't
>>>
>>> That's why I recommended you to list in --help=target content of
>>> arm_arch enum. You replied that it's not complete list of all possible values.
>>> Note that we are talking about content of --help option, it's not a documentation,
>>> it should just help users. Similar to bash completion, it should not be 100% perfect.
>>>
>>>> sat down to count it).  What's more, the extensions might have meaning
>>>> in the order in which they appear.  So, for example,
>>>>
>>>> 	-march=armv8-a+crypto+nosimd
>>>>
>>>> would be very different from
>>>>
>>>> 	-march=armv8-a+nosimd+crypto
>>>>
>>>> since the extensions are applied from left to right (the first collapses
>>>> to armv8-a+nosimd, the latter to armv8-a+crypto, but there are more
>>>> complex cases as well which I don't want to dig into here).
>>>>
>>>> It would be a practical impossibility to list all of these.
>>>
>>> Yes, that's why I recommended to list only base march values. Modifiers can be mentioned
>>> aside if desired.
>>
>> So it might be feasible to print something like:
>>
>>   arch1[+ext1|+ext2]*
>>   arch2[+ext1|+ext3|...]*
> 
> This is not feasible for --completion= option (bash completion).
> 
> Just for sure, are we talking only about aarch64 feature modifiers. Or do you have any other
> special suffixes used in -march, -mtune, -mcpu option values?
> 
> What about listing all possible modifiers after possible values for -march?
> 

Modifiers are context dependent.  The architecture implies which
modifiers can be applied (and what they mean in detail, so, for example,
+fp means enable the default floating point variant for this
architecture).  Not all modifiers apply to all architectures - +fp is
not permitted on ARMv4t, for example.

R.

> Martin
> 
> 
>>
>> etc.  That at least would be a concise summary of the options.  Whether
>> or not automated tools could handle that is another matter.
> 
> 
> 
>>
>> R.
>>
>>>
>>> Martin
>>>
>>>>
>>>> R.
>>>>
>>>>>
>>>>> 0001-Prototype-of-hook-for-possible-list-of-option-values.patch
>>>>>
>>>>>
>>>>> From b2b40f7ca1f801a318aec661d0128a5adde7cb68 Mon Sep 17 00:00:00 2001
>>>>> From: marxin <mliska@suse.cz>
>>>>> Date: Fri, 20 Jul 2018 09:58:16 +0200
>>>>> Subject: [PATCH] Prototype of hook for possible list of option values.
>>>>>
>>>>> ---
>>>>>  gcc/common/common-target.def         |   7 +
>>>>>  gcc/common/common-targhooks.c        |   7 +
>>>>>  gcc/common/common-targhooks.h        |   1 +
>>>>>  gcc/common/config/i386/i386-common.c | 264 +++++++++++++++++
>>>>>  gcc/config/i386/i386.c               | 413 +++------------------------
>>>>>  gcc/config/i386/i386.h               | 144 ++++++++++
>>>>>  gcc/doc/tm.texi                      |   4 +
>>>>>  gcc/doc/tm.texi.in                   |   2 +
>>>>>  gcc/opt-suggestions.c                |  21 +-
>>>>>  gcc/opts.c                           |  33 +++
>>>>>  10 files changed, 524 insertions(+), 372 deletions(-)
>>>>>
>>>>> diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
>>>>> index e0afbc6af29..8c98598b015 100644
>>>>> --- a/gcc/common/common-target.def
>>>>> +++ b/gcc/common/common-target.def
>>>>> @@ -80,6 +80,13 @@ DEFHOOK
>>>>>   bool, (bool report, struct gcc_options *opts),
>>>>>   hook_bool_bool_gcc_optionsp_false)
>>>>>  
>>>>> +DEFHOOK
>>>>> +(get_valid_option_values,
>>>>> +"The hook is used for options that have a non-trivial list of\
>>>>> + possible option values.",
>>>>> + vec<const char *>, (int),
>>>>> + default_get_valid_option_values)
>>>>> +
>>>>>  /* Leave the boolean fields at the end.  */
>>>>>  
>>>>>  /* True if unwinding tables should be generated by default.  */
>>>>> diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
>>>>> index b1090190664..3662180f2e0 100644
>>>>> --- a/gcc/common/common-targhooks.c
>>>>> +++ b/gcc/common/common-targhooks.c
>>>>> @@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
>>>>>  #include "tm.h"
>>>>>  #include "common/common-target.h"
>>>>>  #include "common/common-targhooks.h"
>>>>> +#include "opts.h"
>>>>>  
>>>>>  /* Determine the exception handling mechanism for the target.  */
>>>>>  
>>>>> @@ -77,6 +78,12 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
>>>>>    return true;
>>>>>  }
>>>>>  
>>>>> +vec<const char *>
>>>>> +default_get_valid_option_values (int option)
>>>>> +{
>>>>> +  return vec<const char *> ();
>>>>> +}
>>>>> +
>>>>>  const struct default_options empty_optimization_table[] =
>>>>>    {
>>>>>      { OPT_LEVELS_NONE, 0, NULL, 0 }
>>>>> diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
>>>>> index d290d7f3e21..f8a7436d9dd 100644
>>>>> --- a/gcc/common/common-targhooks.h
>>>>> +++ b/gcc/common/common-targhooks.h
>>>>> @@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
>>>>>  					  struct gcc_options *,
>>>>>  					  const struct cl_decoded_option *,
>>>>>  					  location_t);
>>>>> +extern vec<const char *> default_get_valid_option_values (int);
>>>>>  
>>>>>  extern const struct default_options empty_optimization_table[];
>>>>>  
>>>>> diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
>>>>> index 70b3c3f2fc3..e7253b60c36 100644
>>>>> --- a/gcc/common/config/i386/i386-common.c
>>>>> +++ b/gcc/common/config/i386/i386-common.c
>>>>> @@ -1459,4 +1459,268 @@ i386_except_unwind_info (struct gcc_options *opts)
>>>>>  #undef TARGET_SUPPORTS_SPLIT_STACK
>>>>>  #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
>>>>>  
>>>>> +/* This table must be in sync with enum processor_type in i386.h.  */
>>>>> +const struct ptt processor_target_table[PROCESSOR_max] =
>>>>> +{
>>>>> +  /* The "0:0:8" label alignment specified for some processors generates
>>>>> +     secondary 8-byte alignment only for those label/jump/loop targets
>>>>> +     which have primary alignment.  */
>>>>> +
>>>>> +  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"i386",           "4",       "4",       NULL,    "4" },
>>>>> +  {"i486",           "16",      "16",      "0:0:8", "16"},
>>>>> +  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> +  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> +  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
>>>>> +  {"pentium4",       NULL,      NULL,      NULL,    NULL},
>>>>> +  {"nocona",         NULL,      NULL,      NULL,    NULL},
>>>>> +  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> +  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
>>>>> +  {"geode",          NULL,      NULL,      NULL,    NULL},
>>>>> +  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
>>>>> +  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> +  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> +  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
>>>>> +  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> +  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> +  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> +  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> +  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> +  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> +  {"znver1",         "16",      "16",      "0:0:8", "16"}
>>>>> +};
>>>>> +
>>>>> +const pta processor_alias_table[] =
>>>>> +{
>>>>> +  {"i386", PROCESSOR_I386, CPU_NONE, 0},
>>>>> +  {"i486", PROCESSOR_I486, CPU_NONE, 0},
>>>>> +  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>>> +  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>>> +  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>>>>> +  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>>>>> +  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>>>>> +  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>>> +  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>>> +  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>>> +  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> +  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> +  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> +  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> +  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>>> +  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>>> +  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>>>>> +  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> +  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> +    PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> +  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>>> +  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>>>>> +    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>>> +  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>>> +  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>>>>> +    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> +  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>>>>> +  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>>> +  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>>> +  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>>>>> +  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> +    PTA_SANDYBRIDGE},
>>>>> +  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> +    PTA_SANDYBRIDGE},
>>>>> +  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> +    PTA_IVYBRIDGE},
>>>>> +  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> +    PTA_IVYBRIDGE},
>>>>> +  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>>> +  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>>> +  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>>>>> +  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>>>>> +  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>>>>> +    PTA_SKYLAKE_AVX512},
>>>>> +  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>>>>> +  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>>>>> +    PTA_ICELAKE_CLIENT},
>>>>> +  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>>>>> +    PTA_ICELAKE_SERVER},
>>>>> +  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>>> +  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>>> +  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>>> +  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>>> +  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>>>>> +  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>>>>> +  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>>>>> +  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>>>>> +  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>>>>> +  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>>>>> +  {"geode", PROCESSOR_GEODE, CPU_GEODE,
>>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>>> +  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>>>>> +  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>>> +  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>>> +  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>>> +  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>>> +  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>>> +  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>>> +  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> +    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>>> +  {"x86-64", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"eden-x2", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> +  {"nano", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_FXSR},
>>>>> +  {"nano-1000", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_FXSR},
>>>>> +  {"nano-2000", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_FXSR},
>>>>> +  {"nano-3000", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> +  {"nano-x2", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> +  {"eden-x4", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> +  {"nano-x4", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> +  {"k8", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"k8-sse3", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"opteron", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"athlon64", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> +      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"athlon-fx", PROCESSOR_K8, CPU_K8,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> +      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> +  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>>> +  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>>> +      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>>> +  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>>> +      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>>> +  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>>> +  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>>> +      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>>> +      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
>>>>> +      | PTA_XSAVEOPT | PTA_FSGSBASE},
>>>>> +  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>>>> +      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
>>>>> +      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
>>>>> +      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>>>>> +      | PTA_MOVBE | PTA_MWAITX},
>>>>> +  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>>>>> +    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>>>> +      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>>>>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>>>>> +      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>>>>> +      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>>>>> +      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>>>>> +  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>>>>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>>>>> +      | PTA_FXSR | PTA_XSAVE},
>>>>> +  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>>>>> +    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>>> +      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>>>>> +      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>>>>> +      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>>>>> +      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>>>> +
>>>>> +  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>>>>> +    PTA_64BIT
>>>>> +      | PTA_HLE /* flags are only used for -march switch.  */ },
>>>>> +};
>>>>> +
>>>>> +int const pta_size = ARRAY_SIZE (processor_alias_table);
>>>>> +
>>>>> +vec<const char *>
>>>>> +ix86_get_valid_option_values (int option)
>>>>> +{
>>>>> +  vec<const char *> v;
>>>>> +  v.create (0);
>>>>> +  opt_code opt = (opt_code) option;
>>>>> +
>>>>> +  switch (opt)
>>>>> +    {
>>>>> +    case OPT_march_:
>>>>> +      for (unsigned i = 0; i < pta_size; i++)
>>>>> +	v.safe_push (processor_alias_table[i].name);
>>>>> +      break;
>>>>> +    case OPT_mtune_:
>>>>> +      for (unsigned i = 0; i < PROCESSOR_max; i++)
>>>>> +	v.safe_push (processor_target_table[i].name);
>>>>> +      break;
>>>>> +    default:
>>>>> +      break;
>>>>> +    }
>>>>> +
>>>>> +  return v;
>>>>> +}
>>>>> +
>>>>> +#undef  TARGET_GET_VALID_OPTION_VALUES
>>>>> +#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
>>>>> +
>>>>>  struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
>>>>> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
>>>>> index 2b7e9489ed8..b4d0942188f 100644
>>>>> --- a/gcc/config/i386/i386.c
>>>>> +++ b/gcc/config/i386/i386.c
>>>>> @@ -832,63 +832,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
>>>>>  static tree ix86_veclibabi_svml (combined_fn, tree, tree);
>>>>>  static tree ix86_veclibabi_acml (combined_fn, tree, tree);
>>>>>  
>>>>> -/* Processor target table, indexed by processor number */
>>>>> -struct ptt
>>>>> -{
>>>>> -  const char *const name;			/* processor name  */
>>>>> -  const struct processor_costs *cost;		/* Processor costs */
>>>>> -
>>>>> -  /* Default alignments.  */
>>>>> -  const char *const align_loop;
>>>>> -  const char *const align_jump;
>>>>> -  const char *const align_label;
>>>>> -  const char *const align_func;
>>>>> -};
>>>>> -
>>>>>  /* This table must be in sync with enum processor_type in i386.h.  */ 
>>>>> -static const struct ptt processor_target_table[PROCESSOR_max] =
>>>>> -{
>>>>> -/* The "0:0:8" label alignment specified for some processors generates
>>>>> -   secondary 8-byte alignment only for those label/jump/loop targets
>>>>> -   which have primary alignment.  */
>>>>> -
>>>>> -  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
>>>>> -  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
>>>>> -  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> -  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> -  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
>>>>> -  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
>>>>> -  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
>>>>> -  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
>>>>> -  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>>> -  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>>> -  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>>> -  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
>>>>> -  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>>> -  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
>>>>> -  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
>>>>> -  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
>>>>> -  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
>>>>> -  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
>>>>> -  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> -  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
>>>>> -  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
>>>>> -  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> -  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> -  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> -  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> -  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> -  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
>>>>> -  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
>>>>> +static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
>>>>> +{
>>>>> +  &generic_cost,
>>>>> +  &i386_cost,
>>>>> +  &i486_cost,
>>>>> +  &pentium_cost,
>>>>> +  &lakemont_cost,
>>>>> +  &pentiumpro_cost,
>>>>> +  &pentium4_cost,
>>>>> +  &nocona_cost,
>>>>> +  &core_cost,
>>>>> +  &core_cost,
>>>>> +  &core_cost,
>>>>> +  &core_cost,
>>>>> +  &atom_cost,
>>>>> +  &slm_cost,
>>>>> +  &slm_cost,
>>>>> +  &slm_cost,
>>>>> +  &slm_cost,
>>>>> +  &slm_cost,
>>>>> +  &slm_cost,
>>>>> +  &skylake_cost,
>>>>> +  &skylake_cost,
>>>>> +  &skylake_cost,
>>>>> +  &skylake_cost,
>>>>> +  &skylake_cost,
>>>>> +  &intel_cost,
>>>>> +  &geode_cost,
>>>>> +  &k6_cost,
>>>>> +  &athlon_cost,
>>>>> +  &k8_cost,
>>>>> +  &amdfam10_cost,
>>>>> +  &bdver1_cost,
>>>>> +  &bdver2_cost,
>>>>> +  &bdver3_cost,
>>>>> +  &bdver4_cost,
>>>>> +  &btver1_cost,
>>>>> +  &btver2_cost,
>>>>> +  &znver1_cost,
>>>>>  };
>>>>>  \f
>>>>>  static unsigned int
>>>>> @@ -3392,6 +3375,8 @@ ix86_override_options_after_change (void)
>>>>>    ix86_default_align (&global_options);
>>>>>  }
>>>>>  
>>>>> +
>>>>> +
>>>>>  /* Override various settings based on options.  If MAIN_ARGS_P, the
>>>>>     options are from the command line, otherwise they are from
>>>>>     attributes.  Return true if there's an error related to march
>>>>> @@ -3406,317 +3391,6 @@ ix86_option_override_internal (bool main_args_p,
>>>>>    unsigned HOST_WIDE_INT ix86_arch_mask;
>>>>>    const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
>>>>>  
>>>>> -  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>>>>> -  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>>>>> -  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>>>>> -  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>>>>> -  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>>>>> -  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>>>>> -  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>>>>> -  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>>>>> -  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>>>>> -  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>>>>> -  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>>>>> -  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>>>>> -  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>>>>> -  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>>>>> -  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>>>>> -  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>>>>> -  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>>>>> -  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>>>>> -  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>>>>> -  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>>>>> -  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>>>>> -  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>>>>> -  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>>>>> -  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>>>>> -  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>>>>> -  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>>>>> -  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>>>>> -  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>>>>> -  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>>>>> -  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>>>>> -  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>>>>> -  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>>>>> -  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>>>>> -  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>>>>> -  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>>>>> -  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>>>>> -  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>>>>> -  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>>>>> -  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>>>>> -  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>>>>> -  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>>>>> -  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>>>>> -  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>>>>> -  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>>>>> -  /* Hole after PTA_MPX was removed.  */
>>>>> -  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>>>>> -  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>>>>> -  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>>>>> -  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>>>>> -  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>>>>> -  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>>>>> -  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>>>>> -  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>>>>> -  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>>>>> -  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>>>>> -  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>>>>> -  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>>>>> -  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>>>>> -  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>>>>> -  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>>>>> -  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>>>>> -  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>>>>> -  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>>>>> -  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>>>>> -  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>>>>> -  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>>>>> -  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>>>>> -  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>>>>> -  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>>>>> -  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>>>>> -  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>>>>> -  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>>>>> -  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>>>>> -  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>>>>> -
>>>>> -  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>>>>> -    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>>>>> -  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>>>>> -    | PTA_POPCNT;
>>>>> -  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>>>>> -  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>>>>> -    | PTA_XSAVEOPT;
>>>>> -  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>>>>> -    | PTA_RDRND | PTA_F16C;
>>>>> -  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>>>>> -    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>>>>> -  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>>>>> -    | PTA_RDSEED;
>>>>> -  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>>>>> -    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>>>>> -  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>>>>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>>> -    | PTA_CLWB;
>>>>> -  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>>>>> -    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>>> -    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>>>>> -  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>>>>> -    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>>>>> -    | PTA_RDPID | PTA_CLWB;
>>>>> -  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>>>>> -    | PTA_WBNOINVD;
>>>>> -  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>>>>> -    | PTA_AVX512F | PTA_AVX512CD;
>>>>> -  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>>>>> -  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>>>>> -  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>>>>> -    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>>>>> -    | PTA_FSGSBASE;
>>>>> -  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>>>>> -    | PTA_SGX;
>>>>> -  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>>>>> -    | PTA_GFNI;
>>>>> -  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>>>>> -    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>>>>> -
>>>>> -  static struct pta
>>>>> -    {
>>>>> -      const char *const name;		/* processor name or nickname.  */
>>>>> -      const enum processor_type processor;
>>>>> -      const enum attr_cpu schedule;
>>>>> -      const wide_int_bitmask flags;
>>>>> -    }
>>>>> -  const processor_alias_table[] =
>>>>> -    {
>>>>> -      {"i386", PROCESSOR_I386, CPU_NONE, 0},
>>>>> -      {"i486", PROCESSOR_I486, CPU_NONE, 0},
>>>>> -      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>>> -      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
>>>>> -      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
>>>>> -      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
>>>>> -      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
>>>>> -      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>>> -      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>>> -      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
>>>>> -      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> -      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> -        PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> -      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> -      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> -        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> -      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>>> -      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
>>>>> -      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
>>>>> -      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> -      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> -	PTA_MMX | PTA_SSE | PTA_FXSR},
>>>>> -      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
>>>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>>> -      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
>>>>> -	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>>> -      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
>>>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
>>>>> -      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
>>>>> -	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> -      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
>>>>> -      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>>> -      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
>>>>> -      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
>>>>> -      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> -	PTA_SANDYBRIDGE},
>>>>> -      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> -	PTA_SANDYBRIDGE},
>>>>> -      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> -	PTA_IVYBRIDGE},
>>>>> -      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
>>>>> -	PTA_IVYBRIDGE},
>>>>> -      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>>> -      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
>>>>> -      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
>>>>> -      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
>>>>> -      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
>>>>> -        PTA_SKYLAKE_AVX512},
>>>>> -      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
>>>>> -      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
>>>>> -	PTA_ICELAKE_CLIENT},
>>>>> -      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
>>>>> -	PTA_ICELAKE_SERVER},
>>>>> -      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>>> -      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
>>>>> -      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>>> -      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
>>>>> -      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
>>>>> -      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
>>>>> -      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
>>>>> -      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
>>>>> -      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
>>>>> -      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
>>>>> -      {"geode", PROCESSOR_GEODE, CPU_GEODE,
>>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>>> -      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
>>>>> -      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>>> -      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
>>>>> -      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>>> -      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
>>>>> -      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>>> -      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>>> -      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
>>>>> -	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
>>>>> -      {"x86-64", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"eden-x2", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
>>>>> -      {"nano", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -        | PTA_SSSE3 | PTA_FXSR},
>>>>> -      {"nano-1000", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -        | PTA_SSSE3 | PTA_FXSR},
>>>>> -      {"nano-2000", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -        | PTA_SSSE3 | PTA_FXSR},
>>>>> -      {"nano-3000", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> -      {"nano-x2", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> -      {"eden-x4", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> -      {"nano-x4", PROCESSOR_K8, CPU_K8,
>>>>> -        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
>>>>> -      {"k8", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"k8-sse3", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"opteron", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"athlon64", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> -	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"athlon-fx", PROCESSOR_K8, CPU_K8,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
>>>>> -	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
>>>>> -      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>>> -      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
>>>>> -	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
>>>>> -      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>>> -	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>>> -      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
>>>>> -      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
>>>>> -	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
>>>>> -	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
>>>>> -	| PTA_XSAVEOPT | PTA_FSGSBASE},
>>>>> -      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
>>>>> -	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
>>>>> -	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
>>>>> -	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
>>>>> -	| PTA_MOVBE | PTA_MWAITX},
>>>>> -      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
>>>>> -	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
>>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
>>>>> -	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
>>>>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
>>>>> -	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
>>>>> -	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
>>>>> -	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
>>>>> -      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
>>>>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
>>>>> -	| PTA_FXSR | PTA_XSAVE},
>>>>> -      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
>>>>> -	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
>>>>> -	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
>>>>> -	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
>>>>> -	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
>>>>> -	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>>>> -
>>>>> -      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
>>>>> -	PTA_64BIT
>>>>> -	| PTA_HLE /* flags are only used for -march switch.  */ },
>>>>> -    };
>>>>> -
>>>>>    /* -mrecip options.  */
>>>>>    static struct
>>>>>      {
>>>>> @@ -3733,7 +3407,6 @@ ix86_option_override_internal (bool main_args_p,
>>>>>        { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
>>>>>      };
>>>>>  
>>>>> -  int const pta_size = ARRAY_SIZE (processor_alias_table);
>>>>>  
>>>>>    /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
>>>>>       TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
>>>>> @@ -4389,7 +4062,7 @@ ix86_option_override_internal (bool main_args_p,
>>>>>  	}
>>>>>      }
>>>>>  
>>>>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>>>>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>>>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>>>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>>>>    if (opts->x_optimize_size)
>>>>> @@ -5186,7 +4859,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
>>>>>    opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
>>>>>    opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
>>>>>    opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
>>>>> -  ix86_tune_cost = processor_target_table[ix86_tune].cost;
>>>>> +  ix86_tune_cost = processor_cost_table[ix86_tune];
>>>>>    /* TODO: ix86_cost should be chosen at instruction or function granuality
>>>>>       so for cold code we use size_cost even in !optimize_size compilation.  */
>>>>>    if (opts->x_optimize_size)
>>>>> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
>>>>> index fbba598ffd5..cc7fc1fd443 100644
>>>>> --- a/gcc/config/i386/i386.h
>>>>> +++ b/gcc/config/i386/i386.h
>>>>> @@ -2283,6 +2283,150 @@ enum processor_type
>>>>>    PROCESSOR_max
>>>>>  };
>>>>>  
>>>>> +/* Processor target table, indexed by processor number */
>>>>> +struct ptt
>>>>> +{
>>>>> +  const char *const name;			/* processor name  */
>>>>> +
>>>>> +  /* Default alignments.  */
>>>>> +  const char *const align_loop;
>>>>> +  const char *const align_jump;
>>>>> +  const char *const align_label;
>>>>> +  const char *const align_func;
>>>>> +};
>>>>> +
>>>>> +extern const struct ptt processor_target_table[PROCESSOR_max];
>>>>> +
>>>>> +#include "wide-int-bitmask.h"
>>>>> +
>>>>> +const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>>>>> +const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
>>>>> +const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
>>>>> +const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
>>>>> +const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
>>>>> +const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
>>>>> +const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
>>>>> +const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
>>>>> +const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
>>>>> +const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
>>>>> +const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
>>>>> +const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
>>>>> +const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
>>>>> +const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
>>>>> +const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
>>>>> +const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
>>>>> +const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
>>>>> +const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
>>>>> +const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
>>>>> +const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
>>>>> +const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
>>>>> +const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
>>>>> +const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
>>>>> +const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
>>>>> +const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
>>>>> +const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
>>>>> +const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
>>>>> +const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
>>>>> +const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
>>>>> +const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
>>>>> +const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
>>>>> +const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
>>>>> +const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
>>>>> +const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
>>>>> +const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
>>>>> +const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
>>>>> +const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
>>>>> +const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
>>>>> +const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
>>>>> +const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
>>>>> +const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
>>>>> +const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
>>>>> +const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
>>>>> +const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
>>>>> +/* Hole after PTA_MPX was removed.  */
>>>>> +const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
>>>>> +const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
>>>>> +const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
>>>>> +const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
>>>>> +const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
>>>>> +const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
>>>>> +const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
>>>>> +const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
>>>>> +const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
>>>>> +const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
>>>>> +const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
>>>>> +const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
>>>>> +const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
>>>>> +const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
>>>>> +const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
>>>>> +const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
>>>>> +const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
>>>>> +const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
>>>>> +const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
>>>>> +const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
>>>>> +const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
>>>>> +const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
>>>>> +const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
>>>>> +const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
>>>>> +const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
>>>>> +const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
>>>>> +const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
>>>>> +const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
>>>>> +const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
>>>>> +
>>>>> +const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
>>>>> +  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>>>>> +const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>>>>> +  | PTA_POPCNT;
>>>>> +const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
>>>>> +const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
>>>>> +  | PTA_XSAVEOPT;
>>>>> +const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
>>>>> +  | PTA_RDRND | PTA_F16C;
>>>>> +const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
>>>>> +  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>>>>> +const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
>>>>> +  | PTA_RDSEED;
>>>>> +const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
>>>>> +  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
>>>>> +const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
>>>>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>>> +  | PTA_CLWB;
>>>>> +const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
>>>>> +  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
>>>>> +  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
>>>>> +const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
>>>>> +  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
>>>>> +  | PTA_RDPID | PTA_CLWB;
>>>>> +const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
>>>>> +  | PTA_WBNOINVD;
>>>>> +const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
>>>>> +  | PTA_AVX512F | PTA_AVX512CD;
>>>>> +const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>>>>> +const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
>>>>> +const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
>>>>> +  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
>>>>> +  | PTA_FSGSBASE;
>>>>> +const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
>>>>> +  | PTA_SGX;
>>>>> +const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
>>>>> +  | PTA_GFNI;
>>>>> +const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
>>>>> +  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
>>>>> +
>>>>> +#include "insn-attr-common.h"
>>>>> +
>>>>> +struct pta
>>>>> +{
>>>>> +  const char *const name;		/* processor name or nickname.  */
>>>>> +  const enum processor_type processor;
>>>>> +  const enum attr_cpu schedule;
>>>>> +  const wide_int_bitmask flags;
>>>>> +};
>>>>> +
>>>>> +extern const pta processor_alias_table[];
>>>>> +extern int const pta_size;
>>>>> +
>>>>>  extern enum processor_type ix86_tune;
>>>>>  extern enum processor_type ix86_arch;
>>>>>  
>>>>> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
>>>>> index 0ddcd1aa2ac..c743a7d0dc0 100644
>>>>> --- a/gcc/doc/tm.texi
>>>>> +++ b/gcc/doc/tm.texi
>>>>> @@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
>>>>>  Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
>>>>>  @end deftypefn
>>>>>  
>>>>> +@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int)
>>>>> +The hook is used for options that have a non-trivial list of possible option values.
>>>>> +@end deftypefn
>>>>> +
>>>>>  @node Miscellaneous Register Hooks
>>>>>  @subsection Miscellaneous register hooks
>>>>>  @cindex miscellaneous register hooks
>>>>> diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
>>>>> index e275aca0eec..3fbcbea820b 100644
>>>>> --- a/gcc/doc/tm.texi.in
>>>>> +++ b/gcc/doc/tm.texi.in
>>>>> @@ -3669,6 +3669,8 @@ generic code.
>>>>>  
>>>>>  @hook TARGET_SUPPORTS_SPLIT_STACK
>>>>>  
>>>>> +@hook TARGET_GET_VALID_OPTION_VALUES
>>>>> +
>>>>>  @node Miscellaneous Register Hooks
>>>>>  @subsection Miscellaneous register hooks
>>>>>  @cindex miscellaneous register hooks
>>>>> diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
>>>>> index 894eea5f37c..6f3f071a171 100644
>>>>> --- a/gcc/opt-suggestions.c
>>>>> +++ b/gcc/opt-suggestions.c
>>>>> @@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
>>>>>  #include "params.h"
>>>>>  #include "spellcheck.h"
>>>>>  #include "opt-suggestions.h"
>>>>> +#include "common/common-target.h"
>>>>>  #include "selftest.h"
>>>>>  
>>>>>  option_proposer::~option_proposer ()
>>>>> @@ -135,8 +136,24 @@ option_proposer::build_option_suggestions (void)
>>>>>  		}
>>>>>  	    }
>>>>>  	  else
>>>>> -	    add_misspelling_candidates (m_option_suggestions, option,
>>>>> -					opt_text);
>>>>> +	    {
>>>>> +	      vec<const char *> option_values
>>>>> +		= targetm_common.get_valid_option_values (i);
>>>>> +	      if (!option_values.is_empty ())
>>>>> +		{
>>>>> +		  for (unsigned j = 0; j < option_values.length (); j++)
>>>>> +		    {
>>>>> +		      char *with_arg = concat (opt_text, option_values[j],
>>>>> +					       NULL);
>>>>> +		      add_misspelling_candidates (m_option_suggestions, option,
>>>>> +						  with_arg);
>>>>> +		      free (with_arg);
>>>>> +		    }
>>>>> +		}
>>>>> +	      else
>>>>> +		add_misspelling_candidates (m_option_suggestions, option,
>>>>> +					    opt_text);
>>>>> +	    }
>>>>>  	  break;
>>>>>  
>>>>>  	case OPT_fsanitize_:
>>>>> diff --git a/gcc/opts.c b/gcc/opts.c
>>>>> index b8ae8756b4f..97cfd8f455c 100644
>>>>> --- a/gcc/opts.c
>>>>> +++ b/gcc/opts.c
>>>>> @@ -1090,6 +1090,21 @@ wrap_help (const char *help,
>>>>>    while (remaining);
>>>>>  }
>>>>>  
>>>>> +/* Data structure used to print list of valid option values.  */
>>>>> +
>>>>> +struct option_help_tuple
>>>>> +{
>>>>> +  option_help_tuple (int code, vec<const char *> values):
>>>>> +    m_code (code), m_values (values)
>>>>> +  {}
>>>>> +
>>>>> +  /* Code of an option.  */
>>>>> +  int m_code;
>>>>> +
>>>>> +  /* List of possible values.  */
>>>>> +  vec<const char *> m_values;
>>>>> +};
>>>>> +
>>>>>  /* Print help for a specific front-end, etc.  */
>>>>>  static void
>>>>>  print_filtered_help (unsigned int include_flags,
>>>>> @@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
>>>>>    if (!opts->x_help_enum_printed)
>>>>>      opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
>>>>>  
>>>>> +  auto_vec<option_help_tuple> help_tuples;
>>>>> +
>>>>>    for (i = 0; i < cl_options_count; i++)
>>>>>      {
>>>>>        const struct cl_option *option = cl_options + i;
>>>>> @@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
>>>>>        if (option->var_type == CLVC_ENUM
>>>>>  	  && opts->x_help_enum_printed[option->var_enum] != 2)
>>>>>  	opts->x_help_enum_printed[option->var_enum] = 1;
>>>>> +      else
>>>>> +	{
>>>>> +	  vec<const char *> option_values
>>>>> +	    = targetm_common.get_valid_option_values (i);
>>>>> +	  if (!option_values.is_empty ())
>>>>> +	    help_tuples.safe_push (option_help_tuple (i, option_values));
>>>>> +	}
>>>>>      }
>>>>>  
>>>>>    if (! found)
>>>>> @@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
>>>>>        printf ("\n\n");
>>>>>        opts->x_help_enum_printed[i] = 2;
>>>>>      }
>>>>> +
>>>>> +  for (unsigned i = 0; i < help_tuples.length (); i++)
>>>>> +    {
>>>>> +      const struct cl_option *option = cl_options + help_tuples[i].m_code;
>>>>> +      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
>>>>> +      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
>>>>> +	printf (" %s", help_tuples[i].m_values[j]);
>>>>> +      printf ("\n\n");
>>>>> +    }
>>>>>  }
>>>>>  
>>>>>  /* Display help for a specified type of option.
>>>>>
>>>>
>>>
>>
> 

Re: [PATCH] Prototype of hook for possible list of option values.

[Martin Liška]

On 07/20/2018 12:58 PM, Richard Earnshaw (lists) wrote:
> Modifiers are context dependent.  The architecture implies which
> modifiers can be applied (and what they mean in detail, so, for example,
> +fp means enable the default floating point variant for this
> architecture).  Not all modifiers apply to all architectures - +fp is
> not permitted on ARMv4t, for example.

I see, that said I would really add just the target hook suggested. It will
help people in bash completions and provide reasonable list in --help output.

More complex approaches are possible, but don't worth in my opinion.
If you agree, I can clean up the API and improve documentatio?

Martin

Re: [PATCH] Prototype of hook for possible list of option values.

[Richard Earnshaw (lists)]

On 20/07/18 12:06, Martin Liška wrote:
> On 07/20/2018 12:58 PM, Richard Earnshaw (lists) wrote:
>> Modifiers are context dependent.  The architecture implies which
>> modifiers can be applied (and what they mean in detail, so, for example,
>> +fp means enable the default floating point variant for this
>> architecture).  Not all modifiers apply to all architectures - +fp is
>> not permitted on ARMv4t, for example.
> 
> I see, that said I would really add just the target hook suggested. It will
> help people in bash completions and provide reasonable list in --help output.
> 
> More complex approaches are possible, but don't worth in my opinion.
> If you agree, I can clean up the API and improve documentatio?
> 
> Martin
> 

I do wonder if it would be helpful for the API to be able to provide a
'prefix value' for prematching.  So that, for example,

-mcpu=cortex

would pass 'cortex' as a pre-match and then the compiler could supply
just the valid cpus that start with cortex.  or

-mcpu=cortex-a5+

would pass 'cortex-a5+' and the compiler can supply the valid extensions
to that CPU.

R.

Re: [PATCH] Prototype of hook for possible list of option values.

[Martin Liška]

On 07/23/2018 03:47 PM, Richard Earnshaw (lists) wrote:
> On 20/07/18 12:06, Martin Liška wrote:
>> On 07/20/2018 12:58 PM, Richard Earnshaw (lists) wrote:
>>> Modifiers are context dependent.  The architecture implies which
>>> modifiers can be applied (and what they mean in detail, so, for example,
>>> +fp means enable the default floating point variant for this
>>> architecture).  Not all modifiers apply to all architectures - +fp is
>>> not permitted on ARMv4t, for example.
>>
>> I see, that said I would really add just the target hook suggested. It will
>> help people in bash completions and provide reasonable list in --help output.
>>
>> More complex approaches are possible, but don't worth in my opinion.
>> If you agree, I can clean up the API and improve documentatio?
>>
>> Martin
>>
> 
> I do wonder if it would be helpful for the API to be able to provide a
> 'prefix value' for prematching.  So that, for example,
> 
> -mcpu=cortex
> 
> would pass 'cortex' as a pre-match and then the compiler could supply
> just the valid cpus that start with cortex.  or
> 
> -mcpu=cortex-a5+
> 
> would pass 'cortex-a5+' and the compiler can supply the valid extensions
> to that CPU.

Can be definitely beneficial for bash completion. I'll clean up tomorrow
the API and then you can implement the target hook. I'm going to do
implementation for i386. It's simpler, there is only a list of possible
values.

Thanks,
Martin

> 
> R.
> 

[PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 329 bytes --]

Hi.

I'm sending updated version of the patch. It comes up with a new target common hook
that provide option completion list. It's used both in --help=target and with --completion
option. I implemented support for -match and -mtune for i386 target.

Patch can bootstrap on x86_64-linux-gnu and survives regression tests.

Martin

[-- Attachment #2: 0001-Come-up-with-TARGET_GET_VALID_OPTION_VALUES-option-h.patch --]
[-- Type: text/x-patch, Size: 55744 bytes --]

From 28171804c0aaa5c992eb38d2193ce36746b27231 Mon Sep 17 00:00:00 2001
From: marxin <mliska@suse.cz>
Date: Fri, 20 Jul 2018 09:58:16 +0200
Subject: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR
 driver/83193).

gcc/ChangeLog:

2018-07-24  Martin Liska  <mliska@suse.cz>

        PR driver/83193
	* common/common-target.def: Add TARGET_GET_VALID_OPTION_VALUES.
	* common/common-targhooks.c (default_get_valid_option_values):
        New function.
	* common/common-targhooks.h (default_get_valid_option_values):
        Likewise.
	* common/config/i386/i386-common.c: Move processor_target_table
        from i386.c.
	(ix86_get_valid_option_values): New function.
	(TARGET_GET_VALID_OPTION_VALUES): New macro.
	* config/i386/i386.c (struct ptt): Move to i386-common.c.
	(PTA_*): Move all defined masks into i386-common.c.
	(ix86_function_specific_restore): Use new processor_cost_table.
	* config/i386/i386.h (struct ptt): Moved from i386.c.
	(struct pta): Likewise.
	* doc/tm.texi: Document new TARGET_GET_VALID_OPTION_VALUES.
	* doc/tm.texi.in: Likewise.
	* opt-suggestions.c (option_proposer::suggest_option):
        Pass prefix to build_option_suggestions.
	(option_proposer::get_completions): Likewise.
	(option_proposer::build_option_suggestions): Use the new target
        hook.
	* opts.c (struct option_help_tuple): New struct.
	(print_filtered_help): Use the new target hook.

gcc/testsuite/ChangeLog:

2018-07-24  Martin Liska  <mliska@suse.cz>

	* gcc.dg/completion-4.c: New test.
---
 gcc/common/common-target.def         |  10 +
 gcc/common/common-targhooks.c        |   9 +
 gcc/common/common-targhooks.h        |   1 +
 gcc/common/config/i386/i386-common.c | 266 +++++++++++++++++
 gcc/config/i386/i386.c               | 413 +++------------------------
 gcc/config/i386/i386.h               | 146 ++++++++++
 gcc/doc/tm.texi                      |   4 +
 gcc/doc/tm.texi.in                   |   2 +
 gcc/opt-suggestions.c                |  27 +-
 gcc/opt-suggestions.h                |   6 +-
 gcc/opts.c                           |  33 +++
 gcc/testsuite/gcc.dg/completion-4.c  |   6 +
 12 files changed, 546 insertions(+), 377 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/completion-4.c

diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
index e0afbc6af29..99d5264448a 100644
--- a/gcc/common/common-target.def
+++ b/gcc/common/common-target.def
@@ -80,6 +80,16 @@ DEFHOOK
  bool, (bool report, struct gcc_options *opts),
  hook_bool_bool_gcc_optionsp_false)
 
+DEFHOOK
+(get_valid_option_values,
+"The hook is used for options that have a non-trivial list of\
+ possible option values.  OPTION_CODE is option code of opt_code\
+ enum type.  PREFIX is used for bash completion and allows an implementation\
+ to return more specific completion based on the prefix.  All string values\
+ should be allocated from heap memory and consumers should release them.",
+ vec<const char *>, (int option_code, const char *prefix),
+ default_get_valid_option_values)
+
 /* Leave the boolean fields at the end.  */
 
 /* True if unwinding tables should be generated by default.  */
diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
index b1090190664..747c7da55ca 100644
--- a/gcc/common/common-targhooks.c
+++ b/gcc/common/common-targhooks.c
@@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tm.h"
 #include "common/common-target.h"
 #include "common/common-targhooks.h"
+#include "opts.h"
 
 /* Determine the exception handling mechanism for the target.  */
 
@@ -77,6 +78,14 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
   return true;
 }
 
+/* Default version of TARGET_GET_VALID_OPTION_VALUES.  */
+
+vec<const char *>
+default_get_valid_option_values (int option_code, const char *prefix)
+{
+  return vec<const char *> ();
+}
+
 const struct default_options empty_optimization_table[] =
   {
     { OPT_LEVELS_NONE, 0, NULL, 0 }
diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
index d290d7f3e21..4bdf8efdbe6 100644
--- a/gcc/common/common-targhooks.h
+++ b/gcc/common/common-targhooks.h
@@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
 					  struct gcc_options *,
 					  const struct cl_decoded_option *,
 					  location_t);
+extern vec<const char *> default_get_valid_option_values (int, const char *);
 
 extern const struct default_options empty_optimization_table[];
 
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 70b3c3f2fc3..35ac71be5e5 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1459,4 +1459,270 @@ i386_except_unwind_info (struct gcc_options *opts)
 #undef TARGET_SUPPORTS_SPLIT_STACK
 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
 
+/* This table must be in sync with enum processor_type in i386.h.  */
+const struct ptt processor_target_table[PROCESSOR_max] =
+{
+  /* The "0:0:8" label alignment specified for some processors generates
+     secondary 8-byte alignment only for those label/jump/loop targets
+     which have primary alignment.  */
+
+  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"i386",           "4",       "4",       NULL,    "4" },
+  {"i486",           "16",      "16",      "0:0:8", "16"},
+  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
+  {"pentium4",       NULL,      NULL,      NULL,    NULL},
+  {"nocona",         NULL,      NULL,      NULL,    NULL},
+  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
+  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
+  {"geode",          NULL,      NULL,      NULL,    NULL},
+  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
+  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
+  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"znver1",         "16",      "16",      "0:0:8", "16"}
+};
+
+const pta processor_alias_table[] =
+{
+  {"i386", PROCESSOR_I386, CPU_NONE, 0},
+  {"i486", PROCESSOR_I486, CPU_NONE, 0},
+  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
+  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
+  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
+  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
+  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
+  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
+  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
+  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
+    PTA_SKYLAKE_AVX512},
+  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
+  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
+    PTA_ICELAKE_CLIENT},
+  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
+    PTA_ICELAKE_SERVER},
+  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
+  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
+  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
+  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
+  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
+  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+  {"geode", PROCESSOR_GEODE, CPU_GEODE,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
+  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"x86-64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"k8", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"k8-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon-fx", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
+      | PTA_XSAVEOPT | PTA_FSGSBASE},
+  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
+      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
+      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
+      | PTA_MOVBE | PTA_MWAITX},
+  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
+      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
+      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
+      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE},
+  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
+      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+
+  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
+    PTA_64BIT
+      | PTA_HLE /* flags are only used for -march switch.  */ },
+};
+
+int const pta_size = ARRAY_SIZE (processor_alias_table);
+
+/* Provide valid option values for -march and -mtune options.  */
+
+vec<const char *>
+ix86_get_valid_option_values (int option_code, const char *prefix)
+{
+  vec<const char *> v;
+  v.create (0);
+  opt_code opt = (opt_code) option_code;
+
+  switch (opt)
+    {
+    case OPT_march_:
+      for (unsigned i = 0; i < pta_size; i++)
+	v.safe_push (processor_alias_table[i].name);
+      break;
+    case OPT_mtune_:
+      for (unsigned i = 0; i < PROCESSOR_max; i++)
+	v.safe_push (processor_target_table[i].name);
+      break;
+    default:
+      break;
+    }
+
+  return v;
+}
+
+#undef  TARGET_GET_VALID_OPTION_VALUES
+#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ee409cfe7e4..c0f56e675f6 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -832,63 +832,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
 static tree ix86_veclibabi_svml (combined_fn, tree, tree);
 static tree ix86_veclibabi_acml (combined_fn, tree, tree);
 
-/* Processor target table, indexed by processor number */
-struct ptt
-{
-  const char *const name;			/* processor name  */
-  const struct processor_costs *cost;		/* Processor costs */
-
-  /* Default alignments.  */
-  const char *const align_loop;
-  const char *const align_jump;
-  const char *const align_label;
-  const char *const align_func;
-};
-
 /* This table must be in sync with enum processor_type in i386.h.  */ 
-static const struct ptt processor_target_table[PROCESSOR_max] =
-{
-/* The "0:0:8" label alignment specified for some processors generates
-   secondary 8-byte alignment only for those label/jump/loop targets
-   which have primary alignment.  */
-
-  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
-  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
-  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
-  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
-  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
-  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
-  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
-  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
-  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
-  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
-  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
-  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
+static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
+{
+  &generic_cost,
+  &i386_cost,
+  &i486_cost,
+  &pentium_cost,
+  &lakemont_cost,
+  &pentiumpro_cost,
+  &pentium4_cost,
+  &nocona_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &atom_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &intel_cost,
+  &geode_cost,
+  &k6_cost,
+  &athlon_cost,
+  &k8_cost,
+  &amdfam10_cost,
+  &bdver1_cost,
+  &bdver2_cost,
+  &bdver3_cost,
+  &bdver4_cost,
+  &btver1_cost,
+  &btver2_cost,
+  &znver1_cost,
 };
 \f
 static unsigned int
@@ -3399,6 +3382,8 @@ ix86_override_options_after_change (void)
   ix86_default_align (&global_options);
 }
 
+
+
 /* Override various settings based on options.  If MAIN_ARGS_P, the
    options are from the command line, otherwise they are from
    attributes.  Return true if there's an error related to march
@@ -3413,317 +3398,6 @@ ix86_option_override_internal (bool main_args_p,
   unsigned HOST_WIDE_INT ix86_arch_mask;
   const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
 
-  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
-  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
-  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
-  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
-  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
-  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
-  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
-  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
-  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
-  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
-  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
-  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
-  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
-  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
-  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
-  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
-  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
-  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
-  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
-  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
-  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
-  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
-  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
-  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
-  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
-  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
-  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
-  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
-  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
-  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
-  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
-  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
-  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
-  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
-  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
-  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
-  /* Hole after PTA_MPX was removed.  */
-  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
-  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
-  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
-  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
-  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
-  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
-  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
-  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
-  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
-  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
-  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
-  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
-  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
-  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
-  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
-  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
-  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
-  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
-  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
-  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
-  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
-
-  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
-    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
-  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
-    | PTA_POPCNT;
-  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
-  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
-    | PTA_XSAVEOPT;
-  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
-    | PTA_RDRND | PTA_F16C;
-  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
-    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
-    | PTA_RDSEED;
-  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
-    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
-  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_CLWB;
-  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
-  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
-    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
-    | PTA_RDPID | PTA_CLWB;
-  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
-    | PTA_WBNOINVD;
-  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
-    | PTA_AVX512F | PTA_AVX512CD;
-  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
-  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
-  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
-    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
-    | PTA_FSGSBASE;
-  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
-    | PTA_SGX;
-  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
-    | PTA_GFNI;
-  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
-    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
-
-  static struct pta
-    {
-      const char *const name;		/* processor name or nickname.  */
-      const enum processor_type processor;
-      const enum attr_cpu schedule;
-      const wide_int_bitmask flags;
-    }
-  const processor_alias_table[] =
-    {
-      {"i386", PROCESSOR_I386, CPU_NONE, 0},
-      {"i486", PROCESSOR_I486, CPU_NONE, 0},
-      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
-      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
-      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
-      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
-      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
-      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
-      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
-      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
-      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
-      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
-        PTA_SKYLAKE_AVX512},
-      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
-      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
-	PTA_ICELAKE_CLIENT},
-      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
-	PTA_ICELAKE_SERVER},
-      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
-      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
-      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
-      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
-      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
-      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
-      {"geode", PROCESSOR_GEODE, CPU_GEODE,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
-      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"x86-64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"eden-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nano", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-1000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-2000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-3000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"eden-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"k8", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"k8-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon-fx", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
-	| PTA_XSAVEOPT | PTA_FSGSBASE},
-      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
-	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
-	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
-	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
-	| PTA_MOVBE | PTA_MWAITX},
-      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
-	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
-	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
-	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
-	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
-      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE},
-      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
-	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
-
-      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
-	PTA_64BIT
-	| PTA_HLE /* flags are only used for -march switch.  */ },
-    };
-
   /* -mrecip options.  */
   static struct
     {
@@ -3740,7 +3414,6 @@ ix86_option_override_internal (bool main_args_p,
       { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
     };
 
-  int const pta_size = ARRAY_SIZE (processor_alias_table);
 
   /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
      TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
@@ -4396,7 +4069,7 @@ ix86_option_override_internal (bool main_args_p,
 	}
     }
 
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
@@ -5193,7 +4866,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
   opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
   opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
   opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index fbba598ffd5..bd2b834dadd 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2283,6 +2283,152 @@ enum processor_type
   PROCESSOR_max
 };
 
+#ifndef IN_LIBGCC2
+/* Processor target table, indexed by processor number */
+struct ptt
+{
+  const char *const name;			/* processor name  */
+
+  /* Default alignments.  */
+  const char *const align_loop;
+  const char *const align_jump;
+  const char *const align_label;
+  const char *const align_func;
+};
+
+extern const struct ptt processor_target_table[PROCESSOR_max];
+
+#include "wide-int-bitmask.h"
+
+const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
+const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
+const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
+const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
+const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
+const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
+const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
+const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
+const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
+const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+/* Hole after PTA_MPX was removed.  */
+const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
+const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
+const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
+const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
+const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
+
+const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+  | PTA_POPCNT;
+const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+  | PTA_XSAVEOPT;
+const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
+  | PTA_RDRND | PTA_F16C;
+const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
+  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+  | PTA_RDSEED;
+const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
+const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_CLWB;
+const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
+const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
+  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
+  | PTA_RDPID | PTA_CLWB;
+const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
+  | PTA_WBNOINVD;
+const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+  | PTA_AVX512F | PTA_AVX512CD;
+const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
+  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
+  | PTA_FSGSBASE;
+const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
+  | PTA_SGX;
+const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
+  | PTA_GFNI;
+const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
+  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
+
+#include "insn-attr-common.h"
+
+struct pta
+{
+  const char *const name;		/* processor name or nickname.  */
+  const enum processor_type processor;
+  const enum attr_cpu schedule;
+  const wide_int_bitmask flags;
+};
+
+extern const pta processor_alias_table[];
+extern int const pta_size;
+#endif
+
 extern enum processor_type ix86_tune;
 extern enum processor_type ix86_arch;
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 0ddcd1aa2ac..1f9b216b8b6 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
 Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
 @end deftypefn
 
+@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int @var{option_code}, const char *@var{prefix})
+The hook is used for options that have a non-trivial list of possible option values.  OPTION_CODE is option code of opt_code enum type.  PREFIX is used for bash completion and allows an implementation to return more specific completion based on the prefix.  All string values should be allocated from heap memory and consumers should release them.
+@end deftypefn
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index e275aca0eec..3fbcbea820b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3669,6 +3669,8 @@ generic code.
 
 @hook TARGET_SUPPORTS_SPLIT_STACK
 
+@hook TARGET_GET_VALID_OPTION_VALUES
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
index 894eea5f37c..faaee076b53 100644
--- a/gcc/opt-suggestions.c
+++ b/gcc/opt-suggestions.c
@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "params.h"
 #include "spellcheck.h"
 #include "opt-suggestions.h"
+#include "common/common-target.h"
 #include "selftest.h"
 
 option_proposer::~option_proposer ()
@@ -38,7 +39,7 @@ option_proposer::suggest_option (const char *bad_opt)
 {
   /* Lazily populate m_option_suggestions.  */
   if (!m_option_suggestions)
-    build_option_suggestions ();
+    build_option_suggestions (NULL);
   gcc_assert (m_option_suggestions);
 
   /* "m_option_suggestions" is now populated.  Use it.  */
@@ -80,7 +81,7 @@ option_proposer::get_completions (const char *option_prefix,
     {
       /* Lazily populate m_option_suggestions.  */
       if (!m_option_suggestions)
-	build_option_suggestions ();
+	build_option_suggestions (option_prefix);
       gcc_assert (m_option_suggestions);
 
       for (unsigned i = 0; i < m_option_suggestions->length (); i++)
@@ -108,7 +109,7 @@ option_proposer::suggest_completion (const char *option_prefix)
 }
 
 void
-option_proposer::build_option_suggestions (void)
+option_proposer::build_option_suggestions (const char *prefix)
 {
   gcc_assert (m_option_suggestions == NULL);
   m_option_suggestions = new auto_string_vec ();
@@ -135,8 +136,24 @@ option_proposer::build_option_suggestions (void)
 		}
 	    }
 	  else
-	    add_misspelling_candidates (m_option_suggestions, option,
-					opt_text);
+	    {
+	      vec<const char *> option_values
+		= targetm_common.get_valid_option_values (i, prefix);
+	      if (!option_values.is_empty ())
+		{
+		  for (unsigned j = 0; j < option_values.length (); j++)
+		    {
+		      char *with_arg = concat (opt_text, option_values[j],
+					       NULL);
+		      add_misspelling_candidates (m_option_suggestions, option,
+						  with_arg);
+		      free (with_arg);
+		    }
+		}
+	      else
+		add_misspelling_candidates (m_option_suggestions, option,
+					    opt_text);
+	    }
 	  break;
 
 	case OPT_fsanitize_:
diff --git a/gcc/opt-suggestions.h b/gcc/opt-suggestions.h
index 222bafa12cd..eb932779939 100644
--- a/gcc/opt-suggestions.h
+++ b/gcc/opt-suggestions.h
@@ -58,8 +58,10 @@ public:
 private:
   /* Helper function for option_proposer::suggest_option.  Populate
      m_option_suggestions with candidate strings for misspelled options.
-     The strings will be freed by the option_proposer's dtor.  */
-  void build_option_suggestions ();
+     The strings will be freed by the option_proposer's dtor.
+     PREFIX is used for bash completion suggestions, otherwise
+     it's set to NULL.  */
+  void build_option_suggestions (const char *prefix);
 
   /* Find parameter completions for --param format with SEPARATOR.
      Again, save the completions into results.  */
diff --git a/gcc/opts.c b/gcc/opts.c
index 17d91988ada..7b36a7d8cc4 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1090,6 +1090,21 @@ wrap_help (const char *help,
   while (remaining);
 }
 
+/* Data structure used to print list of valid option values.  */
+
+struct option_help_tuple
+{
+  option_help_tuple (int code, vec<const char *> values):
+    m_code (code), m_values (values)
+  {}
+
+  /* Code of an option.  */
+  int m_code;
+
+  /* List of possible values.  */
+  vec<const char *> m_values;
+};
+
 /* Print help for a specific front-end, etc.  */
 static void
 print_filtered_help (unsigned int include_flags,
@@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
   if (!opts->x_help_enum_printed)
     opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
 
+  auto_vec<option_help_tuple> help_tuples;
+
   for (i = 0; i < cl_options_count; i++)
     {
       const struct cl_option *option = cl_options + i;
@@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
       if (option->var_type == CLVC_ENUM
 	  && opts->x_help_enum_printed[option->var_enum] != 2)
 	opts->x_help_enum_printed[option->var_enum] = 1;
+      else
+	{
+	  vec<const char *> option_values
+	    = targetm_common.get_valid_option_values (i, NULL);
+	  if (!option_values.is_empty ())
+	    help_tuples.safe_push (option_help_tuple (i, option_values));
+	}
     }
 
   if (! found)
@@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
       printf ("\n\n");
       opts->x_help_enum_printed[i] = 2;
     }
+
+  for (unsigned i = 0; i < help_tuples.length (); i++)
+    {
+      const struct cl_option *option = cl_options + help_tuples[i].m_code;
+      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
+      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
+	printf (" %s", help_tuples[i].m_values[j]);
+      printf ("\n\n");
+    }
 }
 
 /* Display help for a specified type of option.
diff --git a/gcc/testsuite/gcc.dg/completion-4.c b/gcc/testsuite/gcc.dg/completion-4.c
new file mode 100644
index 00000000000..8116811998a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/completion-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-options "--completion=-march=geo" } */
+
+/* { dg-begin-multiline-output "" }
+-march=geode
+   { dg-end-multiline-output "" } */
-- 
2.18.0

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Martin Liška]

PING^1

On 07/24/2018 02:05 PM, Martin Liška wrote:
> Hi.
> 
> I'm sending updated version of the patch. It comes up with a new target common hook
> that provide option completion list. It's used both in --help=target and with --completion
> option. I implemented support for -match and -mtune for i386 target.
> 
> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
> 
> Martin
> 

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Ramana Radhakrishnan]

On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
> PING^1
>
> On 07/24/2018 02:05 PM, Martin Liška wrote:
>> Hi.
>>
>> I'm sending updated version of the patch. It comes up with a new target common hook
>> that provide option completion list. It's used both in --help=target and with --completion
>> option. I implemented support for -match and -mtune for i386 target.
>>
>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.


Err I don't maintain the x86 backend to review this effectively. In an
ideal world you would have split this into 2 patches 1 for the common
parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
clear what you are looking for here from me :-/

Ramana
>>
>> Martin
>>
>

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Martin Liška]

On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
>> PING^1
>>
>> On 07/24/2018 02:05 PM, Martin Liška wrote:
>>> Hi.
>>>
>>> I'm sending updated version of the patch. It comes up with a new target common hook
>>> that provide option completion list. It's used both in --help=target and with --completion
>>> option. I implemented support for -match and -mtune for i386 target.
>>>
>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
> 
> 
> Err I don't maintain the x86 backend to review this effectively. In an
> ideal world you would have split this into 2 patches 1 for the common
> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
> clear what you are looking for here from me :-/

Sorry, I was not clear. I would like to hear from ARM's folks that interface
design is fine for them? I know a global reviewer will have to approve that.

Martin

> 
> Ramana
>>>
>>> Martin
>>>
>>

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Ramana Radhakrishnan]

On Mon, Aug 13, 2018 at 2:00 PM, Martin Liška <mliska@suse.cz> wrote:
> On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
>> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
>>> PING^1
>>>
>>> On 07/24/2018 02:05 PM, Martin Liška wrote:
>>>> Hi.
>>>>
>>>> I'm sending updated version of the patch. It comes up with a new target common hook
>>>> that provide option completion list. It's used both in --help=target and with --completion
>>>> option. I implemented support for -match and -mtune for i386 target.
>>>>
>>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>>
>>
>> Err I don't maintain the x86 backend to review this effectively. In an
>> ideal world you would have split this into 2 patches 1 for the common
>> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
>> clear what you are looking for here from me :-/
>
> Sorry, I was not clear. I would like to hear from ARM's folks that interface
> design is fine for them? I know a global reviewer will have to approve that.

Ok, thanks for the explanation , I'll try and have a look but my
afternoon's looking shafted.

Ramana
>
> Martin
>
>>
>> Ramana
>>>>
>>>> Martin
>>>>
>>>
>

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Martin Liška]

On 08/13/2018 03:00 PM, Martin Liška wrote:
> On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
>> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
>>> PING^1
>>>
>>> On 07/24/2018 02:05 PM, Martin Liška wrote:
>>>> Hi.
>>>>
>>>> I'm sending updated version of the patch. It comes up with a new target common hook
>>>> that provide option completion list. It's used both in --help=target and with --completion
>>>> option. I implemented support for -match and -mtune for i386 target.
>>>>
>>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>>
>>
>> Err I don't maintain the x86 backend to review this effectively. In an
>> ideal world you would have split this into 2 patches 1 for the common
>> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
>> clear what you are looking for here from me :-/
> 
> Sorry, I was not clear. I would like to hear from ARM's folks that interface
> design is fine for them? I know a global reviewer will have to approve that.

I'm CC'ing Jakub and Richard who can help us with the new target hook infrastructure.

Martin

> 
> Martin
> 
>>
>> Ramana
>>>>
>>>> Martin
>>>>
>>>
> 

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Richard Biener]

On Mon, Aug 27, 2018 at 12:00 PM Martin Liška <mliska@suse.cz> wrote:
>
> On 08/13/2018 03:00 PM, Martin Liška wrote:
> > On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
> >> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
> >>> PING^1
> >>>
> >>> On 07/24/2018 02:05 PM, Martin Liška wrote:
> >>>> Hi.
> >>>>
> >>>> I'm sending updated version of the patch. It comes up with a new target common hook
> >>>> that provide option completion list. It's used both in --help=target and with --completion
> >>>> option. I implemented support for -match and -mtune for i386 target.
> >>>>
> >>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
> >>
> >>
> >> Err I don't maintain the x86 backend to review this effectively. In an
> >> ideal world you would have split this into 2 patches 1 for the common
> >> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
> >> clear what you are looking for here from me :-/
> >
> > Sorry, I was not clear. I would like to hear from ARM's folks that interface
> > design is fine for them? I know a global reviewer will have to approve that.
>
> I'm CC'ing Jakub and Richard who can help us with the new target hook infrastructure.

+vec<const char *>
+ix86_get_valid_option_values (int option_code, const char *prefix)
+{

prefix isn't used - why does that not fail bootstrap?  It requires documentation
that honoring prefix isn't required and callers have to deal with
that.  IMHO that
makes prefix useless?

Unfortunately option_proposer::build_option_suggestions isn't documented
so I don't see whether it only receives target options.  If not then

-           add_misspelling_candidates (m_option_suggestions, option,
-                                       opt_text);
+           {
+             vec<const char *> option_values
+               = targetm_common.get_valid_option_values (i, prefix);
+             if (!option_values.is_empty ())

this should be guarded with a check for whether this is a target
option (CL_TARGET
in flags).  I wonder why misspellings are to be checked for the bash
completion case?

I also wonder why those target options could not simply be of Enum type and thus
be automatically handled?

Richard.

> Martin
>
> >
> > Martin
> >
> >>
> >> Ramana
> >>>>
> >>>> Martin
> >>>>
> >>>
> >
>

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 3829 bytes --]

On 08/29/2018 01:06 PM, Richard Biener wrote:
> On Mon, Aug 27, 2018 at 12:00 PM Martin Liška <mliska@suse.cz> wrote:
>>
>> On 08/13/2018 03:00 PM, Martin Liška wrote:
>>> On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
>>>> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
>>>>> PING^1
>>>>>
>>>>> On 07/24/2018 02:05 PM, Martin Liška wrote:
>>>>>> Hi.
>>>>>>
>>>>>> I'm sending updated version of the patch. It comes up with a new target common hook
>>>>>> that provide option completion list. It's used both in --help=target and with --completion
>>>>>> option. I implemented support for -match and -mtune for i386 target.
>>>>>>
>>>>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>>>>
>>>>
>>>> Err I don't maintain the x86 backend to review this effectively. In an
>>>> ideal world you would have split this into 2 patches 1 for the common
>>>> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
>>>> clear what you are looking for here from me :-/
>>>
>>> Sorry, I was not clear. I would like to hear from ARM's folks that interface
>>> design is fine for them? I know a global reviewer will have to approve that.
>>
>> I'm CC'ing Jakub and Richard who can help us with the new target hook infrastructure.
> 
> +vec<const char *>
> +ix86_get_valid_option_values (int option_code, const char *prefix)
> +{
> 
> prefix isn't used - why does that not fail bootstrap? 

Will add ATTRIBUTE_UNUSED.

 It requires documentation
> that honoring prefix isn't required and callers have to deal with

It's more detail described in common-target.def:

'The hook is used for options that have a non-trivial list of\
 possible option values.  OPTION_CODE is option code of opt_code\
 enum type.  PREFIX is used for bash completion and allows an implementation\
 to return more specific completion based on the prefix.  All string values\
 should be allocated from heap memory and consumers should release them.'

Should I copy it to the implementation.

> that.  IMHO that
> makes prefix useless?

ARM folks requested that, they want to do a smart filtering for bash completion.
It was there request.

> 
> Unfortunately option_proposer::build_option_suggestions isn't documented
> so I don't see whether it only receives target options.  If not then
> 
> -           add_misspelling_candidates (m_option_suggestions, option,
> -                                       opt_text);
> +           {
> +             vec<const char *> option_values
> +               = targetm_common.get_valid_option_values (i, prefix);
> +             if (!option_values.is_empty ())
> 
> this should be guarded with a check for whether this is a target
> option (CL_TARGET
> in flags). 

Good point!

 I wonder why misspellings are to be checked for the bash
> completion case?

Note that option_proposer::build_option_suggestions is shared infrastructure
in between bash completion and misspellings.

2 examples:

$ /xgcc -B. -march=znver2 -c /tmp/empty.c
cc1: error: bad value (‘znver2’) for ‘-march=’ switch
cc1: note: valid arguments to ‘-march=’ switch are:  ... did you mean ‘znver1’?

$  ./xgcc -B. --completion=-march=znver
-march=znver1

> 
> I also wonder why those target options could not simply be of Enum type and thus
> be automatically handled?

What a question, I asked the same one before I implemented that. It's because
you have modifiers like: -march=armv8.3-a+simd+crypto+nofp for aarch64 target.
For i386, it's also manually parsed because of tables that group
options and various values:

processor_target_table
processor_alias_table

I'm sending updated version of patch that I'm going to test.

Martin

> 
> Richard.
> 
>> Martin
>>
>>>
>>> Martin
>>>
>>>>
>>>> Ramana
>>>>>>
>>>>>> Martin
>>>>>>
>>>>>
>>>
>>


[-- Attachment #2: 0001-Come-up-with-TARGET_GET_VALID_OPTION_VALUES-option-h.patch --]
[-- Type: text/x-patch, Size: 55852 bytes --]

From c01199fd277330f50fe4ba057d6bdb7b944ef9e4 Mon Sep 17 00:00:00 2001
From: marxin <mliska@suse.cz>
Date: Fri, 20 Jul 2018 09:58:16 +0200
Subject: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR
 driver/83193).

gcc/ChangeLog:

2018-07-24  Martin Liska  <mliska@suse.cz>

        PR driver/83193
	* common/common-target.def: Add TARGET_GET_VALID_OPTION_VALUES.
	* common/common-targhooks.c (default_get_valid_option_values):
        New function.
	* common/common-targhooks.h (default_get_valid_option_values):
        Likewise.
	* common/config/i386/i386-common.c: Move processor_target_table
        from i386.c.
	(ix86_get_valid_option_values): New function.
	(TARGET_GET_VALID_OPTION_VALUES): New macro.
	* config/i386/i386.c (struct ptt): Move to i386-common.c.
	(PTA_*): Move all defined masks into i386-common.c.
	(ix86_function_specific_restore): Use new processor_cost_table.
	* config/i386/i386.h (struct ptt): Moved from i386.c.
	(struct pta): Likewise.
	* doc/tm.texi: Document new TARGET_GET_VALID_OPTION_VALUES.
	* doc/tm.texi.in: Likewise.
	* opt-suggestions.c (option_proposer::suggest_option):
        Pass prefix to build_option_suggestions.
	(option_proposer::get_completions): Likewise.
	(option_proposer::build_option_suggestions): Use the new target
        hook.
	* opts.c (struct option_help_tuple): New struct.
	(print_filtered_help): Use the new target hook.

gcc/testsuite/ChangeLog:

2018-07-24  Martin Liska  <mliska@suse.cz>

	* gcc.dg/completion-4.c: New test.
---
 gcc/common/common-target.def         |  10 +
 gcc/common/common-targhooks.c        |   9 +
 gcc/common/common-targhooks.h        |   1 +
 gcc/common/config/i386/i386-common.c | 267 +++++++++++++++++
 gcc/config/i386/i386.c               | 413 +++------------------------
 gcc/config/i386/i386.h               | 150 ++++++++++
 gcc/doc/tm.texi                      |   4 +
 gcc/doc/tm.texi.in                   |   2 +
 gcc/opt-suggestions.c                |  30 +-
 gcc/opt-suggestions.h                |   6 +-
 gcc/opts.c                           |  33 +++
 gcc/testsuite/gcc.dg/completion-4.c  |   6 +
 12 files changed, 554 insertions(+), 377 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/completion-4.c

diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
index e0afbc6af29..99d5264448a 100644
--- a/gcc/common/common-target.def
+++ b/gcc/common/common-target.def
@@ -80,6 +80,16 @@ DEFHOOK
  bool, (bool report, struct gcc_options *opts),
  hook_bool_bool_gcc_optionsp_false)
 
+DEFHOOK
+(get_valid_option_values,
+"The hook is used for options that have a non-trivial list of\
+ possible option values.  OPTION_CODE is option code of opt_code\
+ enum type.  PREFIX is used for bash completion and allows an implementation\
+ to return more specific completion based on the prefix.  All string values\
+ should be allocated from heap memory and consumers should release them.",
+ vec<const char *>, (int option_code, const char *prefix),
+ default_get_valid_option_values)
+
 /* Leave the boolean fields at the end.  */
 
 /* True if unwinding tables should be generated by default.  */
diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
index b1090190664..747c7da55ca 100644
--- a/gcc/common/common-targhooks.c
+++ b/gcc/common/common-targhooks.c
@@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tm.h"
 #include "common/common-target.h"
 #include "common/common-targhooks.h"
+#include "opts.h"
 
 /* Determine the exception handling mechanism for the target.  */
 
@@ -77,6 +78,14 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
   return true;
 }
 
+/* Default version of TARGET_GET_VALID_OPTION_VALUES.  */
+
+vec<const char *>
+default_get_valid_option_values (int option_code, const char *prefix)
+{
+  return vec<const char *> ();
+}
+
 const struct default_options empty_optimization_table[] =
   {
     { OPT_LEVELS_NONE, 0, NULL, 0 }
diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
index d290d7f3e21..4bdf8efdbe6 100644
--- a/gcc/common/common-targhooks.h
+++ b/gcc/common/common-targhooks.h
@@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
 					  struct gcc_options *,
 					  const struct cl_decoded_option *,
 					  location_t);
+extern vec<const char *> default_get_valid_option_values (int, const char *);
 
 extern const struct default_options empty_optimization_table[];
 
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 70b3c3f2fc3..1013f82b23d 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1459,4 +1459,271 @@ i386_except_unwind_info (struct gcc_options *opts)
 #undef TARGET_SUPPORTS_SPLIT_STACK
 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
 
+/* This table must be in sync with enum processor_type in i386.h.  */
+const struct ptt processor_target_table[PROCESSOR_max] =
+{
+  /* The "0:0:8" label alignment specified for some processors generates
+     secondary 8-byte alignment only for those label/jump/loop targets
+     which have primary alignment.  */
+
+  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"i386",           "4",       "4",       NULL,    "4" },
+  {"i486",           "16",      "16",      "0:0:8", "16"},
+  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
+  {"pentium4",       NULL,      NULL,      NULL,    NULL},
+  {"nocona",         NULL,      NULL,      NULL,    NULL},
+  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
+  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
+  {"geode",          NULL,      NULL,      NULL,    NULL},
+  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
+  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
+  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"znver1",         "16",      "16",      "0:0:8", "16"}
+};
+
+const pta processor_alias_table[] =
+{
+  {"i386", PROCESSOR_I386, CPU_NONE, 0},
+  {"i486", PROCESSOR_I486, CPU_NONE, 0},
+  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
+  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
+  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
+  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
+  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
+  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
+  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
+  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
+    PTA_SKYLAKE_AVX512},
+  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
+  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
+    PTA_ICELAKE_CLIENT},
+  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
+    PTA_ICELAKE_SERVER},
+  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
+  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
+  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
+  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
+  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
+  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+  {"geode", PROCESSOR_GEODE, CPU_GEODE,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
+  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"x86-64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"k8", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"k8-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon-fx", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
+      | PTA_XSAVEOPT | PTA_FSGSBASE},
+  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
+      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
+      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
+      | PTA_MOVBE | PTA_MWAITX},
+  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
+      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
+      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
+      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE},
+  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
+      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+
+  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
+    PTA_64BIT
+      | PTA_HLE /* flags are only used for -march switch.  */ },
+};
+
+int const pta_size = ARRAY_SIZE (processor_alias_table);
+
+/* Provide valid option values for -march and -mtune options.  */
+
+vec<const char *>
+ix86_get_valid_option_values (int option_code,
+			      const char *prefix ATTRIBUTE_UNUSED)
+{
+  vec<const char *> v;
+  v.create (0);
+  opt_code opt = (opt_code) option_code;
+
+  switch (opt)
+    {
+    case OPT_march_:
+      for (unsigned i = 0; i < pta_size; i++)
+	v.safe_push (processor_alias_table[i].name);
+      break;
+    case OPT_mtune_:
+      for (unsigned i = 0; i < PROCESSOR_max; i++)
+	v.safe_push (processor_target_table[i].name);
+      break;
+    default:
+      break;
+    }
+
+  return v;
+}
+
+#undef  TARGET_GET_VALID_OPTION_VALUES
+#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c437c18a29c..48e484b3d62 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -828,63 +828,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
 static tree ix86_veclibabi_svml (combined_fn, tree, tree);
 static tree ix86_veclibabi_acml (combined_fn, tree, tree);
 
-/* Processor target table, indexed by processor number */
-struct ptt
-{
-  const char *const name;			/* processor name  */
-  const struct processor_costs *cost;		/* Processor costs */
-
-  /* Default alignments.  */
-  const char *const align_loop;
-  const char *const align_jump;
-  const char *const align_label;
-  const char *const align_func;
-};
-
 /* This table must be in sync with enum processor_type in i386.h.  */ 
-static const struct ptt processor_target_table[PROCESSOR_max] =
-{
-/* The "0:0:8" label alignment specified for some processors generates
-   secondary 8-byte alignment only for those label/jump/loop targets
-   which have primary alignment.  */
-
-  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
-  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
-  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
-  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
-  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
-  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
-  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
-  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
-  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
-  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
-  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
-  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
+static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
+{
+  &generic_cost,
+  &i386_cost,
+  &i486_cost,
+  &pentium_cost,
+  &lakemont_cost,
+  &pentiumpro_cost,
+  &pentium4_cost,
+  &nocona_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &atom_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &intel_cost,
+  &geode_cost,
+  &k6_cost,
+  &athlon_cost,
+  &k8_cost,
+  &amdfam10_cost,
+  &bdver1_cost,
+  &bdver2_cost,
+  &bdver3_cost,
+  &bdver4_cost,
+  &btver1_cost,
+  &btver2_cost,
+  &znver1_cost,
 };
 \f
 static unsigned int
@@ -3386,6 +3369,8 @@ ix86_override_options_after_change (void)
   ix86_default_align (&global_options);
 }
 
+
+
 /* Override various settings based on options.  If MAIN_ARGS_P, the
    options are from the command line, otherwise they are from
    attributes.  Return true if there's an error related to march
@@ -3400,317 +3385,6 @@ ix86_option_override_internal (bool main_args_p,
   unsigned HOST_WIDE_INT ix86_arch_mask;
   const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
 
-  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
-  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
-  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
-  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
-  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
-  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
-  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
-  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
-  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
-  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
-  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
-  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
-  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
-  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
-  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
-  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
-  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
-  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
-  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
-  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
-  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
-  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
-  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
-  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
-  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
-  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
-  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
-  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
-  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
-  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
-  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
-  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
-  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
-  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
-  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
-  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
-  /* Hole after PTA_MPX was removed.  */
-  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
-  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
-  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
-  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
-  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
-  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
-  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
-  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
-  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
-  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
-  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
-  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
-  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
-  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
-  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
-  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
-  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
-  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
-  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
-  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
-  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
-
-  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
-    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
-  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
-    | PTA_POPCNT;
-  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
-  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
-    | PTA_XSAVEOPT;
-  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
-    | PTA_RDRND | PTA_F16C;
-  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
-    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
-    | PTA_RDSEED;
-  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
-    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
-  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_CLWB;
-  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
-  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
-    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
-    | PTA_RDPID | PTA_CLWB;
-  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
-    | PTA_WBNOINVD;
-  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
-    | PTA_AVX512F | PTA_AVX512CD;
-  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
-  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
-  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
-    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
-    | PTA_FSGSBASE;
-  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
-    | PTA_SGX;
-  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
-    | PTA_GFNI;
-  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
-    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
-
-  static struct pta
-    {
-      const char *const name;		/* processor name or nickname.  */
-      const enum processor_type processor;
-      const enum attr_cpu schedule;
-      const wide_int_bitmask flags;
-    }
-  const processor_alias_table[] =
-    {
-      {"i386", PROCESSOR_I386, CPU_NONE, 0},
-      {"i486", PROCESSOR_I486, CPU_NONE, 0},
-      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
-      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
-      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
-      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
-      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
-      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
-      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
-      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
-      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
-      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
-        PTA_SKYLAKE_AVX512},
-      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
-      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
-	PTA_ICELAKE_CLIENT},
-      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
-	PTA_ICELAKE_SERVER},
-      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
-      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
-      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
-      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
-      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
-      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
-      {"geode", PROCESSOR_GEODE, CPU_GEODE,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
-      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"x86-64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"eden-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nano", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-1000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-2000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-3000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"eden-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"k8", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"k8-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon-fx", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
-	| PTA_XSAVEOPT | PTA_FSGSBASE},
-      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
-	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
-	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
-	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
-	| PTA_MOVBE | PTA_MWAITX},
-      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
-	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
-	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
-	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
-	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
-      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE},
-      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
-	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
-
-      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
-	PTA_64BIT
-	| PTA_HLE /* flags are only used for -march switch.  */ },
-    };
-
   /* -mrecip options.  */
   static struct
     {
@@ -3727,7 +3401,6 @@ ix86_option_override_internal (bool main_args_p,
       { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
     };
 
-  int const pta_size = ARRAY_SIZE (processor_alias_table);
 
   /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
      TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
@@ -4383,7 +4056,7 @@ ix86_option_override_internal (bool main_args_p,
 	}
     }
 
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
@@ -5180,7 +4853,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
   opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
   opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
   opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 2a46fccdec1..e16c6032128 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2277,6 +2277,156 @@ enum processor_type
   PROCESSOR_max
 };
 
+#ifndef IN_LIBGCC2
+/* Processor target table, indexed by processor number */
+struct ptt
+{
+  const char *const name;			/* processor name  */
+
+  /* Default alignments.  */
+  const char *const align_loop;
+  const char *const align_jump;
+  const char *const align_label;
+  const char *const align_func;
+};
+
+extern const struct ptt processor_target_table[PROCESSOR_max];
+
+#include "wide-int-bitmask.h"
+
+const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
+const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
+const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
+const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
+const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
+const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
+const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
+const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
+const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
+const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+/* Hole after PTA_MPX was removed.  */
+const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
+const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
+const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
+const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
+const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
+
+const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+  | PTA_POPCNT;
+const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+  | PTA_XSAVEOPT;
+const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
+  | PTA_RDRND | PTA_F16C;
+const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
+  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+  | PTA_RDSEED;
+const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
+const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_CLWB;
+const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
+const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
+  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
+  | PTA_RDPID | PTA_CLWB;
+const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
+  | PTA_WBNOINVD;
+const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+  | PTA_AVX512F | PTA_AVX512CD;
+const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
+  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
+  | PTA_FSGSBASE;
+const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
+  | PTA_SGX;
+const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
+  | PTA_GFNI;
+const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
+  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
+
+#ifndef GENERATOR_FILE
+
+#include "insn-attr-common.h"
+
+struct pta
+{
+  const char *const name;		/* processor name or nickname.  */
+  const enum processor_type processor;
+  const enum attr_cpu schedule;
+  const wide_int_bitmask flags;
+};
+
+extern const pta processor_alias_table[];
+extern int const pta_size;
+#endif
+
+#endif
+
 extern enum processor_type ix86_tune;
 extern enum processor_type ix86_arch;
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index a40f45ade07..0af48d12544 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
 Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
 @end deftypefn
 
+@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int @var{option_code}, const char *@var{prefix})
+The hook is used for options that have a non-trivial list of possible option values.  OPTION_CODE is option code of opt_code enum type.  PREFIX is used for bash completion and allows an implementation to return more specific completion based on the prefix.  All string values should be allocated from heap memory and consumers should release them.
+@end deftypefn
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 39a214e9b2c..d9dcd325d0b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3669,6 +3669,8 @@ generic code.
 
 @hook TARGET_SUPPORTS_SPLIT_STACK
 
+@hook TARGET_GET_VALID_OPTION_VALUES
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
index 894eea5f37c..c68c9eedaf6 100644
--- a/gcc/opt-suggestions.c
+++ b/gcc/opt-suggestions.c
@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "params.h"
 #include "spellcheck.h"
 #include "opt-suggestions.h"
+#include "common/common-target.h"
 #include "selftest.h"
 
 option_proposer::~option_proposer ()
@@ -38,7 +39,7 @@ option_proposer::suggest_option (const char *bad_opt)
 {
   /* Lazily populate m_option_suggestions.  */
   if (!m_option_suggestions)
-    build_option_suggestions ();
+    build_option_suggestions (NULL);
   gcc_assert (m_option_suggestions);
 
   /* "m_option_suggestions" is now populated.  Use it.  */
@@ -80,7 +81,7 @@ option_proposer::get_completions (const char *option_prefix,
     {
       /* Lazily populate m_option_suggestions.  */
       if (!m_option_suggestions)
-	build_option_suggestions ();
+	build_option_suggestions (option_prefix);
       gcc_assert (m_option_suggestions);
 
       for (unsigned i = 0; i < m_option_suggestions->length (); i++)
@@ -108,7 +109,7 @@ option_proposer::suggest_completion (const char *option_prefix)
 }
 
 void
-option_proposer::build_option_suggestions (void)
+option_proposer::build_option_suggestions (const char *prefix)
 {
   gcc_assert (m_option_suggestions == NULL);
   m_option_suggestions = new auto_string_vec ();
@@ -135,8 +136,27 @@ option_proposer::build_option_suggestions (void)
 		}
 	    }
 	  else
-	    add_misspelling_candidates (m_option_suggestions, option,
-					opt_text);
+	    {
+	      if (option->flags & CL_TARGET)
+		{
+		  vec<const char *> option_values
+		    = targetm_common.get_valid_option_values (i, prefix);
+		  if (!option_values.is_empty ())
+		    {
+		      for (unsigned j = 0; j < option_values.length (); j++)
+			{
+			  char *with_arg = concat (opt_text, option_values[j],
+						   NULL);
+			  add_misspelling_candidates (m_option_suggestions, option,
+						      with_arg);
+			  free (with_arg);
+			}
+		    }
+		}
+	      else
+		add_misspelling_candidates (m_option_suggestions, option,
+					    opt_text);
+	    }
 	  break;
 
 	case OPT_fsanitize_:
diff --git a/gcc/opt-suggestions.h b/gcc/opt-suggestions.h
index 222bafa12cd..eb932779939 100644
--- a/gcc/opt-suggestions.h
+++ b/gcc/opt-suggestions.h
@@ -58,8 +58,10 @@ public:
 private:
   /* Helper function for option_proposer::suggest_option.  Populate
      m_option_suggestions with candidate strings for misspelled options.
-     The strings will be freed by the option_proposer's dtor.  */
-  void build_option_suggestions ();
+     The strings will be freed by the option_proposer's dtor.
+     PREFIX is used for bash completion suggestions, otherwise
+     it's set to NULL.  */
+  void build_option_suggestions (const char *prefix);
 
   /* Find parameter completions for --param format with SEPARATOR.
      Again, save the completions into results.  */
diff --git a/gcc/opts.c b/gcc/opts.c
index a5c9ed9d09d..dc12c2ecefd 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1090,6 +1090,21 @@ wrap_help (const char *help,
   while (remaining);
 }
 
+/* Data structure used to print list of valid option values.  */
+
+struct option_help_tuple
+{
+  option_help_tuple (int code, vec<const char *> values):
+    m_code (code), m_values (values)
+  {}
+
+  /* Code of an option.  */
+  int m_code;
+
+  /* List of possible values.  */
+  vec<const char *> m_values;
+};
+
 /* Print help for a specific front-end, etc.  */
 static void
 print_filtered_help (unsigned int include_flags,
@@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
   if (!opts->x_help_enum_printed)
     opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
 
+  auto_vec<option_help_tuple> help_tuples;
+
   for (i = 0; i < cl_options_count; i++)
     {
       const struct cl_option *option = cl_options + i;
@@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
       if (option->var_type == CLVC_ENUM
 	  && opts->x_help_enum_printed[option->var_enum] != 2)
 	opts->x_help_enum_printed[option->var_enum] = 1;
+      else
+	{
+	  vec<const char *> option_values
+	    = targetm_common.get_valid_option_values (i, NULL);
+	  if (!option_values.is_empty ())
+	    help_tuples.safe_push (option_help_tuple (i, option_values));
+	}
     }
 
   if (! found)
@@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
       printf ("\n\n");
       opts->x_help_enum_printed[i] = 2;
     }
+
+  for (unsigned i = 0; i < help_tuples.length (); i++)
+    {
+      const struct cl_option *option = cl_options + help_tuples[i].m_code;
+      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
+      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
+	printf (" %s", help_tuples[i].m_values[j]);
+      printf ("\n\n");
+    }
 }
 
 /* Display help for a specified type of option.
diff --git a/gcc/testsuite/gcc.dg/completion-4.c b/gcc/testsuite/gcc.dg/completion-4.c
new file mode 100644
index 00000000000..8116811998a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/completion-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-options "--completion=-march=geo" } */
+
+/* { dg-begin-multiline-output "" }
+-march=geode
+   { dg-end-multiline-output "" } */
-- 
2.18.0

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Richard Biener]

On Wed, Aug 29, 2018 at 2:47 PM Martin Liška <mliska@suse.cz> wrote:
>
> On 08/29/2018 01:06 PM, Richard Biener wrote:
> > On Mon, Aug 27, 2018 at 12:00 PM Martin Liška <mliska@suse.cz> wrote:
> >>
> >> On 08/13/2018 03:00 PM, Martin Liška wrote:
> >>> On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
> >>>> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
> >>>>> PING^1
> >>>>>
> >>>>> On 07/24/2018 02:05 PM, Martin Liška wrote:
> >>>>>> Hi.
> >>>>>>
> >>>>>> I'm sending updated version of the patch. It comes up with a new target common hook
> >>>>>> that provide option completion list. It's used both in --help=target and with --completion
> >>>>>> option. I implemented support for -match and -mtune for i386 target.
> >>>>>>
> >>>>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
> >>>>
> >>>>
> >>>> Err I don't maintain the x86 backend to review this effectively. In an
> >>>> ideal world you would have split this into 2 patches 1 for the common
> >>>> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
> >>>> clear what you are looking for here from me :-/
> >>>
> >>> Sorry, I was not clear. I would like to hear from ARM's folks that interface
> >>> design is fine for them? I know a global reviewer will have to approve that.
> >>
> >> I'm CC'ing Jakub and Richard who can help us with the new target hook infrastructure.
> >
> > +vec<const char *>
> > +ix86_get_valid_option_values (int option_code, const char *prefix)
> > +{
> >
> > prefix isn't used - why does that not fail bootstrap?
>
> Will add ATTRIBUTE_UNUSED.
>
>  It requires documentation
> > that honoring prefix isn't required and callers have to deal with
>
> It's more detail described in common-target.def:
>
> 'The hook is used for options that have a non-trivial list of\
>  possible option values.  OPTION_CODE is option code of opt_code\
>  enum type.  PREFIX is used for bash completion and allows an implementation\
>  to return more specific completion based on the prefix.  All string values\
>  should be allocated from heap memory and consumers should release them.'
>
> Should I copy it to the implementation.
>
> > that.  IMHO that
> > makes prefix useless?
>
> ARM folks requested that, they want to do a smart filtering for bash completion.
> It was there request.

Ah, I see.  Based on your x86 example below I guess that generic code already
does prefix handling, yes?  I think that's something that should be documented,
that is, "The result will be pruned to cases with PREFIX if not NULL" or so?

> >
> > Unfortunately option_proposer::build_option_suggestions isn't documented
> > so I don't see whether it only receives target options.  If not then
> >
> > -           add_misspelling_candidates (m_option_suggestions, option,
> > -                                       opt_text);
> > +           {
> > +             vec<const char *> option_values
> > +               = targetm_common.get_valid_option_values (i, prefix);
> > +             if (!option_values.is_empty ())
> >
> > this should be guarded with a check for whether this is a target
> > option (CL_TARGET
> > in flags).
>
> Good point!
>
>  I wonder why misspellings are to be checked for the bash
> > completion case?
>
> Note that option_proposer::build_option_suggestions is shared infrastructure
> in between bash completion and misspellings.
>
> 2 examples:
>
> $ /xgcc -B. -march=znver2 -c /tmp/empty.c
> cc1: error: bad value (‘znver2’) for ‘-march=’ switch
> cc1: note: valid arguments to ‘-march=’ switch are:  ... did you mean ‘znver1’?

Hmm, not very pretty ;)  If you do -march=bdver5, what will it print?
"... did you mean 'bdver1' ... did you mean 'bdver2' ......."?

Anyway, sort that out with David ;)

> $  ./xgcc -B. --completion=-march=znver
> -march=znver1
>
> >
> > I also wonder why those target options could not simply be of Enum type and thus
> > be automatically handled?
>
> What a question, I asked the same one before I implemented that. It's because
> you have modifiers like: -march=armv8.3-a+simd+crypto+nofp for aarch64 target.
> For i386, it's also manually parsed because of tables that group
> options and various values:
>
> processor_target_table
> processor_alias_table

Eh, OK.

> I'm sending updated version of patch that I'm going to test.

The middle-end changes (target hook addition) is OK.

I guess the other non-target parts as well, we can improve over the
prettyness as followup.

Please get target maintainer approval for the rest.

Thanks,
Richard.

> Martin
>
> >
> > Richard.
> >
> >> Martin
> >>
> >>>
> >>> Martin
> >>>
> >>>>
> >>>> Ramana
> >>>>>>
> >>>>>> Martin
> >>>>>>
> >>>>>
> >>>
> >>
>

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Martin Liška]

[-- Attachment #1: Type: text/plain, Size: 5087 bytes --]

On 08/30/2018 12:16 PM, Richard Biener wrote:
> On Wed, Aug 29, 2018 at 2:47 PM Martin Liška <mliska@suse.cz> wrote:
>>
>> On 08/29/2018 01:06 PM, Richard Biener wrote:
>>> On Mon, Aug 27, 2018 at 12:00 PM Martin Liška <mliska@suse.cz> wrote:
>>>>
>>>> On 08/13/2018 03:00 PM, Martin Liška wrote:
>>>>> On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
>>>>>> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
>>>>>>> PING^1
>>>>>>>
>>>>>>> On 07/24/2018 02:05 PM, Martin Liška wrote:
>>>>>>>> Hi.
>>>>>>>>
>>>>>>>> I'm sending updated version of the patch. It comes up with a new target common hook
>>>>>>>> that provide option completion list. It's used both in --help=target and with --completion
>>>>>>>> option. I implemented support for -match and -mtune for i386 target.
>>>>>>>>
>>>>>>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>>>>>>
>>>>>>
>>>>>> Err I don't maintain the x86 backend to review this effectively. In an
>>>>>> ideal world you would have split this into 2 patches 1 for the common
>>>>>> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
>>>>>> clear what you are looking for here from me :-/
>>>>>
>>>>> Sorry, I was not clear. I would like to hear from ARM's folks that interface
>>>>> design is fine for them? I know a global reviewer will have to approve that.
>>>>
>>>> I'm CC'ing Jakub and Richard who can help us with the new target hook infrastructure.
>>>
>>> +vec<const char *>
>>> +ix86_get_valid_option_values (int option_code, const char *prefix)
>>> +{
>>>
>>> prefix isn't used - why does that not fail bootstrap?
>>
>> Will add ATTRIBUTE_UNUSED.
>>
>>  It requires documentation
>>> that honoring prefix isn't required and callers have to deal with
>>
>> It's more detail described in common-target.def:
>>
>> 'The hook is used for options that have a non-trivial list of\
>>  possible option values.  OPTION_CODE is option code of opt_code\
>>  enum type.  PREFIX is used for bash completion and allows an implementation\
>>  to return more specific completion based on the prefix.  All string values\
>>  should be allocated from heap memory and consumers should release them.'
>>
>> Should I copy it to the implementation.
>>
>>> that.  IMHO that
>>> makes prefix useless?
>>
>> ARM folks requested that, they want to do a smart filtering for bash completion.
>> It was there request.
> 
> Ah, I see.  Based on your x86 example below I guess that generic code already
> does prefix handling, yes?  I think that's something that should be documented,
> that is, "The result will be pruned to cases with PREFIX if not NULL" or so?

Done.

> 
>>>
>>> Unfortunately option_proposer::build_option_suggestions isn't documented
>>> so I don't see whether it only receives target options.  If not then
>>>
>>> -           add_misspelling_candidates (m_option_suggestions, option,
>>> -                                       opt_text);
>>> +           {
>>> +             vec<const char *> option_values
>>> +               = targetm_common.get_valid_option_values (i, prefix);
>>> +             if (!option_values.is_empty ())
>>>
>>> this should be guarded with a check for whether this is a target
>>> option (CL_TARGET
>>> in flags).
>>
>> Good point!
>>
>>  I wonder why misspellings are to be checked for the bash
>>> completion case?
>>
>> Note that option_proposer::build_option_suggestions is shared infrastructure
>> in between bash completion and misspellings.
>>
>> 2 examples:
>>
>> $ /xgcc -B. -march=znver2 -c /tmp/empty.c
>> cc1: error: bad value (‘znver2’) for ‘-march=’ switch
>> cc1: note: valid arguments to ‘-march=’ switch are:  ... did you mean ‘znver1’?
> 
> Hmm, not very pretty ;)  If you do -march=bdver5, what will it print?
> "... did you mean 'bdver1' ... did you mean 'bdver2' ......."?

Yep, it's not ideal, I created: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87165

> 
> Anyway, sort that out with David ;)
> 
>> $  ./xgcc -B. --completion=-march=znver
>> -march=znver1
>>
>>>
>>> I also wonder why those target options could not simply be of Enum type and thus
>>> be automatically handled?
>>
>> What a question, I asked the same one before I implemented that. It's because
>> you have modifiers like: -march=armv8.3-a+simd+crypto+nofp for aarch64 target.
>> For i386, it's also manually parsed because of tables that group
>> options and various values:
>>
>> processor_target_table
>> processor_alias_table
> 
> Eh, OK.
> 
>> I'm sending updated version of patch that I'm going to test.
> 
> The middle-end changes (target hook addition) is OK.
> 
> I guess the other non-target parts as well, we can improve over the
> prettyness as followup.
> 
> Please get target maintainer approval for the rest.

Good then, I'm sending final version of the patch that I've justed
tested on x86_64-linux-gnu.

Martin

> 
> Thanks,
> Richard.
> 
>> Martin
>>
>>>
>>> Richard.
>>>
>>>> Martin
>>>>
>>>>>
>>>>> Martin
>>>>>
>>>>>>
>>>>>> Ramana
>>>>>>>>
>>>>>>>> Martin
>>>>>>>>
>>>>>>>
>>>>>
>>>>
>>


[-- Attachment #2: 0001-Come-up-with-TARGET_GET_VALID_OPTION_VALUES-option-h.patch --]
[-- Type: text/x-patch, Size: 56031 bytes --]

From 43c1a5198329b4b800793ab03e8510ec5f4b7d10 Mon Sep 17 00:00:00 2001
From: marxin <mliska@suse.cz>
Date: Fri, 20 Jul 2018 09:58:16 +0200
Subject: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR
 driver/83193).

gcc/ChangeLog:

2018-07-24  Martin Liska  <mliska@suse.cz>

        PR driver/83193
	* common/common-target.def: Add TARGET_GET_VALID_OPTION_VALUES.
	* common/common-targhooks.c (default_get_valid_option_values):
        New function.
	* common/common-targhooks.h (default_get_valid_option_values):
        Likewise.
	* common/config/i386/i386-common.c: Move processor_target_table
        from i386.c.
	(ix86_get_valid_option_values): New function.
	(TARGET_GET_VALID_OPTION_VALUES): New macro.
	* config/i386/i386.c (struct ptt): Move to i386-common.c.
	(PTA_*): Move all defined masks into i386-common.c.
	(ix86_function_specific_restore): Use new processor_cost_table.
	* config/i386/i386.h (struct ptt): Moved from i386.c.
	(struct pta): Likewise.
	* doc/tm.texi: Document new TARGET_GET_VALID_OPTION_VALUES.
	* doc/tm.texi.in: Likewise.
	* opt-suggestions.c (option_proposer::suggest_option):
        Pass prefix to build_option_suggestions.
	(option_proposer::get_completions): Likewise.
	(option_proposer::build_option_suggestions): Use the new target
        hook.
	* opts.c (struct option_help_tuple): New struct.
	(print_filtered_help): Use the new target hook.

gcc/testsuite/ChangeLog:

2018-07-24  Martin Liska  <mliska@suse.cz>

	* gcc.dg/completion-4.c: New test.
---
 gcc/common/common-target.def         |  11 +
 gcc/common/common-targhooks.c        |   9 +
 gcc/common/common-targhooks.h        |   1 +
 gcc/common/config/i386/i386-common.c | 267 +++++++++++++++++
 gcc/config/i386/i386.c               | 413 +++------------------------
 gcc/config/i386/i386.h               | 150 ++++++++++
 gcc/doc/tm.texi                      |   4 +
 gcc/doc/tm.texi.in                   |   2 +
 gcc/opt-suggestions.c                |  30 +-
 gcc/opt-suggestions.h                |   6 +-
 gcc/opts.c                           |  33 +++
 gcc/testsuite/gcc.dg/completion-4.c  |   6 +
 12 files changed, 555 insertions(+), 377 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/completion-4.c

diff --git a/gcc/common/common-target.def b/gcc/common/common-target.def
index e0afbc6af29..019b1e752a9 100644
--- a/gcc/common/common-target.def
+++ b/gcc/common/common-target.def
@@ -80,6 +80,17 @@ DEFHOOK
  bool, (bool report, struct gcc_options *opts),
  hook_bool_bool_gcc_optionsp_false)
 
+DEFHOOK
+(get_valid_option_values,
+"The hook is used for options that have a non-trivial list of\
+ possible option values.  OPTION_CODE is option code of opt_code\
+ enum type.  PREFIX is used for bash completion and allows an implementation\
+ to return more specific completion based on the prefix.  All string values\
+ should be allocated from heap memory and consumers should release them. \
+ The result will be pruned to cases with PREFIX if not NULL.",
+ vec<const char *>, (int option_code, const char *prefix),
+ default_get_valid_option_values)
+
 /* Leave the boolean fields at the end.  */
 
 /* True if unwinding tables should be generated by default.  */
diff --git a/gcc/common/common-targhooks.c b/gcc/common/common-targhooks.c
index b1090190664..747c7da55ca 100644
--- a/gcc/common/common-targhooks.c
+++ b/gcc/common/common-targhooks.c
@@ -23,6 +23,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tm.h"
 #include "common/common-target.h"
 #include "common/common-targhooks.h"
+#include "opts.h"
 
 /* Determine the exception handling mechanism for the target.  */
 
@@ -77,6 +78,14 @@ default_target_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
   return true;
 }
 
+/* Default version of TARGET_GET_VALID_OPTION_VALUES.  */
+
+vec<const char *>
+default_get_valid_option_values (int option_code, const char *prefix)
+{
+  return vec<const char *> ();
+}
+
 const struct default_options empty_optimization_table[] =
   {
     { OPT_LEVELS_NONE, 0, NULL, 0 }
diff --git a/gcc/common/common-targhooks.h b/gcc/common/common-targhooks.h
index d290d7f3e21..4bdf8efdbe6 100644
--- a/gcc/common/common-targhooks.h
+++ b/gcc/common/common-targhooks.h
@@ -28,6 +28,7 @@ extern bool default_target_handle_option (struct gcc_options *,
 					  struct gcc_options *,
 					  const struct cl_decoded_option *,
 					  location_t);
+extern vec<const char *> default_get_valid_option_values (int, const char *);
 
 extern const struct default_options empty_optimization_table[];
 
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 70b3c3f2fc3..1013f82b23d 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1459,4 +1459,271 @@ i386_except_unwind_info (struct gcc_options *opts)
 #undef TARGET_SUPPORTS_SPLIT_STACK
 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
 
+/* This table must be in sync with enum processor_type in i386.h.  */
+const struct ptt processor_target_table[PROCESSOR_max] =
+{
+  /* The "0:0:8" label alignment specified for some processors generates
+     secondary 8-byte alignment only for those label/jump/loop targets
+     which have primary alignment.  */
+
+  {"generic",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"i386",           "4",       "4",       NULL,    "4" },
+  {"i486",           "16",      "16",      "0:0:8", "16"},
+  {"pentium",        "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"lakemont",       "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"pentiumpro",     "16",      "16:11:8", "0:0:8", "16"},
+  {"pentium4",       NULL,      NULL,      NULL,    NULL},
+  {"nocona",         NULL,      NULL,      NULL,    NULL},
+  {"core2",          "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"nehalem",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"sandybridge",    "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"haswell",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"bonnell",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"silvermont",     "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont",       "16",      "16:8:8",  "0:0:8", "16"},
+  {"goldmont-plus",  "16",      "16:8:8",  "0:0:8", "16"},
+  {"tremont",        "16",      "16:8:8",  "0:0:8", "16"},
+  {"knl",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"knm",            "16",      "16:8:8",  "0:0:8", "16"},
+  {"skylake",        "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"skylake-avx512", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"cannonlake",     "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-client", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"icelake-server", "16:11:8", "16:11:8", "0:0:8", "16"},
+  {"intel",          "16",      "16:8:8",  "0:0:8", "16"},
+  {"geode",          NULL,      NULL,      NULL,    NULL},
+  {"k6",             "32:8:8",  "32:8:8",  "0:0:8", "32"},
+  {"athlon",         "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"k8",             "16:8:8",  "16:8:8",  "0:0:8", "16"},
+  {"amdfam10",       "32:25:8", "32:8:8",  "0:0:8", "32"},
+  {"bdver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver3",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"bdver4",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver1",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"btver2",         "16:11:8", "16:8:8",  "0:0:8", "11"},
+  {"znver1",         "16",      "16",      "0:0:8", "16"}
+};
+
+const pta processor_alias_table[] =
+{
+  {"i386", PROCESSOR_I386, CPU_NONE, 0},
+  {"i486", PROCESSOR_I486, CPU_NONE, 0},
+  {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
+  {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
+  {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
+  {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
+  {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+  {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
+  {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+  {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_FXSR},
+  {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+  {"prescott", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nocona", PROCESSOR_NOCONA, CPU_NONE,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
+  {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
+  {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+  {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+  {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_SANDYBRIDGE},
+  {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+    PTA_IVYBRIDGE},
+  {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
+  {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
+  {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
+  {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
+    PTA_SKYLAKE_AVX512},
+  {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
+  {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
+    PTA_ICELAKE_CLIENT},
+  {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
+    PTA_ICELAKE_SERVER},
+  {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+  {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+  {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
+  {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
+  {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
+  {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
+  {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
+  {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+  {"geode", PROCESSOR_GEODE, CPU_GEODE,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
+  {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+  {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+  {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
+    PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+  {"x86-64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"eden-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+  {"nano", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-1000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-2000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_FXSR},
+  {"nano-3000", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x2", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"eden-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"nano-x4", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+  {"k8", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"k8-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"opteron-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+  {"athlon-fx", PROCESSOR_K8, CPU_K8,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
+      | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+  {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
+    PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
+      | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+  {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+  {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
+      | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
+      | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
+      | PTA_XSAVEOPT | PTA_FSGSBASE},
+  {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
+      | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
+      | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
+      | PTA_MOVBE | PTA_MWAITX},
+  {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+      | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+      | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
+      | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
+      | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
+      | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+  {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE},
+  {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
+    PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
+      | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
+      | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
+      | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
+      | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+
+  {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
+    PTA_64BIT
+      | PTA_HLE /* flags are only used for -march switch.  */ },
+};
+
+int const pta_size = ARRAY_SIZE (processor_alias_table);
+
+/* Provide valid option values for -march and -mtune options.  */
+
+vec<const char *>
+ix86_get_valid_option_values (int option_code,
+			      const char *prefix ATTRIBUTE_UNUSED)
+{
+  vec<const char *> v;
+  v.create (0);
+  opt_code opt = (opt_code) option_code;
+
+  switch (opt)
+    {
+    case OPT_march_:
+      for (unsigned i = 0; i < pta_size; i++)
+	v.safe_push (processor_alias_table[i].name);
+      break;
+    case OPT_mtune_:
+      for (unsigned i = 0; i < PROCESSOR_max; i++)
+	v.safe_push (processor_target_table[i].name);
+      break;
+    default:
+      break;
+    }
+
+  return v;
+}
+
+#undef  TARGET_GET_VALID_OPTION_VALUES
+#define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c437c18a29c..48e484b3d62 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -828,63 +828,46 @@ static tree (*ix86_veclib_handler) (combined_fn, tree, tree);
 static tree ix86_veclibabi_svml (combined_fn, tree, tree);
 static tree ix86_veclibabi_acml (combined_fn, tree, tree);
 
-/* Processor target table, indexed by processor number */
-struct ptt
-{
-  const char *const name;			/* processor name  */
-  const struct processor_costs *cost;		/* Processor costs */
-
-  /* Default alignments.  */
-  const char *const align_loop;
-  const char *const align_jump;
-  const char *const align_label;
-  const char *const align_func;
-};
-
 /* This table must be in sync with enum processor_type in i386.h.  */ 
-static const struct ptt processor_target_table[PROCESSOR_max] =
-{
-/* The "0:0:8" label alignment specified for some processors generates
-   secondary 8-byte alignment only for those label/jump/loop targets
-   which have primary alignment.  */
-
-  {"generic",        &generic_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"i386",           &i386_cost,       "4",       "4",       NULL,    "4" },
-  {"i486",           &i486_cost,       "16",      "16",      "0:0:8", "16"},
-  {"pentium",        &pentium_cost,    "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"lakemont",       &lakemont_cost,   "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"pentiumpro",     &pentiumpro_cost, "16",      "16:11:8", "0:0:8", "16"},
-  {"pentium4",       &pentium4_cost,   NULL,      NULL,      NULL,    NULL},
-  {"nocona",         &nocona_cost,     NULL,      NULL,      NULL,    NULL},
-  {"core2",          &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"nehalem",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"sandybridge",    &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"haswell",        &core_cost,       "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"bonnell",        &atom_cost,       "16",      "16:8:8",  "0:0:8", "16"},
-  {"silvermont",     &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont",       &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"goldmont-plus",  &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"tremont",	     &slm_cost,	       "16",	  "16:8:8",  "0:0:8", "16"},
-  {"knl",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"knm",            &slm_cost,        "16",      "16:8:8",  "0:0:8", "16"},
-  {"skylake",        &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"skylake-avx512", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"cannonlake",     &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-client", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"icelake-server", &skylake_cost,    "16:11:8", "16:11:8", "0:0:8", "16"},
-  {"intel",          &intel_cost,      "16",      "16:8:8",  "0:0:8", "16"},
-  {"geode",          &geode_cost,      NULL,      NULL,      NULL,    NULL},
-  {"k6",             &k6_cost,         "32:8:8",  "32:8:8",  "0:0:8", "32"},
-  {"athlon",         &athlon_cost,     "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"k8",             &k8_cost,         "16:8:8",  "16:8:8",  "0:0:8", "16"},
-  {"amdfam10",       &amdfam10_cost,   "32:25:8", "32:8:8",  "0:0:8", "32"},
-  {"bdver1",         &bdver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver2",         &bdver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver3",         &bdver3_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"bdver4",         &bdver4_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver1",         &btver1_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"btver2",         &btver2_cost,     "16:11:8", "16:8:8",  "0:0:8", "11"},
-  {"znver1",         &znver1_cost,     "16",      "16",      "0:0:8", "16"}
+static const struct processor_costs *processor_cost_table[PROCESSOR_max] =
+{
+  &generic_cost,
+  &i386_cost,
+  &i486_cost,
+  &pentium_cost,
+  &lakemont_cost,
+  &pentiumpro_cost,
+  &pentium4_cost,
+  &nocona_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &core_cost,
+  &atom_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &slm_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
+  &intel_cost,
+  &geode_cost,
+  &k6_cost,
+  &athlon_cost,
+  &k8_cost,
+  &amdfam10_cost,
+  &bdver1_cost,
+  &bdver2_cost,
+  &bdver3_cost,
+  &bdver4_cost,
+  &btver1_cost,
+  &btver2_cost,
+  &znver1_cost,
 };
 \f
 static unsigned int
@@ -3386,6 +3369,8 @@ ix86_override_options_after_change (void)
   ix86_default_align (&global_options);
 }
 
+
+
 /* Override various settings based on options.  If MAIN_ARGS_P, the
    options are from the command line, otherwise they are from
    attributes.  Return true if there's an error related to march
@@ -3400,317 +3385,6 @@ ix86_option_override_internal (bool main_args_p,
   unsigned HOST_WIDE_INT ix86_arch_mask;
   const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
 
-  const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
-  const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
-  const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
-  const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
-  const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
-  const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
-  const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
-  const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
-  const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
-  const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
-  const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
-  const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
-  const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
-  const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
-  const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
-  const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
-  const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
-  const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
-  const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
-  const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
-  const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
-  const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
-  const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
-  const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
-  const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
-  const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
-  const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
-  const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
-  const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
-  const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
-  const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
-  const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
-  const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
-  const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
-  const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
-  const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
-  /* Hole after PTA_MPX was removed.  */
-  const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
-  const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
-  const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
-  const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
-  const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
-  const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
-  const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
-  const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
-  const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
-  const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
-  const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
-  const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
-  const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
-  const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
-  const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
-  const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
-  const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
-  const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
-  const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
-  const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
-  const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
-  const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
-  const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
-  const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
-  const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
-  const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
-  const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
-  const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
-  const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
-
-  const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
-    | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
-  const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
-    | PTA_POPCNT;
-  const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
-  const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
-    | PTA_XSAVEOPT;
-  const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
-    | PTA_RDRND | PTA_F16C;
-  const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
-    | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
-  const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
-    | PTA_RDSEED;
-  const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
-    | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
-  const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_CLWB;
-  const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
-    | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
-    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
-  const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
-    | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
-    | PTA_RDPID | PTA_CLWB;
-  const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
-    | PTA_WBNOINVD;
-  const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
-    | PTA_AVX512F | PTA_AVX512CD;
-  const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
-  const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
-  const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
-    | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
-    | PTA_FSGSBASE;
-  const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
-    | PTA_SGX;
-  const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
-    | PTA_GFNI;
-  const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
-    | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
-
-  static struct pta
-    {
-      const char *const name;		/* processor name or nickname.  */
-      const enum processor_type processor;
-      const enum attr_cpu schedule;
-      const wide_int_bitmask flags;
-    }
-  const processor_alias_table[] =
-    {
-      {"i386", PROCESSOR_I386, CPU_NONE, 0},
-      {"i486", PROCESSOR_I486, CPU_NONE, 0},
-      {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
-      {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
-      {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
-      {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
-      {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-        PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
-      {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
-      {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_FXSR},
-      {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
-      {"prescott", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nocona", PROCESSOR_NOCONA, CPU_NONE,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
-      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
-      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
-      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
-      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_SANDYBRIDGE},
-      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
-	PTA_IVYBRIDGE},
-      {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
-      {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
-      {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
-      {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
-        PTA_SKYLAKE_AVX512},
-      {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
-      {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
-	PTA_ICELAKE_CLIENT},
-      {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
-	PTA_ICELAKE_SERVER},
-      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
-      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
-      {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
-      {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
-      {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
-      {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
-      {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
-      {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
-      {"geode", PROCESSOR_GEODE, CPU_GEODE,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
-      {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
-      {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
-      {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
-	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
-      {"x86-64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"eden-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
-      {"nano", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-1000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-2000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_FXSR},
-      {"nano-3000", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x2", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"eden-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"nano-x4", PROCESSOR_K8, CPU_K8,
-        PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
-      {"k8", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"k8-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"opteron-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
-      {"athlon-fx", PROCESSOR_K8, CPU_K8,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
-      {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
-	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
-	| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
-      {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
-      {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
-	| PTA_XSAVEOPT | PTA_FSGSBASE},
-      {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 
-	| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 
-	| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR 
-	| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
-	| PTA_MOVBE | PTA_MWAITX},
-      {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
-	| PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
-	| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
-	| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
-	| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
-      {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE},
-      {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
-	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
-	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
-	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
-
-      {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
-	PTA_64BIT
-	| PTA_HLE /* flags are only used for -march switch.  */ },
-    };
-
   /* -mrecip options.  */
   static struct
     {
@@ -3727,7 +3401,6 @@ ix86_option_override_internal (bool main_args_p,
       { "vec-sqrt",  RECIP_MASK_VEC_SQRT },
     };
 
-  int const pta_size = ARRAY_SIZE (processor_alias_table);
 
   /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
      TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false.  */
@@ -4383,7 +4056,7 @@ ix86_option_override_internal (bool main_args_p,
 	}
     }
 
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
@@ -5180,7 +4853,7 @@ ix86_function_specific_restore (struct gcc_options *opts,
   opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy;
   opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default;
   opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type;
-  ix86_tune_cost = processor_target_table[ix86_tune].cost;
+  ix86_tune_cost = processor_cost_table[ix86_tune];
   /* TODO: ix86_cost should be chosen at instruction or function granuality
      so for cold code we use size_cost even in !optimize_size compilation.  */
   if (opts->x_optimize_size)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 2a46fccdec1..382323d385b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2277,6 +2277,156 @@ enum processor_type
   PROCESSOR_max
 };
 
+#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
+/* Processor target table, indexed by processor number */
+struct ptt
+{
+  const char *const name;			/* processor name  */
+
+  /* Default alignments.  */
+  const char *const align_loop;
+  const char *const align_jump;
+  const char *const align_label;
+  const char *const align_func;
+};
+
+extern const struct ptt processor_target_table[PROCESSOR_max];
+
+#include "wide-int-bitmask.h"
+
+const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
+const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
+const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
+const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
+const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
+const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
+const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
+const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
+const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
+const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+/* Hole after PTA_MPX was removed.  */
+const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
+const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
+const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
+const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
+const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
+const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
+const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
+const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
+const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
+const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
+const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7);
+const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8);
+const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
+
+const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+  | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+  | PTA_POPCNT;
+const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+  | PTA_XSAVEOPT;
+const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
+  | PTA_RDRND | PTA_F16C;
+const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
+  | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+  | PTA_RDSEED;
+const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+  | PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
+const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_CLWB;
+const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
+  | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+  | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
+const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
+  | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
+  | PTA_RDPID | PTA_CLWB;
+const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
+  | PTA_WBNOINVD;
+const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+  | PTA_AVX512F | PTA_AVX512CD;
+const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
+  | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
+  | PTA_FSGSBASE;
+const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
+  | PTA_SGX;
+const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
+  | PTA_GFNI;
+const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
+  | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
+
+#ifndef GENERATOR_FILE
+
+#include "insn-attr-common.h"
+
+struct pta
+{
+  const char *const name;		/* processor name or nickname.  */
+  const enum processor_type processor;
+  const enum attr_cpu schedule;
+  const wide_int_bitmask flags;
+};
+
+extern const pta processor_alias_table[];
+extern int const pta_size;
+#endif
+
+#endif
+
 extern enum processor_type ix86_tune;
 extern enum processor_type ix86_arch;
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index a40f45ade07..e9ed35dc649 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5057,6 +5057,10 @@ Returns true if the target wants GCC's default stack protect runtime support, ot
 Whether this target supports splitting the stack when the options described in @var{opts} have been passed.  This is called after options have been parsed, so the target may reject splitting the stack in some configurations.  The default version of this hook returns false.  If @var{report} is true, this function may issue a warning or error; if @var{report} is false, it must simply return a value
 @end deftypefn
 
+@deftypefn {Common Target Hook} {vec<const char *>} TARGET_GET_VALID_OPTION_VALUES (int @var{option_code}, const char *@var{prefix})
+The hook is used for options that have a non-trivial list of possible option values.  OPTION_CODE is option code of opt_code enum type.  PREFIX is used for bash completion and allows an implementation to return more specific completion based on the prefix.  All string values should be allocated from heap memory and consumers should release them.  The result will be pruned to cases with PREFIX if not NULL.
+@end deftypefn
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 39a214e9b2c..d9dcd325d0b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3669,6 +3669,8 @@ generic code.
 
 @hook TARGET_SUPPORTS_SPLIT_STACK
 
+@hook TARGET_GET_VALID_OPTION_VALUES
+
 @node Miscellaneous Register Hooks
 @subsection Miscellaneous register hooks
 @cindex miscellaneous register hooks
diff --git a/gcc/opt-suggestions.c b/gcc/opt-suggestions.c
index 894eea5f37c..c68c9eedaf6 100644
--- a/gcc/opt-suggestions.c
+++ b/gcc/opt-suggestions.c
@@ -26,6 +26,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "params.h"
 #include "spellcheck.h"
 #include "opt-suggestions.h"
+#include "common/common-target.h"
 #include "selftest.h"
 
 option_proposer::~option_proposer ()
@@ -38,7 +39,7 @@ option_proposer::suggest_option (const char *bad_opt)
 {
   /* Lazily populate m_option_suggestions.  */
   if (!m_option_suggestions)
-    build_option_suggestions ();
+    build_option_suggestions (NULL);
   gcc_assert (m_option_suggestions);
 
   /* "m_option_suggestions" is now populated.  Use it.  */
@@ -80,7 +81,7 @@ option_proposer::get_completions (const char *option_prefix,
     {
       /* Lazily populate m_option_suggestions.  */
       if (!m_option_suggestions)
-	build_option_suggestions ();
+	build_option_suggestions (option_prefix);
       gcc_assert (m_option_suggestions);
 
       for (unsigned i = 0; i < m_option_suggestions->length (); i++)
@@ -108,7 +109,7 @@ option_proposer::suggest_completion (const char *option_prefix)
 }
 
 void
-option_proposer::build_option_suggestions (void)
+option_proposer::build_option_suggestions (const char *prefix)
 {
   gcc_assert (m_option_suggestions == NULL);
   m_option_suggestions = new auto_string_vec ();
@@ -135,8 +136,27 @@ option_proposer::build_option_suggestions (void)
 		}
 	    }
 	  else
-	    add_misspelling_candidates (m_option_suggestions, option,
-					opt_text);
+	    {
+	      if (option->flags & CL_TARGET)
+		{
+		  vec<const char *> option_values
+		    = targetm_common.get_valid_option_values (i, prefix);
+		  if (!option_values.is_empty ())
+		    {
+		      for (unsigned j = 0; j < option_values.length (); j++)
+			{
+			  char *with_arg = concat (opt_text, option_values[j],
+						   NULL);
+			  add_misspelling_candidates (m_option_suggestions, option,
+						      with_arg);
+			  free (with_arg);
+			}
+		    }
+		}
+	      else
+		add_misspelling_candidates (m_option_suggestions, option,
+					    opt_text);
+	    }
 	  break;
 
 	case OPT_fsanitize_:
diff --git a/gcc/opt-suggestions.h b/gcc/opt-suggestions.h
index 222bafa12cd..eb932779939 100644
--- a/gcc/opt-suggestions.h
+++ b/gcc/opt-suggestions.h
@@ -58,8 +58,10 @@ public:
 private:
   /* Helper function for option_proposer::suggest_option.  Populate
      m_option_suggestions with candidate strings for misspelled options.
-     The strings will be freed by the option_proposer's dtor.  */
-  void build_option_suggestions ();
+     The strings will be freed by the option_proposer's dtor.
+     PREFIX is used for bash completion suggestions, otherwise
+     it's set to NULL.  */
+  void build_option_suggestions (const char *prefix);
 
   /* Find parameter completions for --param format with SEPARATOR.
      Again, save the completions into results.  */
diff --git a/gcc/opts.c b/gcc/opts.c
index a5c9ed9d09d..dc12c2ecefd 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -1090,6 +1090,21 @@ wrap_help (const char *help,
   while (remaining);
 }
 
+/* Data structure used to print list of valid option values.  */
+
+struct option_help_tuple
+{
+  option_help_tuple (int code, vec<const char *> values):
+    m_code (code), m_values (values)
+  {}
+
+  /* Code of an option.  */
+  int m_code;
+
+  /* List of possible values.  */
+  vec<const char *> m_values;
+};
+
 /* Print help for a specific front-end, etc.  */
 static void
 print_filtered_help (unsigned int include_flags,
@@ -1143,6 +1158,8 @@ print_filtered_help (unsigned int include_flags,
   if (!opts->x_help_enum_printed)
     opts->x_help_enum_printed = XCNEWVAR (char, cl_enums_count);
 
+  auto_vec<option_help_tuple> help_tuples;
+
   for (i = 0; i < cl_options_count; i++)
     {
       const struct cl_option *option = cl_options + i;
@@ -1303,6 +1320,13 @@ print_filtered_help (unsigned int include_flags,
       if (option->var_type == CLVC_ENUM
 	  && opts->x_help_enum_printed[option->var_enum] != 2)
 	opts->x_help_enum_printed[option->var_enum] = 1;
+      else
+	{
+	  vec<const char *> option_values
+	    = targetm_common.get_valid_option_values (i, NULL);
+	  if (!option_values.is_empty ())
+	    help_tuples.safe_push (option_help_tuple (i, option_values));
+	}
     }
 
   if (! found)
@@ -1366,6 +1390,15 @@ print_filtered_help (unsigned int include_flags,
       printf ("\n\n");
       opts->x_help_enum_printed[i] = 2;
     }
+
+  for (unsigned i = 0; i < help_tuples.length (); i++)
+    {
+      const struct cl_option *option = cl_options + help_tuples[i].m_code;
+      printf ("  Known valid arguments for %s option:\n   ", option->opt_text);
+      for (unsigned j = 0; j < help_tuples[i].m_values.length (); j++)
+	printf (" %s", help_tuples[i].m_values[j]);
+      printf ("\n\n");
+    }
 }
 
 /* Display help for a specified type of option.
diff --git a/gcc/testsuite/gcc.dg/completion-4.c b/gcc/testsuite/gcc.dg/completion-4.c
new file mode 100644
index 00000000000..8116811998a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/completion-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-options "--completion=-march=geo" } */
+
+/* { dg-begin-multiline-output "" }
+-march=geode
+   { dg-end-multiline-output "" } */
-- 
2.18.0

Re: [PATCH] Come up with TARGET_GET_VALID_OPTION_VALUES option hook (PR driver/83193).

[Martin Liška]

On 08/31/2018 11:29 AM, Martin Liška wrote:
> On 08/30/2018 12:16 PM, Richard Biener wrote:
>> On Wed, Aug 29, 2018 at 2:47 PM Martin Liška <mliska@suse.cz> wrote:
>>>
>>> On 08/29/2018 01:06 PM, Richard Biener wrote:
>>>> On Mon, Aug 27, 2018 at 12:00 PM Martin Liška <mliska@suse.cz> wrote:
>>>>>
>>>>> On 08/13/2018 03:00 PM, Martin Liška wrote:
>>>>>> On 08/13/2018 02:54 PM, Ramana Radhakrishnan wrote:
>>>>>>> On Mon, Aug 13, 2018 at 1:49 PM, Martin Liška <mliska@suse.cz> wrote:
>>>>>>>> PING^1
>>>>>>>>
>>>>>>>> On 07/24/2018 02:05 PM, Martin Liška wrote:
>>>>>>>>> Hi.
>>>>>>>>>
>>>>>>>>> I'm sending updated version of the patch. It comes up with a new target common hook
>>>>>>>>> that provide option completion list. It's used both in --help=target and with --completion
>>>>>>>>> option. I implemented support for -match and -mtune for i386 target.
>>>>>>>>>
>>>>>>>>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>>>>>>>
>>>>>>>
>>>>>>> Err I don't maintain the x86 backend to review this effectively. In an
>>>>>>> ideal world you would have split this into 2 patches 1 for the common
>>>>>>> parts and 1 for x86 and CC'd the relevant x86 maintainers. I'm not
>>>>>>> clear what you are looking for here from me :-/
>>>>>>
>>>>>> Sorry, I was not clear. I would like to hear from ARM's folks that interface
>>>>>> design is fine for them? I know a global reviewer will have to approve that.
>>>>>
>>>>> I'm CC'ing Jakub and Richard who can help us with the new target hook infrastructure.
>>>>
>>>> +vec<const char *>
>>>> +ix86_get_valid_option_values (int option_code, const char *prefix)
>>>> +{
>>>>
>>>> prefix isn't used - why does that not fail bootstrap?
>>>
>>> Will add ATTRIBUTE_UNUSED.
>>>
>>>  It requires documentation
>>>> that honoring prefix isn't required and callers have to deal with
>>>
>>> It's more detail described in common-target.def:
>>>
>>> 'The hook is used for options that have a non-trivial list of\
>>>  possible option values.  OPTION_CODE is option code of opt_code\
>>>  enum type.  PREFIX is used for bash completion and allows an implementation\
>>>  to return more specific completion based on the prefix.  All string values\
>>>  should be allocated from heap memory and consumers should release them.'
>>>
>>> Should I copy it to the implementation.
>>>
>>>> that.  IMHO that
>>>> makes prefix useless?
>>>
>>> ARM folks requested that, they want to do a smart filtering for bash completion.
>>> It was there request.
>>
>> Ah, I see.  Based on your x86 example below I guess that generic code already
>> does prefix handling, yes?  I think that's something that should be documented,
>> that is, "The result will be pruned to cases with PREFIX if not NULL" or so?
> 
> Done.
> 
>>
>>>>
>>>> Unfortunately option_proposer::build_option_suggestions isn't documented
>>>> so I don't see whether it only receives target options.  If not then
>>>>
>>>> -           add_misspelling_candidates (m_option_suggestions, option,
>>>> -                                       opt_text);
>>>> +           {
>>>> +             vec<const char *> option_values
>>>> +               = targetm_common.get_valid_option_values (i, prefix);
>>>> +             if (!option_values.is_empty ())
>>>>
>>>> this should be guarded with a check for whether this is a target
>>>> option (CL_TARGET
>>>> in flags).
>>>
>>> Good point!
>>>
>>>  I wonder why misspellings are to be checked for the bash
>>>> completion case?
>>>
>>> Note that option_proposer::build_option_suggestions is shared infrastructure
>>> in between bash completion and misspellings.
>>>
>>> 2 examples:
>>>
>>> $ /xgcc -B. -march=znver2 -c /tmp/empty.c
>>> cc1: error: bad value (‘znver2’) for ‘-march=’ switch
>>> cc1: note: valid arguments to ‘-march=’ switch are:  ... did you mean ‘znver1’?
>>
>> Hmm, not very pretty ;)  If you do -march=bdver5, what will it print?
>> "... did you mean 'bdver1' ... did you mean 'bdver2' ......."?
> 
> Yep, it's not ideal, I created: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87165
> 
>>
>> Anyway, sort that out with David ;)
>>
>>> $  ./xgcc -B. --completion=-march=znver
>>> -march=znver1
>>>
>>>>
>>>> I also wonder why those target options could not simply be of Enum type and thus
>>>> be automatically handled?
>>>
>>> What a question, I asked the same one before I implemented that. It's because
>>> you have modifiers like: -march=armv8.3-a+simd+crypto+nofp for aarch64 target.
>>> For i386, it's also manually parsed because of tables that group
>>> options and various values:
>>>
>>> processor_target_table
>>> processor_alias_table
>>
>> Eh, OK.
>>
>>> I'm sending updated version of patch that I'm going to test.
>>
>> The middle-end changes (target hook addition) is OK.
>>
>> I guess the other non-target parts as well, we can improve over the
>> prettyness as followup.
>>
>> Please get target maintainer approval for the rest.
> 
> Good then, I'm sending final version of the patch that I've justed
> tested on x86_64-linux-gnu.

I was given offline approval from Honza about the i386-specific part.
I'm going to install that.

Martin

> 
> Martin
> 
>>
>> Thanks,
>> Richard.
>>
>>> Martin
>>>
>>>>
>>>> Richard.
>>>>
>>>>> Martin
>>>>>
>>>>>>
>>>>>> Martin
>>>>>>
>>>>>>>
>>>>>>> Ramana
>>>>>>>>>
>>>>>>>>> Martin
>>>>>>>>>
>>>>>>>>
>>>>>>
>>>>>
>>>
>