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From: will schmidt To: Carl Love , segher@gcc.gnu.org, dje.gcc@gmail.com, gcc-patches@gcc.gnu.org Date: Thu, 24 Sep 2020 13:21:49 -0500 In-Reply-To: <796ff1e7e6ddfb8b6d2618217054fe2e50597c83.camel@us.ibm.com> References: <815d6b091f4b8bf3ab7c7e203c41d03c6c0e8d81.camel@us.ibm.com> <796ff1e7e6ddfb8b6d2618217054fe2e50597c83.camel@us.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-24_11:2020-09-24, 2020-09-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=4 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 bulkscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009240130 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Sep 2020 18:21:56 -0000 On Mon, 2020-09-21 at 16:56 -0700, Carl Love wrote: > Segher, Will: > > Patch 4 adds the vector 128-bit integer shift instruction support for > the V1TI type. > > The following changes were made from the previous version. > > Renamed VSX_TI to VEC_TI, put def in vector.md. Didn't get it > separated into a different patch. > > Reworked the XXSWAPD_V1TI to not use UNSPEC. > > Test suite program cleanups, removed "//" comments that were not > needed. > > The patch has been tested on > > powerpc64le-unknown-linux-gnu (Power 9 LE) > > with no regression errors. > > The P10 test was run by hand on Mambo. > > > Carl Love > > ------------------------------------------------------ > > > gcc/ChangeLog > > 2020-09-21 Carl Love > * config/rs6000/altivec.md (altivec_vslq, altivec_vsrq): > Rename altivec_vslq_, altivec_vsrq_, mode VEC_TI. Nit "Rename to" > * config/rs6000/vector.md (VEC_TI): New mode iterator. > (vashlv1ti3): Change to vashl3, mode VEC_TI. > (vlshrv1ti3): Change to vlshr3, mode VEC_TI. s/Change/Rename to/ 'New' isn't quite right for the mode iterator, since it's renamed from the VSX_TI iterator. perhaps something like * config/rs6000/vector.md (VEC_TI): New name for VSX_TI iterator from vsx.md. > * config/rs6000/vsx.md (VSX_TI): Remove define_mode_iterator. > (VSX_TI): Renamed VEC_TI. Just the Remove. VEC_TI doesn't exist in vsx.md. > > gcc/testsuite/ChangeLog > > 2020-09-21 Carl Love > gcc.target/powerpc/int_128bit-runnable.c: Add shift_right, > shift_left > tests. > --- > gcc/config/rs6000/altivec.md | 16 ++++----- > gcc/config/rs6000/vector.md | 27 ++++++++------- > gcc/config/rs6000/vsx.md | 33 +++++++++------ > ---- > .../gcc.target/powerpc/int_128bit-runnable.c | 16 +++++++-- > 4 files changed, 52 insertions(+), 40 deletions(-) > > diff --git a/gcc/config/rs6000/altivec.md > b/gcc/config/rs6000/altivec.md > index 34a4731342a..5db3de3cc9f 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -2219,10 +2219,10 @@ > "vsl %0,%1,%2" > [(set_attr "type" "vecsimple")]) > > -(define_insn "altivec_vslq" > - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") > - (ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") > - (match_operand:V1TI 2 "vsx_register_operand" > "v")))] > +(define_insn "altivec_vslq_" > + [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") > + (ashift:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand" > "v") > + (match_operand:VEC_TI 2 "vsx_register_operand" > "v")))] > "TARGET_POWER10" > /* Shift amount in needs to be in bits[57:63] of 128-bit operand. > */ > "vslq %0,%1,%2" > @@ -2236,10 +2236,10 @@ > "vsr %0,%1,%2" > [(set_attr "type" "vecsimple")]) > > -(define_insn "altivec_vsrq" > - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") > - (lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" > "v") > - (match_operand:V1TI 2 "vsx_register_operand" > "v")))] > +(define_insn "altivec_vsrq_" > + [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") > + (lshiftrt:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand" > "v") > + (match_operand:VEC_TI 2 > "vsx_register_operand" "v")))] > "TARGET_POWER10" > /* Shift amount in needs to be in bits[57:63] of 128-bit operand. > */ > "vsrq %0,%1,%2" > diff --git a/gcc/config/rs6000/vector.md > b/gcc/config/rs6000/vector.md > index 0cca4232619..3ea3a91845a 100644 > --- a/gcc/config/rs6000/vector.md > +++ b/gcc/config/rs6000/vector.md > @@ -26,6 +26,9 @@ > ;; Vector int modes > (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI]) > > +;; 128-bit int modes > +(define_mode_iterator VEC_TI [V1TI TI]) > + > ;; Vector int modes for parity > (define_mode_iterator VEC_IP [V8HI > V4SI > @@ -1627,17 +1630,17 @@ > "") > > ;; No immediate version of this 128-bit instruction > -(define_expand "vashlv1ti3" > - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") > - (ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") > - (match_operand:V1TI 2 "vsx_register_operand" > "v")))] > +(define_expand "vashl3" > + [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") > + (ashift:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand") > + (match_operand:VEC_TI 2 > "vsx_register_operand")))] > "TARGET_POWER10" > { > /* Shift amount in needs to be put in bits[57:63] of 128-bit > operand2. */ > - rtx tmp = gen_reg_rtx (V1TImode); > + rtx tmp = gen_reg_rtx (mode); > > emit_insn(gen_xxswapd_v1ti (tmp, operands[2])); > - emit_insn(gen_altivec_vslq (operands[0], operands[1], tmp)); > + emit_insn(gen_altivec_vslq_ (operands[0], operands[1], > tmp)); > DONE; > }) > > @@ -1650,17 +1653,17 @@ > "") > > ;; No immediate version of this 128-bit instruction > -(define_expand "vlshrv1ti3" > - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") > - (lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" > "v") > - (match_operand:V1TI 2 "vsx_register_operand" > "v")))] > +(define_expand "vlshr3" > + [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") > + (lshiftrt:VEC_TI (match_operand:VEC_TI 1 > "vsx_register_operand") > + (match_operand:VEC_TI 2 > "vsx_register_operand")))] > "TARGET_POWER10" > { > /* Shift amount in needs to be put into bits[57:63] of 128-bit > operand2. */ > - rtx tmp = gen_reg_rtx (V1TImode); > + rtx tmp = gen_reg_rtx (mode); > > emit_insn(gen_xxswapd_v1ti (tmp, operands[2])); > - emit_insn(gen_altivec_vsrq (operands[0], operands[1], tmp)); > + emit_insn(gen_altivec_vsrq_ (operands[0], operands[1], > tmp)); > DONE; > }) > > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 5b6a0bd728a..87f96ffcc4c 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -37,9 +37,6 @@ > TI > V1TI]) > > -;; Iterator for 128-bit integer types that go in a single vector > register. > -(define_mode_iterator VSX_TI [TI V1TI]) > - > ;; Iterator for the 2 32-bit vector types > (define_mode_iterator VSX_W [V4SF V4SI]) > > @@ -944,9 +941,9 @@ > ;; special V1TI container class, which it is not appropriate to use > vec_select > ;; for the type. > (define_insn "*vsx_le_permute_" > - [(set (match_operand:VSX_TI 0 "nonimmediate_operand" > "=wa,wa,Z,&r,&r,Q") > - (rotate:VSX_TI > - (match_operand:VSX_TI 1 "input_operand" "wa,Z,wa,r,Q,r") > + [(set (match_operand:VEC_TI 0 "nonimmediate_operand" > "=wa,wa,Z,&r,&r,Q") > + (rotate:VEC_TI > + (match_operand:VEC_TI 1 "input_operand" "wa,Z,wa,r,Q,r") > (const_int 64)))] > "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" > "@ > @@ -960,10 +957,10 @@ > (set_attr "type" "vecperm,vecload,vecstore,*,load,store")]) > > (define_insn_and_split "*vsx_le_undo_permute_" > - [(set (match_operand:VSX_TI 0 "vsx_register_operand" "=wa,wa") > - (rotate:VSX_TI > - (rotate:VSX_TI > - (match_operand:VSX_TI 1 "vsx_register_operand" "0,wa") > + [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=wa,wa") > + (rotate:VEC_TI > + (rotate:VEC_TI > + (match_operand:VEC_TI 1 "vsx_register_operand" "0,wa") > (const_int 64)) > (const_int 64)))] > "!BYTES_BIG_ENDIAN && TARGET_VSX" > @@ -1031,11 +1028,11 @@ > ;; Peepholes to catch loads and stores for TImode if TImode landed > in > ;; GPR registers on a little endian system. > (define_peephole2 > - [(set (match_operand:VSX_TI 0 "int_reg_operand") > - (rotate:VSX_TI (match_operand:VSX_TI 1 "memory_operand") > + [(set (match_operand:VEC_TI 0 "int_reg_operand") > + (rotate:VEC_TI (match_operand:VEC_TI 1 "memory_operand") > (const_int 64))) > - (set (match_operand:VSX_TI 2 "int_reg_operand") > - (rotate:VSX_TI (match_dup 0) > + (set (match_operand:VEC_TI 2 "int_reg_operand") > + (rotate:VEC_TI (match_dup 0) > (const_int 64)))] > "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR > && (rtx_equal_p (operands[0], operands[2]) > @@ -1043,11 +1040,11 @@ > [(set (match_dup 2) (match_dup 1))]) > > (define_peephole2 > - [(set (match_operand:VSX_TI 0 "int_reg_operand") > - (rotate:VSX_TI (match_operand:VSX_TI 1 "int_reg_operand") > + [(set (match_operand:VEC_TI 0 "int_reg_operand") > + (rotate:VEC_TI (match_operand:VEC_TI 1 "int_reg_operand") > (const_int 64))) > - (set (match_operand:VSX_TI 2 "memory_operand") > - (rotate:VSX_TI (match_dup 0) > + (set (match_operand:VEC_TI 2 "memory_operand") > + (rotate:VEC_TI (match_dup 0) > (const_int 64)))] > "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR > && peep2_reg_dead_p (2, operands[0])" > diff --git a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c > b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c > index ec3dcf3dff1..25e2c9d1af4 100644 > --- a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c > +++ b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c > @@ -53,6 +53,18 @@ void print_i128(__int128_t val) > > void abort (void); > > +__attribute__((noinline)) > +__int128_t shift_right (__int128_t a, __uint128_t b) > +{ > + return a >> b; > +} > + > +__attribute__((noinline)) > +__int128_t shift_left (__int128_t a, __uint128_t b) > +{ > + return a << b; > +} > + > int main () > { > int i, result_int; > @@ -141,7 +153,7 @@ int main () > #endif > } > > - arg1 = 3; > + arg1 = vec_result[0]; > uarg2 = 4; > expected_result = arg1*16; > > @@ -225,7 +237,7 @@ int main () > #endif > } > > - arg1 = 48; > + arg1 = vec_uresult[0]; > uarg2 = 4; > expected_result = arg1/16; >