From: Andrew Stubbs <ams@codesourcery.com>
To: Richard Biener via Gcc-patches <gcc-patches@gcc.gnu.org>,
Richard Biener <richard.guenther@gmail.com>,
<juzhe.zhong@rivai.ai>, <richard.sandiford@arm.com>
Subject: Re: [PATCH] vect: while_ult for integer mask
Date: Thu, 29 Sep 2022 10:56:57 +0100 [thread overview]
Message-ID: <b2a02435-04c7-cb06-5749-4ea05c0688ee@codesourcery.com> (raw)
In-Reply-To: <mptfsgav8gw.fsf@arm.com>
On 29/09/2022 10:24, Richard Sandiford wrote:
> Otherwise:
>
> operand0[0] = operand1 < operand2;
> for (i = 1; i < operand3; i++)
> operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
>
> looks like a "length and mask" operation, which IIUC is also what
> RVV wanted? (Wasn't at the Cauldron, so not entirely sure.)
>
> Perhaps the difference is that in this case the length must be constant.
> (Or is that true for RVV as well?)
I too saw that presentation and I have compared notes with Juzhe before
posting this.
As he has posted, what they want is different because their config
register has an explicit length field whereas GCN just uses a mask to
limit the length (more like AArch64, I think).
The RVV solution uses different logic in the gimple IR; this proposal is
indistinguishable from the status quo at that point.
Andrew
next prev parent reply other threads:[~2022-09-29 9:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-28 15:05 Andrew Stubbs
2022-09-29 7:52 ` Richard Biener
2022-09-29 9:24 ` Richard Sandiford
2022-09-29 9:37 ` Richard Biener
2022-09-29 9:38 ` juzhe.zhong
2022-09-29 9:56 ` Andrew Stubbs [this message]
2022-09-29 10:17 ` Richard Sandiford
2022-09-29 13:46 ` Richard Biener
2022-10-03 14:27 ` Andrew Stubbs
2022-09-29 9:50 ` Andrew Stubbs
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