From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98173 invoked by alias); 8 Jul 2019 09:06:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 98157 invoked by uid 89); 8 Jul 2019 09:06:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_NUMSUBJECT,KAM_SHORT autolearn=ham version=3.3.1 spammy=opportunity X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 08 Jul 2019 09:06:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7D21360; Mon, 8 Jul 2019 02:06:00 -0700 (PDT) Received: from [10.2.206.47] (e120808-lin.cambridge.arm.com [10.2.206.47]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5C35A3F246; Mon, 8 Jul 2019 02:06:00 -0700 (PDT) Subject: Re: [PATCH][armeb] PR 91060 gcc.c-torture/execute/scal-to-vec1.c fails since r272843 To: Christophe Lyon , gcc Patches , Richard Biener , Richard Sandiford References: From: Kyrill Tkachov Message-ID: Date: Mon, 08 Jul 2019 09:09:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2019-07/txt/msg00554.txt.bz2 Hi Christophe On 7/8/19 10:01 AM, Christophe Lyon wrote: > Hi, > > This patch fixes PR 91060 where the lane ordering was no longer the > right one (GCC's vs architecture's). > > OK? > > Thanks to both Richards for most of the debugging! Thank you to all for tracking this down. > > Christophe pr91060.patch.txt diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 820502a..4c7b5a8 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -12471,7 +12471,7 @@ neon_expand_vector_init (rtx target, rtx vals) if (n_var == 1) { rtx copy = copy_rtx (vals); - rtx index = GEN_INT (one_var); + rtx index = GEN_INT (1 << one_var); /* Load constant part of vector, substitute neighboring value for varying element. */ @@ -12483,31 +12483,31 @@ neon_expand_vector_init (rtx target, rtx vals) switch (mode) { case E_V8QImode: - emit_insn (gen_neon_vset_lanev8qi (target, x, target, index)); + emit_insn (gen_vec_setv8qi_internal (target, x, index, target)); break; case E_V16QImode: - emit_insn (gen_neon_vset_lanev16qi (target, x, target, index)); + emit_insn (gen_vec_setv16qi_internal (target, x, index, target)); break; case E_V4HImode: - emit_insn (gen_neon_vset_lanev4hi (target, x, target, index)); + emit_insn (gen_vec_setv4hi_internal (target, x, index, target)); break; case E_V8HImode: - emit_insn (gen_neon_vset_lanev8hi (target, x, target, index)); + emit_insn (gen_vec_setv8hi_internal (target, x, index, target)); break; case E_V2SImode: - emit_insn (gen_neon_vset_lanev2si (target, x, target, index)); + emit_insn (gen_vec_setv2si_internal (target, x, index, target)); break; case E_V4SImode: - emit_insn (gen_neon_vset_lanev4si (target, x, target, index)); + emit_insn (gen_vec_setv4si_internal (target, x, index, target)); break; case E_V2SFmode: - emit_insn (gen_neon_vset_lanev2sf (target, x, target, index)); + emit_insn (gen_vec_setv2sf_internal (target, x, index, target)); break; case E_V4SFmode: - emit_insn (gen_neon_vset_lanev4sf (target, x, target, index)); + emit_insn (gen_vec_setv4sf_internal (target, x, index, target)); break; case E_V2DImode: - emit_insn (gen_neon_vset_lanev2di (target, x, target, index)); + emit_insn (gen_vec_setv2di_internal (target, x, index, target)); break; default: gcc_unreachable (); Can we take the opportunity here to remove that switch statement and use the parametrised names machinery: https://gcc.gnu.org/onlinedocs/gccint/Parameterized-Names.html#Parameterized-Names so that we can instead have one call to gen_vec_setv8hi_internal (mode, target, x, merge_mask, target) or something. Thanks, Kyrill