* [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5
@ 2017-03-23 16:03 Thomas Preudhomme
2017-03-23 16:10 ` Richard Earnshaw (lists)
0 siblings, 1 reply; 9+ messages in thread
From: Thomas Preudhomme @ 2017-03-23 16:03 UTC (permalink / raw)
To: Kyrill Tkachov, Ramana Radhakrishnan, Richard Earnshaw, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 544 bytes --]
Hi,
gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
not test the changed code since ARMv7-R does not have division
instructions in ARM state. This patch changes it to target Cortex-R5
processor instead which does have division instructions in ARM state.
ChangeLog entry is as follows:
*** gcc/testsuite/ChangeLog ***
2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
PR target/80082
* gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
ARMv7-R.
Is this ok for stage4?
Best regards,
Thomas
[-- Attachment #2: atomic_loaddi_11_cortexr5.patch --]
[-- Type: text/x-patch, Size: 550 bytes --]
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
index 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b 100644
--- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -1,7 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v7r_ok } */
-/* { dg-options "-O2" } */
-/* { dg-add-options arm_arch_v7r } */
+/* { dg-options "-O2 -mcpu=cortex-r5" } */
#include <stdatomic.h>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5
2017-03-23 16:03 [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5 Thomas Preudhomme
@ 2017-03-23 16:10 ` Richard Earnshaw (lists)
2017-03-23 16:19 ` Thomas Preudhomme
0 siblings, 1 reply; 9+ messages in thread
From: Richard Earnshaw (lists) @ 2017-03-23 16:10 UTC (permalink / raw)
To: Thomas Preudhomme, Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
On 23/03/17 16:02, Thomas Preudhomme wrote:
> Hi,
>
> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
> not test the changed code since ARMv7-R does not have division
> instructions in ARM state. This patch changes it to target Cortex-R5
> processor instead which does have division instructions in ARM state.
>
> ChangeLog entry is as follows:
>
> *** gcc/testsuite/ChangeLog ***
>
> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>
> PR target/80082
> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
> ARMv7-R.
>
> Is this ok for stage4?
>
> Best regards,
>
> Thomas
>
> atomic_loaddi_11_cortexr5.patch
>
>
> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
> index 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b 100644
> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
> @@ -1,7 +1,6 @@
> /* { dg-do compile } */
> /* { dg-require-effective-target arm_arch_v7r_ok } */
> -/* { dg-options "-O2" } */
> -/* { dg-add-options arm_arch_v7r } */
> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>
> #include <stdatomic.h>
>
>
Will that work properly if doing multilib testing with a specific CPU
target?
R.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5
2017-03-23 16:10 ` Richard Earnshaw (lists)
@ 2017-03-23 16:19 ` Thomas Preudhomme
2017-03-23 16:53 ` Thomas Preudhomme
0 siblings, 1 reply; 9+ messages in thread
From: Thomas Preudhomme @ 2017-03-23 16:19 UTC (permalink / raw)
To: Richard Earnshaw (lists),
Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
Mmmh I probably need to add a dg-skip-if in there. Will respin the patch.
Best regards,
Thomas
On 23/03/17 16:10, Richard Earnshaw (lists) wrote:
> On 23/03/17 16:02, Thomas Preudhomme wrote:
>> Hi,
>>
>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
>> not test the changed code since ARMv7-R does not have division
>> instructions in ARM state. This patch changes it to target Cortex-R5
>> processor instead which does have division instructions in ARM state.
>>
>> ChangeLog entry is as follows:
>>
>> *** gcc/testsuite/ChangeLog ***
>>
>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>
>> PR target/80082
>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>> ARMv7-R.
>>
>> Is this ok for stage4?
>>
>> Best regards,
>>
>> Thomas
>>
>> atomic_loaddi_11_cortexr5.patch
>>
>>
>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>> index 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b 100644
>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>> @@ -1,7 +1,6 @@
>> /* { dg-do compile } */
>> /* { dg-require-effective-target arm_arch_v7r_ok } */
>> -/* { dg-options "-O2" } */
>> -/* { dg-add-options arm_arch_v7r } */
>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>>
>> #include <stdatomic.h>
>>
>>
>
> Will that work properly if doing multilib testing with a specific CPU
> target?
>
> R.
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5
2017-03-23 16:19 ` Thomas Preudhomme
@ 2017-03-23 16:53 ` Thomas Preudhomme
2017-03-23 17:00 ` Thomas Preudhomme
0 siblings, 1 reply; 9+ messages in thread
From: Thomas Preudhomme @ 2017-03-23 16:53 UTC (permalink / raw)
To: Richard Earnshaw (lists),
Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1946 bytes --]
Please find attached an updated patch. ChangeLog entry unchanged:
*** gcc/testsuite/ChangeLog ***
2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
PR target/80082
* gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
ARMv7-R.
Is this ok for stage4?
Best regards,
Thomas
On 23/03/17 16:19, Thomas Preudhomme wrote:
> Mmmh I probably need to add a dg-skip-if in there. Will respin the patch.
>
> Best regards,
>
> Thomas
>
> On 23/03/17 16:10, Richard Earnshaw (lists) wrote:
>> On 23/03/17 16:02, Thomas Preudhomme wrote:
>>> Hi,
>>>
>>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
>>> not test the changed code since ARMv7-R does not have division
>>> instructions in ARM state. This patch changes it to target Cortex-R5
>>> processor instead which does have division instructions in ARM state.
>>>
>>> ChangeLog entry is as follows:
>>>
>>> *** gcc/testsuite/ChangeLog ***
>>>
>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>
>>> PR target/80082
>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>> ARMv7-R.
>>>
>>> Is this ok for stage4?
>>>
>>> Best regards,
>>>
>>> Thomas
>>>
>>> atomic_loaddi_11_cortexr5.patch
>>>
>>>
>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>> b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>> index
>>> 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b
>>> 100644
>>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>> @@ -1,7 +1,6 @@
>>> /* { dg-do compile } */
>>> /* { dg-require-effective-target arm_arch_v7r_ok } */
>>> -/* { dg-options "-O2" } */
>>> -/* { dg-add-options arm_arch_v7r } */
>>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>>>
>>> #include <stdatomic.h>
>>>
>>>
>>
>> Will that work properly if doing multilib testing with a specific CPU
>> target?
>>
>> R.
>>
[-- Attachment #2: atomic_loaddi_11_cortexr5.patch --]
[-- Type: text/x-patch, Size: 550 bytes --]
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
index 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b 100644
--- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -1,7 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v7r_ok } */
-/* { dg-options "-O2" } */
-/* { dg-add-options arm_arch_v7r } */
+/* { dg-options "-O2 -mcpu=cortex-r5" } */
#include <stdatomic.h>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5
2017-03-23 16:53 ` Thomas Preudhomme
@ 2017-03-23 17:00 ` Thomas Preudhomme
2017-03-23 17:18 ` Thomas Preudhomme
0 siblings, 1 reply; 9+ messages in thread
From: Thomas Preudhomme @ 2017-03-23 17:00 UTC (permalink / raw)
To: Richard Earnshaw (lists),
Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
Sorry, I forgot about -march. Hold on.
On 23/03/17 16:51, Thomas Preudhomme wrote:
> Please find attached an updated patch. ChangeLog entry unchanged:
>
> *** gcc/testsuite/ChangeLog ***
>
> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>
> PR target/80082
> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
> ARMv7-R.
>
> Is this ok for stage4?
>
> Best regards,
>
> Thomas
>
> On 23/03/17 16:19, Thomas Preudhomme wrote:
>> Mmmh I probably need to add a dg-skip-if in there. Will respin the patch.
>>
>> Best regards,
>>
>> Thomas
>>
>> On 23/03/17 16:10, Richard Earnshaw (lists) wrote:
>>> On 23/03/17 16:02, Thomas Preudhomme wrote:
>>>> Hi,
>>>>
>>>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
>>>> not test the changed code since ARMv7-R does not have division
>>>> instructions in ARM state. This patch changes it to target Cortex-R5
>>>> processor instead which does have division instructions in ARM state.
>>>>
>>>> ChangeLog entry is as follows:
>>>>
>>>> *** gcc/testsuite/ChangeLog ***
>>>>
>>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>>
>>>> PR target/80082
>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>>> ARMv7-R.
>>>>
>>>> Is this ok for stage4?
>>>>
>>>> Best regards,
>>>>
>>>> Thomas
>>>>
>>>> atomic_loaddi_11_cortexr5.patch
>>>>
>>>>
>>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>> b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>> index
>>>> 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b
>>>>
>>>> 100644
>>>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>> @@ -1,7 +1,6 @@
>>>> /* { dg-do compile } */
>>>> /* { dg-require-effective-target arm_arch_v7r_ok } */
>>>> -/* { dg-options "-O2" } */
>>>> -/* { dg-add-options arm_arch_v7r } */
>>>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>>>>
>>>> #include <stdatomic.h>
>>>>
>>>>
>>>
>>> Will that work properly if doing multilib testing with a specific CPU
>>> target?
>>>
>>> R.
>>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5
2017-03-23 17:00 ` Thomas Preudhomme
@ 2017-03-23 17:18 ` Thomas Preudhomme
2017-03-30 11:32 ` Thomas Preudhomme
0 siblings, 1 reply; 9+ messages in thread
From: Thomas Preudhomme @ 2017-03-23 17:18 UTC (permalink / raw)
To: Richard Earnshaw (lists),
Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 2581 bytes --]
My apologize, this works for both -march of -mcpu not cortex-r4 in RUNTESTFLAGS.
ChangeLog entry is unchanged:
*** gcc/testsuite/ChangeLog ***
2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
PR target/80082
* gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
ARMv7-R.
Best regards,
Thomas
On 23/03/17 16:53, Thomas Preudhomme wrote:
> Sorry, I forgot about -march. Hold on.
>
> On 23/03/17 16:51, Thomas Preudhomme wrote:
>> Please find attached an updated patch. ChangeLog entry unchanged:
>>
>> *** gcc/testsuite/ChangeLog ***
>>
>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>
>> PR target/80082
>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>> ARMv7-R.
>>
>> Is this ok for stage4?
>>
>> Best regards,
>>
>> Thomas
>>
>> On 23/03/17 16:19, Thomas Preudhomme wrote:
>>> Mmmh I probably need to add a dg-skip-if in there. Will respin the patch.
>>>
>>> Best regards,
>>>
>>> Thomas
>>>
>>> On 23/03/17 16:10, Richard Earnshaw (lists) wrote:
>>>> On 23/03/17 16:02, Thomas Preudhomme wrote:
>>>>> Hi,
>>>>>
>>>>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
>>>>> not test the changed code since ARMv7-R does not have division
>>>>> instructions in ARM state. This patch changes it to target Cortex-R5
>>>>> processor instead which does have division instructions in ARM state.
>>>>>
>>>>> ChangeLog entry is as follows:
>>>>>
>>>>> *** gcc/testsuite/ChangeLog ***
>>>>>
>>>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>>>
>>>>> PR target/80082
>>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>>>> ARMv7-R.
>>>>>
>>>>> Is this ok for stage4?
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Thomas
>>>>>
>>>>> atomic_loaddi_11_cortexr5.patch
>>>>>
>>>>>
>>>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>> b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>> index
>>>>> 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b
>>>>>
>>>>>
>>>>> 100644
>>>>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>> @@ -1,7 +1,6 @@
>>>>> /* { dg-do compile } */
>>>>> /* { dg-require-effective-target arm_arch_v7r_ok } */
>>>>> -/* { dg-options "-O2" } */
>>>>> -/* { dg-add-options arm_arch_v7r } */
>>>>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>>>>>
>>>>> #include <stdatomic.h>
>>>>>
>>>>>
>>>>
>>>> Will that work properly if doing multilib testing with a specific CPU
>>>> target?
>>>>
>>>> R.
>>>>
[-- Attachment #2: atomic_loaddi_11_cortexr5.patch --]
[-- Type: text/x-patch, Size: 550 bytes --]
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
index 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b 100644
--- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -1,7 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v7r_ok } */
-/* { dg-options "-O2" } */
-/* { dg-add-options arm_arch_v7r } */
+/* { dg-options "-O2 -mcpu=cortex-r5" } */
#include <stdatomic.h>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5
2017-03-23 17:18 ` Thomas Preudhomme
@ 2017-03-30 11:32 ` Thomas Preudhomme
2017-04-04 17:00 ` [PATCH, GCC/testsuite/ARM, stage4, ping] " Thomas Preudhomme
0 siblings, 1 reply; 9+ messages in thread
From: Thomas Preudhomme @ 2017-03-30 11:32 UTC (permalink / raw)
To: Richard Earnshaw (lists),
Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 2777 bytes --]
Ping?
Best regards,
Thomas
On 23/03/17 17:09, Thomas Preudhomme wrote:
> My apologize, this works for both -march of -mcpu not cortex-r4 in RUNTESTFLAGS.
>
> ChangeLog entry is unchanged:
>
> *** gcc/testsuite/ChangeLog ***
>
> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>
> PR target/80082
> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
> ARMv7-R.
>
> Best regards,
>
> Thomas
>
> On 23/03/17 16:53, Thomas Preudhomme wrote:
>> Sorry, I forgot about -march. Hold on.
>>
>> On 23/03/17 16:51, Thomas Preudhomme wrote:
>>> Please find attached an updated patch. ChangeLog entry unchanged:
>>>
>>> *** gcc/testsuite/ChangeLog ***
>>>
>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>
>>> PR target/80082
>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>> ARMv7-R.
>>>
>>> Is this ok for stage4?
>>>
>>> Best regards,
>>>
>>> Thomas
>>>
>>> On 23/03/17 16:19, Thomas Preudhomme wrote:
>>>> Mmmh I probably need to add a dg-skip-if in there. Will respin the patch.
>>>>
>>>> Best regards,
>>>>
>>>> Thomas
>>>>
>>>> On 23/03/17 16:10, Richard Earnshaw (lists) wrote:
>>>>> On 23/03/17 16:02, Thomas Preudhomme wrote:
>>>>>> Hi,
>>>>>>
>>>>>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
>>>>>> not test the changed code since ARMv7-R does not have division
>>>>>> instructions in ARM state. This patch changes it to target Cortex-R5
>>>>>> processor instead which does have division instructions in ARM state.
>>>>>>
>>>>>> ChangeLog entry is as follows:
>>>>>>
>>>>>> *** gcc/testsuite/ChangeLog ***
>>>>>>
>>>>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>>>>
>>>>>> PR target/80082
>>>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>>>>> ARMv7-R.
>>>>>>
>>>>>> Is this ok for stage4?
>>>>>>
>>>>>> Best regards,
>>>>>>
>>>>>> Thomas
>>>>>>
>>>>>> atomic_loaddi_11_cortexr5.patch
>>>>>>
>>>>>>
>>>>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>> b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>> index
>>>>>> 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b
>>>>>>
>>>>>>
>>>>>>
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>> @@ -1,7 +1,6 @@
>>>>>> /* { dg-do compile } */
>>>>>> /* { dg-require-effective-target arm_arch_v7r_ok } */
>>>>>> -/* { dg-options "-O2" } */
>>>>>> -/* { dg-add-options arm_arch_v7r } */
>>>>>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>>>>>>
>>>>>> #include <stdatomic.h>
>>>>>>
>>>>>>
>>>>>
>>>>> Will that work properly if doing multilib testing with a specific CPU
>>>>> target?
>>>>>
>>>>> R.
>>>>>
[-- Attachment #2: atomic_loaddi_11_cortexr5.patch --]
[-- Type: text/x-patch, Size: 550 bytes --]
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
index 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b 100644
--- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -1,7 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v7r_ok } */
-/* { dg-options "-O2" } */
-/* { dg-add-options arm_arch_v7r } */
+/* { dg-options "-O2 -mcpu=cortex-r5" } */
#include <stdatomic.h>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4, ping] Compile atomic_loaddi_11 for Cortex-R5
2017-03-30 11:32 ` Thomas Preudhomme
@ 2017-04-04 17:00 ` Thomas Preudhomme
2017-04-06 13:03 ` Ramana Radhakrishnan
0 siblings, 1 reply; 9+ messages in thread
From: Thomas Preudhomme @ 2017-04-04 17:00 UTC (permalink / raw)
To: Richard Earnshaw (lists),
Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 3482 bytes --]
Hi,
gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
not test the changed code since ARMv7-R does not have division
instructions in ARM state. This patch changes it to target Cortex-R5
processor instead which does have division instructions in ARM state.
ChangeLog entry is as follows:
*** gcc/testsuite/ChangeLog ***
2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
PR target/80082
* gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
ARMv7-R.
Is this ok for stage4?
Best regards,
Thomas
On 30/03/17 11:55, Thomas Preudhomme wrote:
> Ping?
>
> Best regards,
>
> Thomas
>
> On 23/03/17 17:09, Thomas Preudhomme wrote:
>> My apologize, this works for both -march of -mcpu not cortex-r4 in RUNTESTFLAGS.
>>
>> ChangeLog entry is unchanged:
>>
>> *** gcc/testsuite/ChangeLog ***
>>
>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>
>> PR target/80082
>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>> ARMv7-R.
>>
>> Best regards,
>>
>> Thomas
>>
>> On 23/03/17 16:53, Thomas Preudhomme wrote:
>>> Sorry, I forgot about -march. Hold on.
>>>
>>> On 23/03/17 16:51, Thomas Preudhomme wrote:
>>>> Please find attached an updated patch. ChangeLog entry unchanged:
>>>>
>>>> *** gcc/testsuite/ChangeLog ***
>>>>
>>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>>
>>>> PR target/80082
>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>>> ARMv7-R.
>>>>
>>>> Is this ok for stage4?
>>>>
>>>> Best regards,
>>>>
>>>> Thomas
>>>>
>>>> On 23/03/17 16:19, Thomas Preudhomme wrote:
>>>>> Mmmh I probably need to add a dg-skip-if in there. Will respin the patch.
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Thomas
>>>>>
>>>>> On 23/03/17 16:10, Richard Earnshaw (lists) wrote:
>>>>>> On 23/03/17 16:02, Thomas Preudhomme wrote:
>>>>>>> Hi,
>>>>>>>
>>>>>>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
>>>>>>> not test the changed code since ARMv7-R does not have division
>>>>>>> instructions in ARM state. This patch changes it to target Cortex-R5
>>>>>>> processor instead which does have division instructions in ARM state.
>>>>>>>
>>>>>>> ChangeLog entry is as follows:
>>>>>>>
>>>>>>> *** gcc/testsuite/ChangeLog ***
>>>>>>>
>>>>>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>>>>>
>>>>>>> PR target/80082
>>>>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>>>>>> ARMv7-R.
>>>>>>>
>>>>>>> Is this ok for stage4?
>>>>>>>
>>>>>>> Best regards,
>>>>>>>
>>>>>>> Thomas
>>>>>>>
>>>>>>> atomic_loaddi_11_cortexr5.patch
>>>>>>>
>>>>>>>
>>>>>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>> b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>> index
>>>>>>> 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> 100644
>>>>>>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>> @@ -1,7 +1,6 @@
>>>>>>> /* { dg-do compile } */
>>>>>>> /* { dg-require-effective-target arm_arch_v7r_ok } */
>>>>>>> -/* { dg-options "-O2" } */
>>>>>>> -/* { dg-add-options arm_arch_v7r } */
>>>>>>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>>>>>>>
>>>>>>> #include <stdatomic.h>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>> Will that work properly if doing multilib testing with a specific CPU
>>>>>> target?
>>>>>>
>>>>>> R.
>>>>>>
[-- Attachment #2: atomic_loaddi_11_cortexr5.patch --]
[-- Type: text/x-patch, Size: 653 bytes --]
diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
index 275669bd76356dc7c7b6a5373792d9a5089ede51..85c64ae68b1b1ee68466809f7f83d07ceabec575 100644
--- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
+++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v7r_ok } */
-/* { dg-options "-O2" } */
-/* { dg-add-options arm_arch_v7r } */
+/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-r5" } } */
+/* { dg-options "-O2 -mcpu=cortex-r5" } */
#include <stdatomic.h>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, GCC/testsuite/ARM, stage4, ping] Compile atomic_loaddi_11 for Cortex-R5
2017-04-04 17:00 ` [PATCH, GCC/testsuite/ARM, stage4, ping] " Thomas Preudhomme
@ 2017-04-06 13:03 ` Ramana Radhakrishnan
0 siblings, 0 replies; 9+ messages in thread
From: Ramana Radhakrishnan @ 2017-04-06 13:03 UTC (permalink / raw)
To: Thomas Preudhomme
Cc: Richard Earnshaw (lists),
Kyrill Tkachov, Ramana Radhakrishnan, gcc-patches
On Tue, Apr 4, 2017 at 6:00 PM, Thomas Preudhomme
<thomas.preudhomme@foss.arm.com> wrote:
> Hi,
>
> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does
> not test the changed code since ARMv7-R does not have division
> instructions in ARM state. This patch changes it to target Cortex-R5
> processor instead which does have division instructions in ARM state.
>
> ChangeLog entry is as follows:
>
> *** gcc/testsuite/ChangeLog ***
>
> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>
> PR target/80082
> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
> ARMv7-R.
>
> Is this ok for stage4?
OK.
Ramana
>
> Best regards,
>
> Thomas
>
> On 30/03/17 11:55, Thomas Preudhomme wrote:
>>
>> Ping?
>>
>> Best regards,
>>
>> Thomas
>>
>> On 23/03/17 17:09, Thomas Preudhomme wrote:
>>>
>>> My apologize, this works for both -march of -mcpu not cortex-r4 in
>>> RUNTESTFLAGS.
>>>
>>> ChangeLog entry is unchanged:
>>>
>>> *** gcc/testsuite/ChangeLog ***
>>>
>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>
>>> PR target/80082
>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>> ARMv7-R.
>>>
>>> Best regards,
>>>
>>> Thomas
>>>
>>> On 23/03/17 16:53, Thomas Preudhomme wrote:
>>>>
>>>> Sorry, I forgot about -march. Hold on.
>>>>
>>>> On 23/03/17 16:51, Thomas Preudhomme wrote:
>>>>>
>>>>> Please find attached an updated patch. ChangeLog entry unchanged:
>>>>>
>>>>> *** gcc/testsuite/ChangeLog ***
>>>>>
>>>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>>>
>>>>> PR target/80082
>>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>>>> ARMv7-R.
>>>>>
>>>>> Is this ok for stage4?
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Thomas
>>>>>
>>>>> On 23/03/17 16:19, Thomas Preudhomme wrote:
>>>>>>
>>>>>> Mmmh I probably need to add a dg-skip-if in there. Will respin the
>>>>>> patch.
>>>>>>
>>>>>> Best regards,
>>>>>>
>>>>>> Thomas
>>>>>>
>>>>>> On 23/03/17 16:10, Richard Earnshaw (lists) wrote:
>>>>>>>
>>>>>>> On 23/03/17 16:02, Thomas Preudhomme wrote:
>>>>>>>>
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365
>>>>>>>> does
>>>>>>>> not test the changed code since ARMv7-R does not have division
>>>>>>>> instructions in ARM state. This patch changes it to target Cortex-R5
>>>>>>>> processor instead which does have division instructions in ARM
>>>>>>>> state.
>>>>>>>>
>>>>>>>> ChangeLog entry is as follows:
>>>>>>>>
>>>>>>>> *** gcc/testsuite/ChangeLog ***
>>>>>>>>
>>>>>>>> 2017-03-22 Thomas Preud'homme <thomas.preudhomme@arm.com
>>>>>>>>
>>>>>>>> PR target/80082
>>>>>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of
>>>>>>>> ARMv7-R.
>>>>>>>>
>>>>>>>> Is this ok for stage4?
>>>>>>>>
>>>>>>>> Best regards,
>>>>>>>>
>>>>>>>> Thomas
>>>>>>>>
>>>>>>>> atomic_loaddi_11_cortexr5.patch
>>>>>>>>
>>>>>>>>
>>>>>>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>>> b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>>> index
>>>>>>>>
>>>>>>>> 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> 100644
>>>>>>>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c
>>>>>>>> @@ -1,7 +1,6 @@
>>>>>>>> /* { dg-do compile } */
>>>>>>>> /* { dg-require-effective-target arm_arch_v7r_ok } */
>>>>>>>> -/* { dg-options "-O2" } */
>>>>>>>> -/* { dg-add-options arm_arch_v7r } */
>>>>>>>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */
>>>>>>>>
>>>>>>>> #include <stdatomic.h>
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>> Will that work properly if doing multilib testing with a specific CPU
>>>>>>> target?
>>>>>>>
>>>>>>> R.
>>>>>>>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-04-06 13:03 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-23 16:03 [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5 Thomas Preudhomme
2017-03-23 16:10 ` Richard Earnshaw (lists)
2017-03-23 16:19 ` Thomas Preudhomme
2017-03-23 16:53 ` Thomas Preudhomme
2017-03-23 17:00 ` Thomas Preudhomme
2017-03-23 17:18 ` Thomas Preudhomme
2017-03-30 11:32 ` Thomas Preudhomme
2017-04-04 17:00 ` [PATCH, GCC/testsuite/ARM, stage4, ping] " Thomas Preudhomme
2017-04-06 13:03 ` Ramana Radhakrishnan
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