From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) by sourceware.org (Postfix) with ESMTPS id ECC453858D20 for ; Wed, 20 Sep 2023 01:12:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ECC453858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-ot1-x32e.google.com with SMTP id 46e09a7af769-6c21b2c6868so3661956a34.1 for ; Tue, 19 Sep 2023 18:12:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1695172363; x=1695777163; darn=gcc.gnu.org; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=6XMoVLnCff4Nzvu8o/cg4cgMZmx227jBqxU6yWT/uJA=; b=cdEgOM1D96tlRECXQGU2C2bK3Os2PffxAWGX4DySnhJb5MJKMmo0HSW9yUXclX9WDU t6tsntpsAyzXZxUXYYYUTUlxrMzGW9gPU/Q0tk1W8aHZbiSgeZBnomXAmTK6Z7AnyFmQ +wRAKqgxC51p/YIJCGbAJh9JiQqhnCDAi2meq2JBE3PlF+EZnvCf9VpvZQjL8RTjmVP8 UKqEaaaLTHrbI0OiBgiuSk0MSahW79NJ1Ic7mDducxVvUFFAWj9BfgvLq6OxTPdLSnnw GhH6jKO/2cheyu3VCzqm+nt5F1nsOLGk1XnKg8jyb7RAEPsLz9s9MadLoUmnugbExf07 opbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695172363; x=1695777163; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=6XMoVLnCff4Nzvu8o/cg4cgMZmx227jBqxU6yWT/uJA=; b=ABbaEEDixy+drqyvIZPztCbK1ZvtHyWaT34JfbSztSMHu4/xQ9MQFhufyN2d6NffeO 3xmq0ckHe2LiQb4aB5KySxj2bFlB9bD642gzSjqoncB4yJUQMRbaeAzI4oJdQCRG53xk 5po06vnPNls32DT6Dm859wj4CJYc3RTbe/NtYMHitspESL7iPbxTQUrkhjw8wQZnF3fT 5Dqk2PSphg8BTQSKzyXpM5nr54l/4jtrsGW20hIeXdE/+zA4JUonhkoYMXAXMketAvIw LzWFv/tqBpBxTBkDjI4dqsbNigcEobUp8M4rWEnFkh0NcC2Ghte89J4KmKdJoGy1eN4J atyg== X-Gm-Message-State: AOJu0Yw2Mn1yGvh4Q6Lfuj0bBiuk0V3X5hZ5BsFiow2Z/yTA8HO16sR/ IDkQiRPxfjtyEcjX+PesM4hHbg== X-Google-Smtp-Source: AGHT+IFvKXzmPjh54ncG5f4jyS/6H0bgTqTX4Q6UuFLe3eUZlyuk87ph2tr1MPDdw7pAx0+CRk2xyg== X-Received: by 2002:a05:6808:208d:b0:3a4:31c6:7650 with SMTP id s13-20020a056808208d00b003a431c67650mr1065549oiw.26.1695172363295; Tue, 19 Sep 2023 18:12:43 -0700 (PDT) Received: from [10.0.17.156] ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id k25-20020aa792d9000000b0068c0fcb40d3sm9023220pfa.211.2023.09.19.18.12.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Sep 2023 18:12:42 -0700 (PDT) Content-Type: multipart/alternative; boundary="------------f0M37G6N1hycvHA3UBOdP1T3" Message-ID: Date: Tue, 19 Sep 2023 18:12:41 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [Committed] RISC-V: Support VLS unary floating-point patterns Content-Language: en-US To: "juzhe.zhong@rivai.ai" , "kito.cheng" Cc: Robin Dapp , gcc-patches , "Kito.cheng" , jeffreyalaw , palmer , Edwin Lu , "joern.rennecke" , "jeremy.bennett" , gnu-toolchain References: <20230919112653.539780-1-juzhe.zhong@rivai.ai> <093b0e09-6106-447b-f8f8-0c036f2c927b@rivosinc.com> <4762709994E94A14+2023092008545356909135@rivai.ai> From: Patrick O'Neill In-Reply-To: <4762709994E94A14+2023092008545356909135@rivai.ai> X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------f0M37G6N1hycvHA3UBOdP1T3 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit I'll let it run overnight and see if this helps. Even before this patch, I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so this won't fix all the issues. It's easily replicated using upstream riscv-gnu-toolchain git clone https://github.com/riscv-collab/riscv-gnu-toolchain cd riscv-gnu-toolchain git submodule update --init gcc cd gcc git pull master cd .. mkdir build cd build ../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d make report-linux -j32 Then search for "stubs" in the debug logs (/build-gcc-linux-stage2/gcc/testsuite/*.log) Patrick On 9/19/23 17:54, juzhe.zhong@rivai.ai wrote: > I think we could remove match.h. > > Hi, @Patrick. Could you verify it? > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > index 2292372d7a3..674098e9ba6 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > @@ -1,5 +1,4 @@ >  #include > -#include > > and commit it. > > Thanks. > ------------------------------------------------------------------------ > juzhe.zhong@rivai.ai > > *From:* Kito Cheng > *Date:* 2023-09-20 08:52 > *To:* 钟居哲 > *CC:* Patrick O'Neill ; Robin Dapp > ; gcc-patches > ; Kito.cheng > ; jeffreyalaw > ; palmer > ; Edwin Lu ; > joern.rennecke ; > jeremy.bennett ; gnu-toolchain > > *Subject:* Re: Re: [Committed] RISC-V: Support VLS unary > floating-point patterns > It seems because math.h, similar issue as stdint.h, does math.h > necessary for the test case? > > juzhe.zhong@rivai.ai 於 2023年9月20日 週三 > 08:44 寫道： > > I didn't see this issue. > They should be the bogus FAILs. > We should either fix testcases or ignore them. > > ------------------------------------------------------------------------ > juzhe.zhong@rivai.ai > > *From:* Patrick O'Neill > *Date:* 2023-09-20 08:34 > *To:* Juzhe-Zhong ; Robin > Dapp ; gcc-patches > > *CC:* kito.cheng ; kito.cheng > ; jeffreyalaw > ; Palmer Dabbelt > ; Edwin Lu > ; joern.rennecke > ; jeremy.bennett > ; gnu-toolchain > > *Subject:* Re: [Committed] RISC-V: Support VLS unary > floating-point patterns > Hi, > This patch highlights an issue Edwin and I have been > having with the > testsuite where rv64 testcases are run when testing rv32gcv. > There's a large number of new failures in the rv32gcv > testsuite from > this seemingly innocuous patch. > https://github.com/ewlu/riscv-gnu-toolchain/issues/166 > (The repo is still a WIP - eventually will be non-gating > patchworks > pre-commit CI) > From Edwin and my investigation the failures for rv32gcv > look like [1]. > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11: > > fatal error: gnu/stubs-lp64d.h: No such file or directory > compilation terminated. > Top of the failing testcase: > /* { dg-do compile } */ > /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > -fno-schedule-insns -fno-schedule-insns2 > --param=riscv-autovec-lmul=m8" } */ > #include "def.h" > The dg-options explicitly set rv64gcv, so I don't think > this testcase > should even be executed. > For the 3 new failures on rv64gcv, they all explicitly set > rv32gcv. > /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ > These are seen on non-multilib builds. Multilib rv32/64gc > does not > appear to have the same issue when compiling (we're > currently testing > multilib rv32/64gcv to see if they encounter issues when > executing). > Are other people seeing similar errors/is this a known issue? > Patrick > [1]: > Executing on host: > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc > > -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c > > -march=rv32gcv -mabi=ilp32d -mcmodel=medlow > -fdiagnostics-plain-output > -O3 -ftree-vectorize --param > riscv-autovec-preference=scalable > -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > -fno-schedule-insns > -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 > -ffat-lto-objects > -fno-ident -S   -o floating-point-mul-3.s (timeout = 600) > spawn -ignore SIGHUP > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc > > -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ > > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c > > -march=rv32gcv -mabi=ilp32d -mcmodel=medlow > -fdiagnostics-plain-output > -O3 -ftree-vectorize --param > riscv-autovec-preference=scalable > -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > -fno-schedule-insns > -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 > -ffat-lto-objects > -fno-ident -S -o floating-point-mul-3.s > In file included from > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515, >                  from > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33, >                  from > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27, >                  from > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h:2, >                  from > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4: > /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11: > > fatal error: gnu/stubs-lp64d.h: No such file or directory > compilation terminated. > compiler exited with status 1 > FAIL: > gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3 > -ftree-vectorize --param riscv-autovec-preference=scalable > (test for > excess errors) > On 9/19/23 04:26, Juzhe-Zhong wrote: > > Extend current VLA patterns with VLS modes. > > > > Regression all passed. > > > > gcc/ChangeLog: > > > > * config/riscv/autovec.md: Extend VLS modes. > > * config/riscv/vector.md: Ditto. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test. > > * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test. > > > > --- > > gcc/config/riscv/autovec.md                   | 12 ++--- > > gcc/config/riscv/vector.md                    | 20 +++---- > > .../gcc.target/riscv/rvv/autovec/vls/def.h    | 3 +- > > .../gcc.target/riscv/rvv/autovec/vls/neg-2.c  | 52 > +++++++++++++++++++ > >   4 files changed, 70 insertions(+), 17 deletions(-) > >   create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > > > > diff --git a/gcc/config/riscv/autovec.md > b/gcc/config/riscv/autovec.md > > index 769ef6daa36..75ed7ae4f2e 100644 > > --- a/gcc/config/riscv/autovec.md > > +++ b/gcc/config/riscv/autovec.md > > @@ -1031,9 +1031,9 @@ > >   ;; - vfneg.v/vfabs.v > >   ;; > ------------------------------------------------------------------------------- > >   (define_insn_and_split "2" > > -  [(set (match_operand:VF 0 "register_operand") > > -    (any_float_unop_nofrm:VF > > -     (match_operand:VF 1 "register_operand")))] > > +  [(set (match_operand:V_VLSF 0 "register_operand") > > +    (any_float_unop_nofrm:V_VLSF > > +     (match_operand:V_VLSF 1 "register_operand")))] > >     "TARGET_VECTOR && can_create_pseudo_p ()" > >     "#" > >     "&& 1" > > @@ -1052,9 +1052,9 @@ > >   ;; - vfsqrt.v > >   ;; > ------------------------------------------------------------------------------- > >   (define_insn_and_split "2" > > -  [(set (match_operand:VF 0 "register_operand") > > -    (any_float_unop:VF > > -     (match_operand:VF 1 "register_operand")))] > > +  [(set (match_operand:V_VLSF 0 "register_operand") > > +    (any_float_unop:V_VLSF > > +     (match_operand:V_VLSF 1 "register_operand")))] > >     "TARGET_VECTOR && can_create_pseudo_p ()" > >     "#" > >     "&& 1" > > diff --git a/gcc/config/riscv/vector.md > b/gcc/config/riscv/vector.md > > index f7f37da692a..f66ffebba24 100644 > > --- a/gcc/config/riscv/vector.md > > +++ b/gcc/config/riscv/vector.md > > @@ -6756,8 +6756,8 @@ > >   ;; > ------------------------------------------------------------------------------- > > > >   (define_insn "@pred_" > > -  [(set (match_operand:VF 0 > "register_operand"           "=vd, vd, vr, vr") > > - (if_then_else:VF > > +  [(set (match_operand:V_VLSF 0 > "register_operand"           "=vd, vd, vr, vr") > > + (if_then_else:V_VLSF > >     (unspec: > >       [(match_operand: 1 "vector_mask_operand" " vm, > vm,Wc1,Wc1") > >        (match_operand 4 "vector_length_operand"    " rK, > rK, rK, rK") > > @@ -6768,9 +6768,9 @@ > >        (reg:SI VL_REGNUM) > >        (reg:SI VTYPE_REGNUM) > >        (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > > -   (any_float_unop:VF > > -     (match_operand:VF 3 "register_operand"       " vr, > vr, vr, vr")) > > -   (match_operand:VF 2 "vector_merge_operand"     " > vu,  0, vu,  0")))] > > +   (any_float_unop:V_VLSF > > +     (match_operand:V_VLSF 3 "register_operand"       " > vr, vr, vr, vr")) > > +   (match_operand:V_VLSF 2 "vector_merge_operand"     " > vu,  0, vu,  0")))] > >     "TARGET_VECTOR" > >     "vf.v\t%0,%3%p1" > >     [(set_attr "type" "") > > @@ -6783,8 +6783,8 @@ > >   (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) > > > >   (define_insn "@pred_" > > -  [(set (match_operand:VF 0 > "register_operand"           "=vd, vd, vr, vr") > > - (if_then_else:VF > > +  [(set (match_operand:V_VLSF 0 > "register_operand"           "=vd, vd, vr, vr") > > + (if_then_else:V_VLSF > >     (unspec: > >       [(match_operand: 1 "vector_mask_operand" " vm, > vm,Wc1,Wc1") > >        (match_operand 4 "vector_length_operand"    " rK, > rK, rK, rK") > > @@ -6793,9 +6793,9 @@ > >        (match_operand 7 "const_int_operand"        "  > i,  i,  i,  i") > >        (reg:SI VL_REGNUM) > >        (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > > -   (any_float_unop_nofrm:VF > > -     (match_operand:VF 3 "register_operand"       " vr, > vr, vr, vr")) > > -   (match_operand:VF 2 "vector_merge_operand"     " > vu,  0, vu,  0")))] > > +   (any_float_unop_nofrm:V_VLSF > > +     (match_operand:V_VLSF 3 "register_operand"       " > vr, vr, vr, vr")) > > +   (match_operand:V_VLSF 2 "vector_merge_operand"     " > vu,  0, vu,  0")))] > >     "TARGET_VECTOR" > >     "vf.v\t%0,%3%p1" > >     [(set_attr "type" "") > > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > > index 5df90704885..d7b721b4e3e 100644 > > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > > @@ -1,4 +1,5 @@ > >   #include > > +#include > > > >   typedef int8_t v1qi __attribute__ ((vector_size (1))); > >   typedef int8_t v2qi __attribute__ ((vector_size (2))); > > @@ -210,7 +211,7 @@ typedef double v512df __attribute__ > ((vector_size (4096))); > >     PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE > *restrict b)                    \ > > { \ > >       for (int i = 0; i < NUM; ++i) \ > > -      a[i] = OP b[i]; \ > > +      a[i] = OP (b[i]); \ > >     } > > > >   #define DEF_CALL_VV(PREFIX, NUM, TYPE, > CALL)                                   \ > > diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > > new file mode 100644 > > index 00000000000..c2ab0098afa > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > > @@ -0,0 +1,52 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b > -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 > --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ > > + > > +#include "def.h" > > + > > +DEF_OP_V (neg, 2, _Float16, -) > > +DEF_OP_V (neg, 4, _Float16, -) > > +DEF_OP_V (neg, 8, _Float16, -) > > +DEF_OP_V (neg, 16, _Float16, -) > > +DEF_OP_V (neg, 32, _Float16, -) > > +DEF_OP_V (neg, 64, _Float16, -) > > +DEF_OP_V (neg, 128, _Float16, -) > > +DEF_OP_V (neg, 256, _Float16, -) > > +DEF_OP_V (neg, 512, _Float16, -) > > +DEF_OP_V (neg, 1024, _Float16, -) > > +DEF_OP_V (neg, 2048, _Float16, -) > > + > > +DEF_OP_V (neg, 2, float, -) > > +DEF_OP_V (neg, 4, float, -) > > +DEF_OP_V (neg, 8, float, -) > > +DEF_OP_V (neg, 16, float, -) > > +DEF_OP_V (neg, 32, float, -) > > +DEF_OP_V (neg, 64, float, -) > > +DEF_OP_V (neg, 128, float, -) > > +DEF_OP_V (neg, 256, float, -) > > +DEF_OP_V (neg, 512, float, -) > > +DEF_OP_V (neg, 1024, float, -) > > + > > +DEF_OP_V (neg, 2, double, -) > > +DEF_OP_V (neg, 4, double, -) > > +DEF_OP_V (neg, 8, double, -) > > +DEF_OP_V (neg, 16, double, -) > > +DEF_OP_V (neg, 32, double, -) > > +DEF_OP_V (neg, 64, double, -) > > +DEF_OP_V (neg, 128, double, -) > > +DEF_OP_V (neg, 256, double, -) > > +DEF_OP_V (neg, 512, double, -) > > + > > +/* { dg-final { scan-assembler-times > {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */ > > +/* { dg-final { scan-assembler-not {csrr} } } */ > > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" > } } */ > > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" > } } */ > > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" > } } */ > > +/* { dg-final { scan-tree-dump-not "128,128" > "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "256,256" > "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "512,512" > "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "1024,1024" > "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "2048,2048" > "optimized" } } */ > > +/* { dg-final { scan-tree-dump-not "4096,4096" > "optimized" } } */ > --------------f0M37G6N1hycvHA3UBOdP1T3--