Re: [PATCH] Fix typo in insn name.

["Kewen.Lin" <linkw@linux.ibm.com>]

Hi Mike,

on 2023/7/11 03:59, Michael Meissner wrote:
> In doing other work, I noticed that there was an insn:
> 
> 	vsx_extract_v4sf_<mode>_load
> 
> Which did not have an iterator.  I removed the useless <mode>.

It actually has a mode iterator, the "P" is used for clobber.

The whole pattern of this define_insn_and_split is

(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
  [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
	(vec_select:SF
	 (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
	 (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
   (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]         <== *P used here*

Its definition is:

(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])

I guess we can just leave it there?

BR,
Kewen

> 
> I have tested this patch on the following systems and there was no degration.
> Can I check it into the trunk branch?
> 
>     *	Power10, LE, --with-cpu=power10, IBM 128-bit long double
>     *	Power9,  LE, --with-cpu=power9,  IBM 128-bit long double
>     *	Power9,  LE, --with-cpu=power9,  IEEE 128-bit long double
>     *   Power9,  LE, --with-cpu=power9,  64-bit default long double
>     *	Power9,  BE, --with-cpu=power9,  IBM 128-bit long double
>     *	Power8,  BE, --with-cpu=power8,  IBM 128-bit long double
> 
> 2023-07-10  Michael Meissner  <meissner@linux.ibm.com>
> 
> gcc/
> 
> 	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from
> 	vsx_extract_v4sf_<mode>_load.
> ---
>  gcc/config/rs6000/vsx.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index d34c3b21abe..aed450e31ec 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -3576,7 +3576,7 @@ (define_insn_and_split "vsx_extract_v4sf"
>    [(set_attr "length" "8")
>     (set_attr "type" "fp")])
>  
> -(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
> +(define_insn_and_split "*vsx_extract_v4sf_load"
>    [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
>  	(vec_select:SF
>  	 (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")