From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id BD5B63858D1E for ; Sat, 9 Sep 2023 08:09:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BD5B63858D1E Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1694246995; bh=W0Rz1HSNrNEkvWRxwUN3rRi5Il/QHISsZ8UloQ99/3s=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=cvxcU0aoCHrEutoWE/+DzL4Rpy+OQ9Hg43cDplyh9pvgCw8eflTg4RiYEGQXegzjs Zfl4LFRk7KT6YDALJjzjAba6m2nDAjVtov0J+1ZMRUb5rbBnO6o342V8RUxpxYTTO2 fW7XMRZkkPfcjNysW0xGH4m3UhZ+0pX+rwopu3XU= Received: from [IPv6:240e:358:11c0:f500:dc73:854d:832e:6] (unknown [IPv6:240e:358:11c0:f500:dc73:854d:832e:6]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 921E8659C0; Sat, 9 Sep 2023 04:09:52 -0400 (EDT) Message-ID: Subject: Re: [PATCH v1] LoongArch: Fix bug of 'di3_fake'. From: Xi Ruoyao To: Lulu Cheng , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn Date: Sat, 09 Sep 2023 16:09:47 +0800 In-Reply-To: <20230909074209.1187-1-chenglulu@loongson.cn> References: <20230909074209.1187-1-chenglulu@loongson.cn> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 MIME-Version: 1.0 X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, 2023-09-09 at 15:42 +0800, Lulu Cheng wrote: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0PR 111334 >=20 > gcc/ChangeLog: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* config/loongarch/loonga= rch.md: Fix bug of di3_fake. >=20 > gcc/testsuite/ChangeLog: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* gcc.target/loongarch/pr= 111334.c: New test. Ok. Despite I still think we should use unspec inside any_div, this should be enough to prevent the compiler from matching di3_fake. > --- > =C2=A0gcc/config/loongarch/loongarch.md=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 14 +++++-- > =C2=A0gcc/testsuite/gcc.target/loongarch/pr111334.c | 39 ++++++++++++++++= +++ > =C2=A02 files changed, 49 insertions(+), 4 deletions(-) > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/pr111334.c >=20 > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loo= ngarch.md > index 1dc6b524416..3fa32562aa6 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -72,6 +72,9 @@ (define_c_enum "unspec" [ > =C2=A0=C2=A0 UNSPEC_LUI_H_HI12 > =C2=A0=C2=A0 UNSPEC_TLS_LOW > =C2=A0 > +=C2=A0 ;; Fake div.w[u] mod.w[u] > +=C2=A0 UNSPEC_FAKE_ANY_DIV > + > =C2=A0=C2=A0 UNSPEC_SIBCALL_VALUE_MULTIPLE_INTERNAL_1 > =C2=A0=C2=A0 UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1 > =C2=A0]) > @@ -900,7 +903,7 @@ (define_expand "3" > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (match_operand:GPR 2 "regi= ster_operand")))] > =C2=A0=C2=A0 "" > =C2=A0{ > - if (GET_MODE (operands[0]) =3D=3D SImode) > + if (GET_MODE (operands[0]) =3D=3D SImode && TARGET_64BIT) > =C2=A0=C2=A0 { > =C2=A0=C2=A0=C2=A0=C2=A0 rtx reg1 =3D gen_reg_rtx (DImode); > =C2=A0=C2=A0=C2=A0=C2=A0 rtx reg2 =3D gen_reg_rtx (DImode); > @@ -938,9 +941,12 @@ (define_insn "*3" > =C2=A0(define_insn "di3_fake" > =C2=A0=C2=A0 [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r") > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(sign_extend:DI > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (any_div:SI (match_oper= and:DI 1 "register_operand" "r,r,0") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (match_operand:DI 2 "regis= ter_operand" "r,r,r"))))] > -=C2=A0 "" > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (unspec:SI > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 [(subreg:SI > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (any_= div:DI (match_operand:DI 1 "register_operand" "r,r,0") > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (match_o= perand:DI 2 "register_operand" "r,r,r")) 0)] > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 UNSPEC_FAKE_ANY_DIV)))] > +=C2=A0 "TARGET_64BIT" > =C2=A0{ > =C2=A0=C2=A0 return loongarch_output_division (".w\t%0,%1,%2", o= perands); > =C2=A0} > diff --git a/gcc/testsuite/gcc.target/loongarch/pr111334.c b/gcc/testsuit= e/gcc.target/loongarch/pr111334.c > new file mode 100644 > index 00000000000..47366afcb74 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/pr111334.c > @@ -0,0 +1,39 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > + > +unsigned > +util_next_power_of_two (unsigned x) > +{ > +=C2=A0 return (1 << __builtin_clz (x - 1)); > +} > + > +extern int create_vec_from_array (void); > + > +struct ac_shader_args { > +=C2=A0=C2=A0=C2=A0 struct { > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0unsigned char offset; > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0unsigned char size; > +=C2=A0=C2=A0=C2=A0 } args[384]; > +}; > + > +struct isel_context { > +=C2=A0=C2=A0=C2=A0 const struct ac_shader_args* args; > +=C2=A0=C2=A0=C2=A0 int arg_temps[384]; > +}; > + > + > +void > +add_startpgm (struct isel_context* ctx, unsigned short arg_count) > +{ > + > +=C2=A0 for (unsigned i =3D 0, arg =3D 0; i < arg_count; i++) > +=C2=A0=C2=A0=C2=A0 { > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned size =3D ctx->args->args[i].size= ; > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned reg =3D ctx->args->args[i].offse= t; > + > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (reg % ( 4 < util_next_power_of_two (s= ize) > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 ? 4 : util_next_power_of_two (size))) > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ctx->arg_temps[i] =3D c= reate_vec_from_array (); > +=C2=A0=C2=A0=C2=A0 } > +} > + --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University