From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from omggw0013.mail.otm.ynwl.yahoo.co.jp (omggw0013.mail.otm.yahoo.co.jp [182.22.18.27]) by sourceware.org (Postfix) with ESMTPS id C31913858C00 for ; Tue, 30 May 2023 09:27:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C31913858C00 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=yahoo.co.jp Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=yahoo.co.jp X-YMail-OSG: 8X2w0TsVM1nsBKr1CITLf.KA4ay2SLdmEdTYY_G_rT_rR_boWW5YegimyvdGCb0 wmd7s8ZJIm8_xM8w745cTcYJEs8zXG5xJxzi56GnsFrZr7JkB.ZubER3w96eA04f67ZiKFtYNmFi yqehyvUf7DRim9SUmfHnAfM4AjH_9FE0Isb8RywYZz.ZLlUyiMD8G115kBSq7PIcaOdFAgJhcNnX Pg95sFwl3nKpaf8vXVagLAwq5EMleSN_kv77987DNVE8YzC0wjbzeRxXo4iEFWDmSTEP2SL.0jnN 3tSFMKyhGMLDYgwP4oErHwWQ8FrSLcEa671K9Ug_XktUb0wk3GXz4ZwYwLedm_r0I9ZzAAYJWjHS 0_egMdzxIQDDrkaCwPU3c8rFoPUfRzxvm4xaRD6PXfj.voqtuy8uVypZ8v51.L48fpqBWsS.vzAM IsKsqrOzzVIwo9UOUUXbN7nHZWCIGmS4lMfiRfonymp5g59UC2iupX.fMudr7sk8lty2sQP4LuAV .wNlOiDWSiBHTUjyiOuKZtlhj35DXznEGHxO8XBBeKMIjtOdmI_65OaIBpPBkHLcAn6jf71EcLD6 axeGRgZIHwNjNh6yPmSztcSw3j52TTHK5XLaoMsSSJk_tszryq3vBlKThhjorzuPfHLM7Hvs.6vr mRgTB01cCihZgZFFRoLNHqsXS9mouZ932TxWD8KIdT06pC3SlWlX.KLw1Y8vJbGgmnlnN4043ghd mjwgxmJ0pSyj95BK2jJVESCKNp4AilXqw1jaA0fVZaY6RiXuMQuW5rravQ8tBKc2623A08V1dwi8 BzjfDMem.3aJZqLG07WAdgarHE8qGqiBsv2dZmxU7VLtjEYlFlwCO0R3R7vrpt.wm_DDcBRFa4uT lYMofD2lOegJVH4Twzk0oWPzH6wJjJpkc.xvzNaCFoyNspJvNmNvbzTvIIjWeENT2S8SfsUPzbJr dQrApUDhlegGCzKgr5zFswGtXnUCVOQmEKeylvUgooe2SYy2D1Od1mw4IVKFzhYQV8lo- Received: from sonicgw.mail.yahoo.co.jp by sonicconh6001.mail.ssk.yahoo.co.jp with HTTP; Tue, 30 May 2023 09:27:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1685438826; s=yj20110701; d=yahoo.co.jp; h=Message-ID:Date:MIME-Version:To:Cc:From:Subject:Content-Type:Content-Transfer-Encoding:References; bh=gD+VbYKaB5cJnEiPsVmesRguqQ59XI782efvghBdD+o=; b=QjWiJCoEHQWYgjNTMui/8F4tZsKsIx6KXbGjgKXLl+Y+bytX5XW40ckp9n3Vqdh6 y1EesIgxq10aQIw4WCruWh91Y0vXcVtis4hTF2d8wABHNK5zjnjF1dcmR8tXc0qP7wA 2020N+0hGqJkzr2csyDmKUn4J1eK4wmlABzEwvfU= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=yj20110701; d=yahoo.co.jp; h=Message-ID:Date:MIME-Version:Cc:From:Content-Type:Content-Transfer-Encoding:References; b=lmHHtS7U8Wdm1QQ5rn/gkb9SR1X/3H+aN7HOHQ5gXRUfZ7Kpt1bafYiQy37LxP5L FM1b51O7aJ2oi4+QNm/7pV6AwHWNybpbL4HAsuRrhCXiPiVzxZn2P9uRRstGfaKe/Np rs7SJjjyixFvxwvlTyUbH3HCtfPKPkWKhZOm+j4w=; Received: by smtphe5007.mail.kks.ynwp.yahoo.co.jp (YJ Hermes SMTP Server) with ESMTPA ID 3cad198af2e9f658f090f8a7eb20f35f; Tue, 30 May 2023 18:27:03 +0900 (JST) Message-ID: Date: Tue, 30 May 2023 18:25:18 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 To: GCC Patches Cc: Max Filippov From: Takayuki 'January June' Suwa Subject: [PATCH 1/3] xtensa: Improve "*shlrd_reg" insn pattern and its variant Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit References: X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_STOCKGEN,NML_ADSP_CUSTOM_MED,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The insn "*shlrd_reg" shifts two registers with a funnel shifter by the third register to get a single word result: reg0 = (reg1 SHIFT_OP0 reg3) BIT_JOIN_OP (reg2 SHIFT_OP1 (32 - reg3)) where the funnel left shift is SHIFT_OP0 := ASHIFT, SHIFT_OP1 := LSHIFTRT and its right shift is SHIFT_OP0 := LSHIFTRT, SHIFT_OP1 := ASHIFT, respectively. And also, BIT_JOIN_OP can be either PLUS or IOR in either shift direction. [(set (match_operand:SI 0 "register_operand" "=a") (match_operator:SI 6 "xtensa_bit_join_operator" [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 3 "register_operand" "r")]) (match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 2 "register_operand" "r") (neg:SI (match_dup 3))])]))] Although the RTL matching template can express it as above, there is no way of direcing that the operator (operands[6]) that combines the two individual shifts is commutative. Thus, if multiple insn sequences matching the above pattern appear adjacently, the combiner may accidentally mix them up and get partial results. This patch adds a new insn-and-split pattern with the two sides swapped representation of the bit-combining operation that was lacking and described above. And also changes the other "*shlrd" variants from previously describing the arbitraryness of bit-combining operations with code iterators to a combination of the match_operator and the predicate above. gcc/ChangeLog: * config/xtensa/predicates.md (xtensa_bit_join_operator): New predicate. * config/xtensa/xtensa.md (ior_op): Remove. (*shlrd_reg): Rename from "*shlrd_reg_", and add the insn_and_split pattern of the same name to express and capture the bit-combining operation with both sides swapped. In addition, replace use of code iterator with new operator predicate. (*shlrd_const, *shlrd_per_byte): Likewise regarding the code iterator. --- gcc/config/xtensa/predicates.md | 3 ++ gcc/config/xtensa/xtensa.md | 81 ++++++++++++++++++++++----------- 2 files changed, 58 insertions(+), 26 deletions(-) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index 5faf1be8c15..a3575a68892 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -200,6 +200,9 @@ (define_predicate "xtensa_shift_per_byte_operator" (match_code "ashift,ashiftrt,lshiftrt")) +(define_predicate "xtensa_bit_join_operator" + (match_code "plus,ior")) + (define_predicate "tls_symbol_operand" (and (match_code "symbol_ref") (match_test "SYMBOL_REF_TLS_MODEL (op) != 0"))) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 57e50911f52..eda1353894b 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -87,9 +87,6 @@ ;; the same template. (define_mode_iterator HQI [HI QI]) -;; This code iterator is for *shlrd and its variants. -(define_code_iterator ior_op [ior plus]) - ;; Attributes. @@ -1682,21 +1679,22 @@ (set_attr "mode" "SI") (set_attr "length" "9")]) -(define_insn "*shlrd_reg_" +(define_insn "*shlrd_reg" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + (match_operator:SI 6 "xtensa_bit_join_operator" + [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r")]) - (match_operator:SI 5 "logical_shift_operator" - [(match_operand:SI 3 "register_operand" "r") - (neg:SI (match_dup 2))])))] + (match_operand:SI 3 "register_operand" "r")]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 2 "register_operand" "r") + (neg:SI (match_dup 3))])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" { switch (xtensa_shlrd_which_direction (operands[4], operands[5])) { - case ASHIFT: return "ssl\t%2\;src\t%0, %1, %3"; - case LSHIFTRT: return "ssr\t%2\;src\t%0, %3, %1"; + case ASHIFT: return "ssl\t%3\;src\t%0, %1, %2"; + case LSHIFTRT: return "ssr\t%3\;src\t%0, %2, %1"; default: gcc_unreachable (); } } @@ -1704,14 +1702,42 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) -(define_insn "*shlrd_const_" +(define_insn_and_split "*shlrd_reg" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 6 "xtensa_bit_join_operator" + [(match_operator:SI 4 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (neg:SI (match_operand:SI 3 "register_operand" "r"))]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 2 "register_operand" "r") + (match_dup 3)])]))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[5], operands[4]) != UNKNOWN" + "#" + "&& 1" + [(set (match_dup 0) + (match_op_dup 6 + [(match_op_dup 5 + [(match_dup 2) + (match_dup 3)]) + (match_op_dup 4 + [(match_dup 1) + (neg:SI (match_dup 3))])]))] + "" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + + +(define_insn "*shlrd_const" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + (match_operator:SI 7 "xtensa_bit_join_operator" + [(match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 3 "const_int_operand" "i")]) - (match_operator:SI 6 "logical_shift_operator" + (match_operator:SI 6 "logical_shift_operator" [(match_operand:SI 2 "register_operand" "r") - (match_operand:SI 4 "const_int_operand" "i")])))] + (match_operand:SI 4 "const_int_operand" "i")])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN && IN_RANGE (INTVAL (operands[3]), 1, 31) @@ -1729,16 +1755,17 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) -(define_insn "*shlrd_per_byte_" +(define_insn "*shlrd_per_byte" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + (match_operator:SI 6 "xtensa_bit_join_operator" + [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 3))]) - (match_operator:SI 5 "logical_shift_operator" + (match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 3 "register_operand" "r") (neg:SI (ashift:SI (match_dup 2) - (const_int 3)))])))] + (const_int 3)))])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" { @@ -1753,32 +1780,34 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) -(define_insn_and_split "*shlrd_per_byte__omit_AND" +(define_insn_and_split "*shlrd_per_byte_omit_AND" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + (match_operator:SI 7 "xtensa_bit_join_operator" + [(match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 3)) (match_operand:SI 4 "const_int_operand" "i"))]) - (match_operator:SI 6 "logical_shift_operator" + (match_operator:SI 6 "logical_shift_operator" [(match_operand:SI 3 "register_operand" "r") (neg:SI (and:SI (ashift:SI (match_dup 2) (const_int 3)) - (match_dup 4)))])))] + (match_dup 4)))])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN && (INTVAL (operands[4]) & 0x1f) == 3 << 3" "#" "&& 1" [(set (match_dup 0) - (ior_op:SI (match_op_dup 5 + (match_op_dup 7 + [(match_op_dup 5 [(match_dup 1) (ashift:SI (match_dup 2) (const_int 3))]) - (match_op_dup 6 + (match_op_dup 6 [(match_dup 3) (neg:SI (ashift:SI (match_dup 2) - (const_int 3)))])))] + (const_int 3)))])]))] "" [(set_attr "type" "arith") (set_attr "mode" "SI") -- 2.30.2