From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id D205F3858D20 for ; Tue, 8 Aug 2023 19:55:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D205F3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="6.01,157,1684828800"; d="scan'208";a="15761289" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 08 Aug 2023 11:55:42 -0800 IronPort-SDR: /EgfyXtRt8A92mjyPtYaIAEJV8iqaELnUfAu7qk1rbTmxDkiDGcQpoWU1+AkUwGT4jzv3LvH12 hR/Tit9SMWMw6dCfDJtTW/RWtk49USfVWr6DiB2mOr3fbWKIZJPULPK5KHAhrBjuIAHbADpAGw iBtNhoGre4qDImitOlmP6/wHZx1+pZAknbZSaIXTu6bB0eRX+eJSbvFN8cgrEtE7X+IKD7mYAN botw1wBLuWv6e7wSBe83PR6qmALmr63YJN2qUTWdodzQUu4hVLiT4v1Wiw9qKcIoGO6Gg/FVzW bxc= Date: Tue, 8 Aug 2023 19:55:38 +0000 From: Joseph Myers To: Haochen Jiang CC: , , Subject: Re: Intel AVX10.1 Compiler Design and Support In-Reply-To: <20230808071312.1569559-1-haochen.jiang@intel.com> Message-ID: References: <20230808071312.1569559-1-haochen.jiang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-13.mgc.mentorg.com (139.181.222.13) To svr-ies-mbx-10.mgc.mentorg.com (139.181.222.10) X-Spam-Status: No, score=-3104.9 required=5.0 tests=BAYES_00,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Do you have any comments on the interaction of AVX10 with the micro-architecture levels defined in the ABI (and supported with glibc-hwcaps directories in glibc)? Given that the levels are cumulative, should we take it that any future levels will be ones supporting 512-bit vector width for AVX10 (because x86-64-v4 requires the current AVX512F, AVX512BW, AVX512CD, AVX512DQ and AVX512VL) - and so any future processors that only support 256-bit vector width will be considered to match the x86-64-v3 micro-architecture level but not any higher level? -- Joseph S. Myers joseph@codesourcery.com