From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 67327385828B for ; Wed, 26 Jun 2024 07:53:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 67327385828B Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 67327385828B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719388432; cv=none; b=Mkv9wQqP1eU/0kmDmBtMzDbMM/YpdcTdDg4m1QOKj1C3OISk93V2kAc7z2nFlVPCP+yn9FhrU9AmYDzIL0pTMmc6yU3f2m0gJfBLv++5BBDZLr471M5PXi+ye/OdpzqwxiGgmqF0Oy7cnleYalVI4Mjvpz/NyUNEThCEuRFC7tk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719388432; c=relaxed/simple; bh=TnIAMS9k5+GhVd/ReqUcRPi/SWD7ZCPI0Q0RE//4x+U=; h=DKIM-Signature:Message-ID:Subject:From:To:Date:MIME-Version; b=eQgZCm9csV924Cm/cfhYvSaSeCywSDlmtIEZ5RCfisS0vM1ryRa5r0zOfo9JLBPjqvg2m+NQB8i0fms78Mcm1xK69hsiIPoN/6RWGANHzGtpF1O7r3XwpMeV3eDosASGwchDqYhD1w9EYZBjlcgVQsHN8jjAZHqrGdXSOw9gY+w= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1719388429; bh=TnIAMS9k5+GhVd/ReqUcRPi/SWD7ZCPI0Q0RE//4x+U=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=IJmv73bUv6HEwSsonY4ZrSxM7arfArDwUzyCP+iLMoU31GPKPS2XZyphgF7zSDPzT fBL0fmHcKDMIZt3KMgXvyzd+REwrqxavcGxsyqbInFDeWs4rt6NBp83trbq7MUzmpI 9gC+xyoKzO/N5BurbyCMXNzG3IHgeEqSdioNN2pc= Received: from [192.168.124.13] (unknown [113.200.174.6]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id D9F8066B4D; Wed, 26 Jun 2024 03:53:47 -0400 (EDT) Message-ID: Subject: Ping: [PATCH v2] LoongArch: Tweak IOR rtx_cost for bstrins From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn Date: Wed, 26 Jun 2024 15:53:44 +0800 In-Reply-To: <20240615175102.1837-1-xry111@xry111.site> References: <20240615175102.1837-1-xry111@xry111.site> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.2 MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Ping. On Sun, 2024-06-16 at 01:50 +0800, Xi Ruoyao wrote: > Consider >=20 > =C2=A0=C2=A0=C2=A0 c &=3D 0xfff; > =C2=A0=C2=A0=C2=A0 a &=3D ~0xfff; > =C2=A0=C2=A0=C2=A0 b &=3D ~0xfff; > =C2=A0=C2=A0=C2=A0 a |=3D c; > =C2=A0=C2=A0=C2=A0 b |=3D c; >=20 > This can be done with 2 bstrins instructions.=C2=A0 But we need to > recognize > it in loongarch_rtx_costs or the compiler will not propagate "c & > 0xfff" > forward. >=20 > gcc/ChangeLog: >=20 > * config/loongarch/loongarch.cc: > (loongarch_use_bstrins_for_ior_with_mask): Split the main > logic > into ... > (loongarch_use_bstrins_for_ior_with_mask_1): ... here. > (loongarch_rtx_costs): Special case for IOR those can be > implemented with bstrins. >=20 > gcc/testsuite/ChangeLog; >=20 > * gcc.target/loongarch/bstrins-3.c: New test. > --- >=20 > Bootstrapped and regtested on loongarch64-linux-gnu.=C2=A0 Ok for trunk? >=20 > =C2=A0gcc/config/loongarch/loongarch.cc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 73 ++++++++++++++---- > - > =C2=A0.../gcc.target/loongarch/bstrins-3.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 | 16 ++++ > =C2=A02 files changed, 72 insertions(+), 17 deletions(-) > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/bstrins-3.c >=20 > diff --git a/gcc/config/loongarch/loongarch.cc > b/gcc/config/loongarch/loongarch.cc > index 6ec3ee62502..256b76d044b 100644 > --- a/gcc/config/loongarch/loongarch.cc > +++ b/gcc/config/loongarch/loongarch.cc > @@ -3681,6 +3681,27 @@ loongarch_set_reg_reg_piece_cost (machine_mode > mode, unsigned int units) > =C2=A0=C2=A0 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / u= nits); > =C2=A0} > =C2=A0 > +static int > +loongarch_use_bstrins_for_ior_with_mask_1 (machine_mode mode, > + =C2=A0=C2=A0 unsigned HOST_WIDE_INT > mask1, > + =C2=A0=C2=A0 unsigned HOST_WIDE_INT > mask2) > +{ > +=C2=A0 if (mask1 !=3D ~mask2 || !mask1 || !mask2) > +=C2=A0=C2=A0=C2=A0 return 0; > + > +=C2=A0 /* Try to avoid a right-shift.=C2=A0 */ > +=C2=A0 if (low_bitmask_len (mode, mask1) !=3D -1) > +=C2=A0=C2=A0=C2=A0 return -1; > + > +=C2=A0 if (low_bitmask_len (mode, mask2 >> (ffs_hwi (mask2) - 1)) !=3D -= 1) > +=C2=A0=C2=A0=C2=A0 return 1; > + > +=C2=A0 if (low_bitmask_len (mode, mask1 >> (ffs_hwi (mask1) - 1)) !=3D -= 1) > +=C2=A0=C2=A0=C2=A0 return -1; > + > +=C2=A0 return 0; > +} > + > =C2=A0/* Return the cost of moving between two registers of mode MODE.=C2= =A0 */ > =C2=A0 > =C2=A0static int > @@ -3812,6 +3833,38 @@ loongarch_rtx_costs (rtx x, machine_mode mode, > int outer_code, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Fall through.=C2=A0 */ > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0 case IOR: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 { > + rtx op[2] =3D {XEXP (x, 0), XEXP (x, 1)}; > + if (GET_CODE (op[0]) =3D=3D AND && GET_CODE (op[1]) =3D=3D AND > + =C2=A0=C2=A0=C2=A0 && (mode =3D=3D SImode || (TARGET_64BIT && mode =3D= =3D DImode))) > + =C2=A0 { > + =C2=A0=C2=A0=C2=A0 rtx rtx_mask0 =3D XEXP (op[0], 1), rtx_mask1 =3D XEX= P (op[1], > 1); > + =C2=A0=C2=A0=C2=A0 if (CONST_INT_P (rtx_mask0) && CONST_INT_P (rtx_mask= 1)) > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 { > + unsigned HOST_WIDE_INT mask0 =3D UINTVAL (rtx_mask0); > + unsigned HOST_WIDE_INT mask1 =3D UINTVAL (rtx_mask1); > + if (loongarch_use_bstrins_for_ior_with_mask_1 (mode, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mask0, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > mask1)) > + =C2=A0 { > + =C2=A0=C2=A0=C2=A0 /* A bstrins instruction */ > + =C2=A0=C2=A0=C2=A0 *total =3D COSTS_N_INSNS (1); > + > + =C2=A0=C2=A0=C2=A0 /* A srai instruction */ > + =C2=A0=C2=A0=C2=A0 if (low_bitmask_len (mode, mask0) =3D=3D -1 > + && low_bitmask_len (mode, mask1) =3D=3D -1) > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *total +=3D COSTS_N_INSNS (1); > + > + =C2=A0=C2=A0=C2=A0 for (int i =3D 0; i < 2; i++) > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *total +=3D set_src_cost (XEXP (op[i], = 0), mode, > speed); > + > + =C2=A0=C2=A0=C2=A0 return true; > + =C2=A0 } > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > + =C2=A0 } > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > + > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Fall through.=C2=A0 */ > =C2=A0=C2=A0=C2=A0=C2=A0 case XOR: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Double-word operations use two si= ngle-word operations.=C2=A0 */ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *total =3D loongarch_binary_cost (x,= COSTS_N_INSNS (1), > COSTS_N_INSNS (2), > @@ -5796,23 +5849,9 @@ bool loongarch_pre_reload_split (void) > =C2=A0int > =C2=A0loongarch_use_bstrins_for_ior_with_mask (machine_mode mode, rtx *op= ) > =C2=A0{ > -=C2=A0 unsigned HOST_WIDE_INT mask1 =3D UINTVAL (op[2]); > -=C2=A0 unsigned HOST_WIDE_INT mask2 =3D UINTVAL (op[4]); > - > -=C2=A0 if (mask1 !=3D ~mask2 || !mask1 || !mask2) > -=C2=A0=C2=A0=C2=A0 return 0; > - > -=C2=A0 /* Try to avoid a right-shift.=C2=A0 */ > -=C2=A0 if (low_bitmask_len (mode, mask1) !=3D -1) > -=C2=A0=C2=A0=C2=A0 return -1; > - > -=C2=A0 if (low_bitmask_len (mode, mask2 >> (ffs_hwi (mask2) - 1)) !=3D -= 1) > -=C2=A0=C2=A0=C2=A0 return 1; > - > -=C2=A0 if (low_bitmask_len (mode, mask1 >> (ffs_hwi (mask1) - 1)) !=3D -= 1) > -=C2=A0=C2=A0=C2=A0 return -1; > - > -=C2=A0 return 0; > +=C2=A0 return loongarch_use_bstrins_for_ior_with_mask_1 (mode, > + =C2=A0=C2=A0=C2=A0 UINTVAL (op[2]), > + =C2=A0=C2=A0=C2=A0 UINTVAL (op[4])); > =C2=A0} > =C2=A0 > =C2=A0/* Rewrite a MEM for simple load/store under -mexplicit-relocs=3Dau= to > diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-3.c > b/gcc/testsuite/gcc.target/loongarch/bstrins-3.c > new file mode 100644 > index 00000000000..13762bdef42 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/bstrins-3.c > @@ -0,0 +1,16 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -fdump-rtl-final" } */ > +/* { dg-final { scan-rtl-dump-times "insv\[sd\]i" 2 "final" } } */ > + > +struct X { > +=C2=A0 long a, b; > +}; > + > +struct X > +test (long a, long b, long c) > +{ > +=C2=A0 c &=3D 0xfff; > +=C2=A0 a &=3D ~0xfff; > +=C2=A0 b &=3D ~0xfff; > +=C2=A0 return (struct X){.a =3D a | c, .b =3D b | c};=20 > +} --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University