* [PATCH 00/12] rs6000: Another batch of constraint simplification
@ 2019-06-04 23:20 Segher Boessenkool
2019-06-04 23:20 ` [PATCH 01/12] rs6000: Simplify VS[ra]* for VSX_[BDF] Segher Boessenkool
` (11 more replies)
0 siblings, 12 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
Tested as before. Committing to trunk.
Segher
gcc/config/rs6000/constraints.md | 9 -
gcc/config/rs6000/rs6000.c | 19 -
gcc/config/rs6000/rs6000.h | 3 -
gcc/config/rs6000/rs6000.md | 105 ++--
gcc/config/rs6000/vsx.md | 561 ++++++++++-----------
gcc/doc/md.texi | 14 +-
.../gcc.target/powerpc/direct-move-double1.c | 1 -
.../gcc.target/powerpc/direct-move-double2.c | 1 -
.../gcc.target/powerpc/direct-move-float1.c | 1 -
.../gcc.target/powerpc/direct-move-float2.c | 1 -
.../gcc.target/powerpc/direct-move-vint1.c | 1 -
.../gcc.target/powerpc/direct-move-vint2.c | 1 -
12 files changed, 312 insertions(+), 405 deletions(-)
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 01/12] rs6000: Simplify VS[ra]* for VSX_[BDF]
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
@ 2019-06-04 23:20 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 10/12] rs6000: Add p9kf and p9tf isa values Segher Boessenkool
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
When used in VSX_B, VSX_D, or VSX_F, both <VSr> and <VSa> are always
just "wa" now. Similarly <VSr2> and <VSr3>. The former of those is
always "wa", so we can remove the mode attribute completely.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md (define_mode_attr VSr2): Delete.
(rest of file): Replace all <VSa>, <VSr>, <VSr2>, and <VSr3> that are
used with VSX_B, VSX_D, or VSX_F, with just "wa".
---
gcc/config/rs6000/vsx.md | 207 ++++++++++++++++++++++-------------------------
1 file changed, 97 insertions(+), 110 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4450537..11e50bf 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -123,16 +123,7 @@ (define_mode_attr VSr [(V16QI "v")
(TI "wa")])
;; Map the register class used for float<->int conversions (floating point side)
-;; VSr2 is the preferred register class, VSr3 is any register class that will
-;; hold the data
-(define_mode_attr VSr2 [(V2DF "wa")
- (V4SF "wa")
- (DF "wa")
- (SF "ww")
- (DI "wa")
- (KF "wq")
- (TF "wp")])
-
+;; VSr3 is any register class that will hold the data
(define_mode_attr VSr3 [(V2DF "wa")
(V4SF "wa")
(DF "wa")
@@ -429,7 +420,7 @@ (define_c_enum "unspec"
;; The patterns for LE permuted loads and stores come before the general
;; VSX moves so they match first.
(define_insn_and_split "*vsx_le_perm_load_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"#"
@@ -644,7 +635,7 @@ (define_insn_and_split "*vsx_le_perm_load_v16qi"
(define_insn "*vsx_le_perm_store_<mode>"
[(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "=Z")
- (match_operand:VSX_D 1 "vsx_register_operand" "+<VSa>"))]
+ (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"#"
[(set_attr "type" "vecstore")
@@ -1599,25 +1590,25 @@ (define_insn "*vsx_st_elemrev_v16qi_internal"
;; instructions are now combined with the insn for the traditional floating
;; point unit.
(define_insn "*vsx_add<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvadd<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_sub<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa>")
+ (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsub<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_mul<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmul<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
@@ -1663,9 +1654,9 @@ (define_insn_and_split "vsx_mul_v2di"
[(set_attr "type" "mul")])
(define_insn "*vsx_div<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvdiv<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_div>")])
@@ -1794,71 +1785,71 @@ (define_expand "vsx_tdiv<mode>3_fe"
})
(define_insn "*vsx_tdiv<mode>3_internal"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=x")
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_B 2 "vsx_register_operand" "wa")]
UNSPEC_VSX_TDIV))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tdiv<VSs> %0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fre<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_FRES))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvre<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_neg<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvneg<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_abs<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvabs<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_nabs<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(neg:VSX_F
(abs:VSX_F
- (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>"))))]
+ (match_operand:VSX_F 1 "vsx_register_operand" "wa"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvnabs<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_smax<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmax<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_smin<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmin<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_sqrt<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsqrt<VSs> %x0,%x1"
[(set_attr "type" "<VStype_sqrt>")])
(define_insn "*vsx_rsqrte<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_RSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvrsqrte<VSs> %x0,%x1"
@@ -1891,8 +1882,8 @@ (define_expand "vsx_tsqrt<mode>2_fe"
})
(define_insn "*vsx_tsqrt<mode>2_internal"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=x")
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_TSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tsqrt<VSs> %0,%x1"
@@ -1929,32 +1920,28 @@ (define_insn "*vsx_fmav2df4"
[(set_attr "type" "vecdouble")])
(define_insn "*vsx_fms<mode>4"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa,wa")
(fma:VSX_F
- (match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,<VSa>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0")
+ (match_operand:VSX_F 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa,0")
(neg:VSX_F
- (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))]
+ (match_operand:VSX_F 3 "vsx_register_operand" "0,wa"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
xvmsuba<VSs> %x0,%x1,%x2
- xvmsubm<VSs> %x0,%x1,%x3
- xvmsuba<VSs> %x0,%x1,%x2
xvmsubm<VSs> %x0,%x1,%x3"
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfma<mode>4"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa,wa")
(neg:VSX_F
(fma:VSX_F
- (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,<VSa>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0")
- (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))]
+ (match_operand:VSX_F 1 "vsx_register_operand" "wa,wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa,0")
+ (match_operand:VSX_F 3 "vsx_register_operand" "0,wa"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
xvnmadda<VSs> %x0,%x1,%x2
- xvnmaddm<VSs> %x0,%x1,%x3
- xvnmadda<VSs> %x0,%x1,%x2
xvnmaddm<VSs> %x0,%x1,%x3"
[(set_attr "type" "<VStype_mul>")])
@@ -1989,25 +1976,25 @@ (define_insn "*vsx_nfmsv2df4"
;; Vector conditional expressions (no scalar version for these instructions)
(define_insn "vsx_eq<mode>"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpeq<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_gt<mode>"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpgt<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_ge<mode>"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpge<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
@@ -2017,10 +2004,10 @@ (define_insn "*vsx_ge<mode>"
(define_insn "*vsx_eq_<mode>_p"
[(set (reg:CC CR6_REGNO)
(unspec:CC
- [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
+ [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
UNSPEC_PREDICATE))
- (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(eq:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -2030,10 +2017,10 @@ (define_insn "*vsx_eq_<mode>_p"
(define_insn "*vsx_gt_<mode>_p"
[(set (reg:CC CR6_REGNO)
(unspec:CC
- [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
+ [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
UNSPEC_PREDICATE))
- (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(gt:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -2043,10 +2030,10 @@ (define_insn "*vsx_gt_<mode>_p"
(define_insn "*vsx_ge_<mode>_p"
[(set (reg:CC CR6_REGNO)
(unspec:CC
- [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
+ [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
UNSPEC_PREDICATE))
- (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(ge:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -2078,10 +2065,10 @@ (define_insn "*vsx_xxsel<mode>_uns"
;; Copy sign
(define_insn "vsx_copysign<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(unspec:VSX_F
- [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_F 2 "vsx_register_operand" "wa")]
UNSPEC_COPYSIGN))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcpsgn<VSs> %x0,%x2,%x1"
@@ -2094,76 +2081,76 @@ (define_insn "vsx_copysign<mode>3"
;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md
;; in allowing virtual registers.
(define_insn "vsx_float<VSi><mode>2"
- [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=<VSr>,?<VSa>")
- (float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
+ [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=wa")
+ (float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcvsx<VSc><VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_floatuns<VSi><mode>2"
- [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=<VSr>,?<VSa>")
- (unsigned_float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
+ [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=wa")
+ (unsigned_float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcvux<VSc><VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fix_trunc<mode><VSi>2"
- [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
- (fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=wa")
+ (fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fixuns_trunc<mode><VSi>2"
- [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
- (unsigned_fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=wa")
+ (unsigned_fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
;; Math rounding functions
(define_insn "vsx_x<VSv>r<VSs>i"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:VSX_B 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_ROUND_I))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>i %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_x<VSv>r<VSs>ic"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:VSX_B 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_ROUND_IC))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>ic %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_btrunc<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>iz %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_b2trunc<mode>2"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:VSX_B 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_FRIZ))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>iz %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_floor<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_FRIM))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>im %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_ceil<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_FRIP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>ip %x0,%x1"
@@ -2987,9 +2974,9 @@ (define_expand "vsx_init_v4si"
;; xxpermdi for little endian loads and stores. We need several of
;; these since the form of the PARALLEL differs by mode.
(define_insn "*vsx_xxpermdi2_le_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(vec_select:VSX_D
- (match_operand:VSX_D 1 "vsx_register_operand" "<VSa>")
+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
(parallel [(const_int 1) (const_int 0)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
"xxpermdi %x0,%x1,%x1,2"
@@ -3036,7 +3023,7 @@ (define_insn "*vsx_xxpermdi16_le_V16QI"
;; lxvd2x for little endian loads. We need several of
;; these since the form of the PARALLEL differs by mode.
(define_insn "*vsx_lxvd2x2_le_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(vec_select:VSX_D
(match_operand:VSX_D 1 "memory_operand" "Z")
(parallel [(const_int 1) (const_int 0)])))]
@@ -3087,7 +3074,7 @@ (define_insn "*vsx_lxvd2x16_le_V16QI"
(define_insn "*vsx_stxvd2x2_le_<mode>"
[(set (match_operand:VSX_D 0 "memory_operand" "=Z")
(vec_select:VSX_D
- (match_operand:VSX_D 1 "vsx_register_operand" "<VSa>")
+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
(parallel [(const_int 1) (const_int 0)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR"
"stxvd2x %x1,%y0"
@@ -3184,11 +3171,11 @@ (define_expand "vsx_set_<mode>"
;; register was picked. Limit the scalar value to FPRs for now.
(define_insn "vsx_extract_<mode>"
- [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d, wr, wr")
+ [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d, wr, wr")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>, <VSa>, wa, wa")
+ (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa")
(parallel
- [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))]
+ [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
int element = INTVAL (operands[2]);
@@ -4103,7 +4090,7 @@ (define_expand "vsx_splat_<mode>"
})
(define_insn "vsx_splat_<mode>_reg"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSX_D:VSa>,we")
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa,we")
(vec_duplicate:VSX_D
(match_operand:<VS_scalar> 1 "gpc_reg_operand" "wa,b")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -4112,8 +4099,8 @@ (define_insn "vsx_splat_<mode>_reg"
mtvsrdd %x0,%1,%1"
[(set_attr "type" "vecperm")])
-(define_insn "vsx_splat_<VSX_D:mode>_mem"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSX_D:VSa>")
+(define_insn "vsx_splat_<mode>_mem"
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(vec_duplicate:VSX_D
(match_operand:<VSX_D:VS_scalar> 1 "memory_operand" "Z")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 03/12] rs6000: Remove Ftrad, Fvsx, Fs; add s and sd
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (10 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 08/12] rs6000: <VSs> -> <sd>p Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This removes the <Ftrad>, <Fvsx>, and <Fs> mode attributes, and creates
new <sd> and <s> mode attributes instead. <sd> is either "s" or "d",
depending on whether the mode is single-precision or double-precision
floating point; and <s> is either "s" or nothing.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (SFDF, SFDF2): Adjust comments.
(define_mode_attr sd): New.
(define_mode_attr s): New.
(define_mode_attr Ftrad): Delete.
(define_mode_attr Fvsx): Delete.
(define_mode_attr Fs): Delete.
(rest of file): Use the new mode attributes.
* config.rs6000/vsx.md: Use the new mode attributes.
---
gcc/config/rs6000/rs6000.md | 86 +++++++++++++++++++++------------------------
gcc/config/rs6000/vsx.md | 8 ++---
2 files changed, 45 insertions(+), 49 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f596987..c0a7f76 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -486,13 +486,18 @@ (define_mode_iterator DIFD [DI DF DD])
; Iterator for reciprocal estimate instructions
(define_mode_iterator RECIPF [SF DF V4SF V2DF])
-; Iterator for just SF/DF
+; SFmode or DFmode.
(define_mode_iterator SFDF [SF DF])
-; Like SFDF, but a different name to match conditional move where the
-; comparison operands may be a different mode than the input operands.
+; And again, for when we need two FP modes in a pattern.
(define_mode_iterator SFDF2 [SF DF])
+; A generic s/d attribute, for sp/dp for example.
+(define_mode_attr sd [(SF "s") (DF "d")])
+
+; "s" or nothing, for fmuls/fmul for example.
+(define_mode_attr s [(SF "s") (DF "")])
+
; Iterator for 128-bit floating point that uses the IBM double-double format
(define_mode_iterator IBM128 [(IF "FLOAT128_IBM_P (IFmode)")
(TF "FLOAT128_IBM_P (TFmode)")])
@@ -513,12 +518,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
; Iterator for ISA 3.0 supported floating point types
(define_mode_iterator FP_ISA3 [SF DF])
-; SF/DF suffix for traditional floating instructions
-(define_mode_attr Ftrad [(SF "s") (DF "")])
-
-; SF/DF suffix for VSX instructions
-(define_mode_attr Fvsx [(SF "sp") (DF "dp")])
-
; SF/DF constraint for arithmetic on traditional floating point registers
(define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
@@ -531,9 +530,6 @@ (define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
-; s/d suffix for things like sdiv/ddiv
-(define_mode_attr Fs [(SF "s") (DF "d")])
-
; FRE/FRES support
(define_mode_attr Ffre [(SF "fres") (DF "fre")])
(define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
@@ -4638,8 +4634,8 @@ (define_insn "*add<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fadd<Ftrad> %0,%1,%2
- xsadd<Fvsx> %x0,%x1,%x2"
+ fadd<s> %0,%1,%2
+ xsadd<sd>p %x0,%x1,%x2"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -4656,8 +4652,8 @@ (define_insn "*sub<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fsub<Ftrad> %0,%1,%2
- xssub<Fvsx> %x0,%x1,%x2"
+ fsub<s> %0,%1,%2
+ xssub<sd>p %x0,%x1,%x2"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -4674,8 +4670,8 @@ (define_insn "*mul<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fmul<Ftrad> %0,%1,%2
- xsmul<Fvsx> %x0,%x1,%x2"
+ fmul<s> %0,%1,%2
+ xsmul<sd>p %x0,%x1,%x2"
[(set_attr "type" "dmul")
(set_attr "isa" "*,<Fisa>")])
@@ -4700,9 +4696,9 @@ (define_insn "*div<mode>3_fpr"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
- fdiv<Ftrad> %0,%1,%2
- xsdiv<Fvsx> %x0,%x1,%x2"
- [(set_attr "type" "<Fs>div")
+ fdiv<s> %0,%1,%2
+ xsdiv<sd>p %x0,%x1,%x2"
+ [(set_attr "type" "<sd>div")
(set_attr "isa" "*,<Fisa>")])
(define_insn "*sqrt<mode>2_internal"
@@ -4710,9 +4706,9 @@ (define_insn "*sqrt<mode>2_internal"
(sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
"@
- fsqrt<Ftrad> %0,%1
- xssqrt<Fvsx> %x0,%x1"
- [(set_attr "type" "<Fs>sqrt")
+ fsqrt<s> %0,%1
+ xssqrt<sd>p %x0,%x1"
+ [(set_attr "type" "<sd>sqrt")
(set_attr "isa" "*,<Fisa>")])
(define_expand "sqrt<mode>2"
@@ -4733,14 +4729,14 @@ (define_expand "sqrt<mode>2"
})
;; Floating point reciprocal approximation
-(define_insn "fre<Fs>"
+(define_insn "fre<sd>"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
UNSPEC_FRES))]
"TARGET_<FFRE>"
"@
- fre<Ftrad> %0,%1
- xsre<Fvsx> %x0,%x1"
+ fre<s> %0,%1
+ xsre<sd>p %x0,%x1"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -4750,8 +4746,8 @@ (define_insn "*rsqrt<mode>2"
UNSPEC_RSQRT))]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
"@
- frsqrte<Ftrad> %0,%1
- xsrsqrte<Fvsx> %x0,%x1"
+ frsqrte<s> %0,%1
+ xsrsqrte<sd>p %x0,%x1"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>")])
@@ -9390,8 +9386,8 @@ (define_insn "*mov<mode>_update1"
&& (!avoiding_indexed_address_p (<MODE>mode)
|| !gpc_reg_operand (operands[2], Pmode))"
"@
- lf<Fs>ux %3,%0,%2
- lf<Fs>u %3,%2(%0)"
+ lf<sd>ux %3,%0,%2
+ lf<sd>u %3,%2(%0)"
[(set_attr "type" "fpload")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")
@@ -9407,8 +9403,8 @@ (define_insn "*mov<mode>_update2"
&& (!avoiding_indexed_address_p (<MODE>mode)
|| !gpc_reg_operand (operands[2], Pmode))"
"@
- stf<Fs>ux %3,%0,%2
- stf<Fs>u %3,%2(%0)"
+ stf<sd>ux %3,%0,%2
+ stf<sd>u %3,%2(%0)"
[(set_attr "type" "fpstore")
(set_attr "update" "yes")
(set_attr "indexed" "yes,no")
@@ -13376,9 +13372,9 @@ (define_insn "*fma<mode>4_fpr"
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))]
"TARGET_HARD_FLOAT"
"@
- fmadd<Ftrad> %0,%1,%2,%3
- xsmadda<Fvsx> %x0,%x1,%x2
- xsmaddm<Fvsx> %x0,%x1,%x3"
+ fmadd<s> %0,%1,%2,%3
+ xsmadda<sd>p %x0,%x1,%x2
+ xsmaddm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
@@ -13400,9 +13396,9 @@ (define_insn "*fms<mode>4_fpr"
(neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
- fmsub<Ftrad> %0,%1,%2,%3
- xsmsuba<Fvsx> %x0,%x1,%x2
- xsmsubm<Fvsx> %x0,%x1,%x3"
+ fmsub<s> %0,%1,%2,%3
+ xsmsuba<sd>p %x0,%x1,%x2
+ xsmsubm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
@@ -13448,9 +13444,9 @@ (define_insn "*nfma<mode>4_fpr"
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
- fnmadd<Ftrad> %0,%1,%2,%3
- xsnmadda<Fvsx> %x0,%x1,%x2
- xsnmaddm<Fvsx> %x0,%x1,%x3"
+ fnmadd<s> %0,%1,%2,%3
+ xsnmadda<sd>p %x0,%x1,%x2
+ xsnmaddm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
@@ -13475,9 +13471,9 @@ (define_insn "*nfmssf4_fpr"
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))))]
"TARGET_HARD_FLOAT"
"@
- fnmsub<Ftrad> %0,%1,%2,%3
- xsnmsuba<Fvsx> %x0,%x1,%x2
- xsnmsubm<Fvsx> %x0,%x1,%x3"
+ fnmsub<s> %0,%1,%2,%3
+ xsnmsuba<sd>p %x0,%x1,%x2
+ xsnmsubm<sd>p %x0,%x1,%x3"
[(set_attr "type" "fp")
(set_attr "isa" "*,<Fisa>,<Fisa>")])
\f
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d349091..0e04455 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4612,7 +4612,7 @@ (define_expand "xststdcqp_<mode>"
;; (The lt bit is set if operand 1 is negative. The eq bit is set
;; if any of the conditions tested by operand 2 are satisfied.
;; The gt and unordered bits are cleared to zero.)
-(define_expand "xststdc<Fvsx>"
+(define_expand "xststdc<sd>p"
[(set (match_dup 3)
(compare:CCFP
(unspec:SFDF
@@ -4647,7 +4647,7 @@ (define_expand "xststdcnegqp_<mode>"
})
;; The VSX Scalar Test Negative Double- and Single-Precision
-(define_expand "xststdcneg<Fvsx>"
+(define_expand "xststdcneg<sd>p"
[(set (match_dup 2)
(compare:CCFP
(unspec:SFDF
@@ -4676,7 +4676,7 @@ (define_insn "*xststdcqp_<mode>"
"xststdcqp %0,%1,%2"
[(set_attr "type" "fpcompare")])
-(define_insn "*xststdc<Fvsx>"
+(define_insn "*xststdc<sd>p"
[(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP
(unspec:SFDF [(match_operand:SFDF 1 "vsx_register_operand" "wa")
@@ -4684,7 +4684,7 @@ (define_insn "*xststdc<Fvsx>"
UNSPEC_VSX_STSTDC)
(match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_VECTOR"
- "xststdc<Fvsx> %0,%x1,%2"
+ "xststdc<sd>p %0,%x1,%2"
[(set_attr "type" "fpcompare")])
;; VSX Vector Extract Exponent Double and Single Precision
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 11/12] rs6000: Remove wp and wq
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (7 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 05/12] rs6000: Simplify <VSa> for VSX_TI Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 07/12] rs6000: ww->wa in testsuite Segher Boessenkool
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
wp becomes wa with isa p9tf, and wq is replaced by wa with isa p9kf.
To manage to do that, there is the new mode attribute VSisa.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wp"):
Delete.
(define_register_constraint "wq"): Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wp and RS6000_CONSTRAINT_wq.
* config/rs6000/vsx.md (define_mode_attr VSr3): Delete.
(define_mode_attr VSa): Delete.
(define_mode_attr VSisa): New.
(rest of file): Adjust.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 6 --
gcc/config/rs6000/rs6000.c | 11 ----
gcc/config/rs6000/rs6000.h | 2 -
gcc/config/rs6000/vsx.md | 115 +++++++++++++++++++--------------------
gcc/doc/md.texi | 11 +---
5 files changed, 57 insertions(+), 88 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index b1dcee2..f047742 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -67,12 +67,6 @@ (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode
(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
-(define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]"
- "VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.")
-
-(define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]"
- "VSX register to use for IEEE 128-bit fp KFmode, or NO_REGS.")
-
(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
"General purpose register if 64-bit instructions are enabled or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index eef4572..91fafc4 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2509,8 +2509,6 @@ rs6000_debug_reg_global (void)
"v reg_class = %s\n"
"wa reg_class = %s\n"
"we reg_class = %s\n"
- "wp reg_class = %s\n"
- "wq reg_class = %s\n"
"wr reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
@@ -2520,8 +2518,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -3159,13 +3155,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_STFIWX)
rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
- if (TARGET_FLOAT128_TYPE)
- {
- rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
- if (FLOAT128_IEEE_P (TFmode))
- rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
- }
-
/* Support for new direct moves (ISA 3.0 + 64bit). */
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 102fe1c..9b2f0d8 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1257,8 +1257,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_v, /* Altivec registers */
RS6000_CONSTRAINT_wa, /* Any VSX register */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
- RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
- RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b3ebc95..f04b5fc 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -103,37 +103,25 @@ (define_mode_attr VSr [(V16QI "v")
(DI "wa")
(DF "wa")
(SF "wa")
- (TF "wp")
- (KF "wq")
+ (TF "wa")
+ (KF "wa")
(V1TI "v")
(TI "wa")])
-;; Map the register class used for float<->int conversions (floating point side)
-;; VSr3 is any register class that will hold the data
-(define_mode_attr VSr3 [(V2DF "wa")
- (V4SF "wa")
- (DF "wa")
- (SF "wa")
- (DI "wa")
- (KF "wq")
- (TF "wp")])
-
-;; The VSX register class that a type can occupy, even if it is not the
-;; preferred register class (VSr is the preferred register class that will get
-;; allocated first).
-(define_mode_attr VSa [(V16QI "wa")
- (V8HI "wa")
- (V4SI "wa")
- (V4SF "wa")
- (V2DI "wa")
- (V2DF "wa")
- (DI "wa")
- (DF "wa")
- (SF "wa")
- (V1TI "wa")
- (TI "wa")
- (TF "wp")
- (KF "wq")])
+;; What value we need in the "isa" field, to make the IEEE QP float work.
+(define_mode_attr VSisa [(V16QI "*")
+ (V8HI "*")
+ (V4SI "*")
+ (V4SF "*")
+ (V2DI "*")
+ (V2DF "*")
+ (DI "*")
+ (DF "*")
+ (SF "*")
+ (V1TI "*")
+ (TI "*")
+ (TF "p9tf")
+ (KF "p9kf")])
;; A mode attribute to disparage use of GPR registers, except for scalar
;; integer modes.
@@ -962,7 +950,7 @@ (define_insn_and_split "*vsx_le_undo_permute_<mode>"
(set_attr "type" "veclogical")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
- [(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=<VSa>,r")
+ [(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=wa,r")
(match_operand:VSX_LE_128 1 "memory_operand" "Z,Q"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"@
@@ -979,17 +967,19 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
DONE;
}
[(set_attr "type" "vecload,load")
- (set_attr "length" "8,8")])
+ (set_attr "length" "8,8")
+ (set_attr "isa" "<VSisa>,*")])
(define_insn "*vsx_le_perm_store_<mode>"
[(set (match_operand:VSX_LE_128 0 "memory_operand" "=Z,Q")
- (match_operand:VSX_LE_128 1 "vsx_register_operand" "+<VSa>,r"))]
+ (match_operand:VSX_LE_128 1 "vsx_register_operand" "+wa,r"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"@
#
#"
[(set_attr "type" "vecstore,store")
- (set_attr "length" "12,8")])
+ (set_attr "length" "12,8")
+ (set_attr "isa" "<VSisa>,*")])
(define_split
[(set (match_operand:VSX_LE_128 0 "memory_operand")
@@ -1140,12 +1130,12 @@ (define_insn_and_split "*xxspltib_<mode>_split"
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
- "=ZwO, <VSa>, <VSa>, r, we, ?wQ,
+ "=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- ?<VSa>, v, <??r>, wZ, v")
+ ?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
- "<VSa>, ZwO, <VSa>, we, r, r,
+ "wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1164,21 +1154,21 @@ (define_insn "vsx_mov<mode>_64bit"
8, 8, 8, 8, 4, 4,
4, 20, 8, 4, 4")
(set_attr "isa"
- "*, *, *, *, *, *,
+ "<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- *, *, *, *, *")])
+ <VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
- "=ZwO, <VSa>, <VSa>, ??r, ??Y, <??r>,
- wa, v, ?<VSa>, v, <??r>,
+ "=ZwO, wa, wa, ??r, ??Y, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
- "<VSa>, ZwO, <VSa>, Y, r, r,
+ "wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1197,8 +1187,8 @@ (define_insn "*vsx_mov<mode>_32bit"
4, 4, 4, 20, 16,
4, 4")
(set_attr "isa"
- "*, *, *, *, *, *,
- p9v, *, *, *, *,
+ "<VSisa>, <VSisa>, <VSisa>, *, *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
@@ -1993,26 +1983,28 @@ (define_insn "*vsx_ge_<mode>_p"
;; Vector select
(define_insn "*vsx_xxsel<mode>"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
(if_then_else:VSX_L
- (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 4 "zero_constant" ""))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
+ (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
+ (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecmove")])
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
(define_insn "*vsx_xxsel<mode>_uns"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
(if_then_else:VSX_L
- (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 4 "zero_constant" ""))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>")
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
+ (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
+ (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
- [(set_attr "type" "vecmove")])
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
;; Copy sign
(define_insn "vsx_copysign<mode>3"
@@ -3814,7 +3806,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_<mode>"
;; 128-bit hardware types) and <vtype> is vector char, vector unsigned char,
;; vector short or vector unsigned short.
(define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<FL_CONV:VSr3>")
+ [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=wa")
(float:FL_CONV
(vec_select:<VSX_EXTRACT_I:VS_scalar>
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v")
@@ -3835,10 +3827,11 @@ (define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>"
(float:<FL_CONV:MODE> (match_dup 4)))]
{
operands[4] = gen_rtx_REG (DImode, REGNO (operands[3]));
-})
+}
+ [(set_attr "isa" "<VSisa>")])
(define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>"
- [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=<FL_CONV:VSr3>")
+ [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=wa")
(unsigned_float:FL_CONV
(vec_select:<VSX_EXTRACT_I:VS_scalar>
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v")
@@ -3857,7 +3850,8 @@ (define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>"
(float:<FL_CONV:MODE> (match_dup 4)))]
{
operands[4] = gen_rtx_REG (DImode, REGNO (operands[3]));
-})
+}
+ [(set_attr "isa" "<VSisa>")])
;; V4SI/V8HI/V16QI set operation on ISA 3.0
(define_insn "vsx_set_<mode>_p9"
@@ -4210,14 +4204,15 @@ (define_insn "vsx_xxmrglw_<mode>"
;; Shift left double by word immediate
(define_insn "vsx_xxsldwi_<mode>"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSa>")
- (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "<VSa>")
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSa>")
+ [(set (match_operand:VSX_L 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_L 2 "vsx_register_operand" "wa")
(match_operand:QI 3 "u5bit_cint_operand" "i")]
UNSPEC_VSX_SLDWI))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsldwi %x0,%x1,%x2,%3"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "<VSisa>")])
\f
;; Vector reduction insns and splitters
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 04618f6..843dd08 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3196,9 +3196,8 @@ Altivec vector register
@item wa
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
-When using any of the register constraints (@code{wa},
-@code{wp}, or @code{wq},
-that take VSX registers, you must use @code{%x<n>} in the template so
+When using the register constraint @code{wa}
+that takes VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
is an operand of a VSX instruction that expects VSX register
@@ -3251,12 +3250,6 @@ were used or NO_REGS.
@item wn
No register (NO_REGS).
-@item wp
-VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
-
-@item wq
-VSX register to use for IEEE 128-bit floating point, or NO_REGS.
-
@item wr
General purpose register if 64-bit instructions are enabled or NO_REGS.
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 12/12] rs6000: Update direct-move* testcases
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
2019-06-04 23:20 ` [PATCH 01/12] rs6000: Simplify VS[ra]* for VSX_[BDF] Segher Boessenkool
2019-06-04 23:21 ` [PATCH 10/12] rs6000: Add p9kf and p9tf isa values Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 02/12] rs6000: Simplify <VSa> for VSX_W Segher Boessenkool
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This fixes some testcases that the last fifteen or so patches broke.
In all these cases we no longer need to set VSX_REG_ATTR: the default
value of "wa" is correct.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
gcc/testsuite/
* gcc.target/powerpc/direct-move-double1.c (VSX_REG_ATTR): Delete.
* gcc.target/powerpc/direct-move-double2.c: Ditto.
* gcc.target/powerpc/direct-move-float1.c: Ditto.
* gcc.target/powerpc/direct-move-float2.c: Ditto.
* gcc.target/powerpc/direct-move-vint1.c: Ditto.
* gcc.target/powerpc/direct-move-vint2.c: Ditto.
---
gcc/testsuite/gcc.target/powerpc/direct-move-double1.c | 1 -
gcc/testsuite/gcc.target/powerpc/direct-move-double2.c | 1 -
gcc/testsuite/gcc.target/powerpc/direct-move-float1.c | 1 -
gcc/testsuite/gcc.target/powerpc/direct-move-float2.c | 1 -
gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c | 1 -
gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c | 1 -
6 files changed, 6 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
index 0c00a59..13f0192 100644
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
@@ -11,6 +11,5 @@
#define TYPE double
#define IS_FLOAT 1
#define NO_ALTIVEC 1
-#define VSX_REG_ATTR "ws"
#include "direct-move.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
index dae7e85..23e3423 100644
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
@@ -10,6 +10,5 @@
#define IS_FLOAT 1
#define NO_ALTIVEC 1
#define DO_MAIN
-#define VSX_REG_ATTR "ws"
#include "direct-move.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
index 14ba21e..63ab591 100644
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
@@ -13,6 +13,5 @@
#define TYPE float
#define IS_FLOAT 1
#define NO_ALTIVEC 1
-#define VSX_REG_ATTR "wa"
#include "direct-move.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
index e24f7fa..666b292 100644
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
@@ -10,6 +10,5 @@
#define IS_FLOAT 1
#define NO_ALTIVEC 1
#define DO_MAIN
-#define VSX_REG_ATTR "ww"
#include "direct-move.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
index 1de15d1..fa9d660 100644
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
@@ -9,6 +9,5 @@
/* Check code generation for direct move for vector types. */
#define TYPE vector int
-#define VSX_REG_ATTR "wa"
#include "direct-move.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
index 8618a55..b813ad4 100644
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
@@ -8,6 +8,5 @@
#define TYPE vector int
#define DO_MAIN
-#define VSX_REG_ATTR "wa"
#include "direct-move.h"
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 08/12] rs6000: <VSs> -> <sd>p
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (9 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 07/12] rs6000: ww->wa in testsuite Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 03/12] rs6000: Remove Ftrad, Fvsx, Fs; add s and sd Segher Boessenkool
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
We don't need the <VSs> mode attribute, if we make <sd> work for V4SF
and V2DF just like for SF and DF.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (define_mode_attr sd): Add values for V4SF
and V2DF.
* config/rs6000/vsx.md (define_mode_attr VSs): Delete.
(rest of file): Adjust.
---
gcc/config/rs6000/rs6000.md | 3 +-
gcc/config/rs6000/vsx.md | 104 +++++++++++++++++++-------------------------
2 files changed, 47 insertions(+), 60 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 2c86082..b8b246a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -493,7 +493,8 @@ (define_mode_iterator SFDF [SF DF])
(define_mode_iterator SFDF2 [SF DF])
; A generic s/d attribute, for sp/dp for example.
-(define_mode_attr sd [(SF "s") (DF "d")])
+(define_mode_attr sd [(SF "s") (DF "d")
+ (V4SF "s") (V2DF "d")])
; "s" or nothing, for fmuls/fmul for example.
(define_mode_attr s [(SF "s") (DF "")])
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 519f1a0..4061a5e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -93,20 +93,6 @@ (define_mode_attr VSm [(V16QI "vw4")
(V1TI "vd2")
(TI "vd2")])
-;; Map into the appropriate suffix based on the type
-(define_mode_attr VSs [(V16QI "sp")
- (V8HI "sp")
- (V4SI "sp")
- (V4SF "sp")
- (V2DF "dp")
- (V2DI "dp")
- (DF "dp")
- (SF "sp")
- (TF "dp")
- (KF "dp")
- (V1TI "dp")
- (TI "dp")])
-
;; Map the register class used
(define_mode_attr VSr [(V16QI "v")
(V8HI "v")
@@ -1594,7 +1580,7 @@ (define_insn "*vsx_add<mode>3"
(plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvadd<VSs> %x0,%x1,%x2"
+ "xvadd<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_sub<mode>3"
@@ -1602,7 +1588,7 @@ (define_insn "*vsx_sub<mode>3"
(minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvsub<VSs> %x0,%x1,%x2"
+ "xvsub<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_mul<mode>3"
@@ -1610,7 +1596,7 @@ (define_insn "*vsx_mul<mode>3"
(mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvmul<VSs> %x0,%x1,%x2"
+ "xvmul<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
; Emulate vector with scalar for vec_mul in V2DImode
@@ -1658,7 +1644,7 @@ (define_insn "*vsx_div<mode>3"
(div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvdiv<VSs> %x0,%x1,%x2"
+ "xvdiv<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_div>")])
; Emulate vector with scalar for vec_div in V2DImode
@@ -1790,7 +1776,7 @@ (define_insn "*vsx_tdiv<mode>3_internal"
(match_operand:VSX_B 2 "vsx_register_operand" "wa")]
UNSPEC_VSX_TDIV))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>tdiv<VSs> %0,%x1,%x2"
+ "x<VSv>tdiv<sd>p %0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fre<mode>2"
@@ -1798,21 +1784,21 @@ (define_insn "vsx_fre<mode>2"
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_FRES))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvre<VSs> %x0,%x1"
+ "xvre<sd>p %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_neg<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvneg<VSs> %x0,%x1"
+ "xvneg<sd>p %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_abs<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvabs<VSs> %x0,%x1"
+ "xvabs<sd>p %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_nabs<mode>2"
@@ -1821,7 +1807,7 @@ (define_insn "vsx_nabs<mode>2"
(abs:VSX_F
(match_operand:VSX_F 1 "vsx_register_operand" "wa"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvnabs<VSs> %x0,%x1"
+ "xvnabs<sd>p %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_smax<mode>3"
@@ -1829,7 +1815,7 @@ (define_insn "vsx_smax<mode>3"
(smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvmax<VSs> %x0,%x1,%x2"
+ "xvmax<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_smin<mode>3"
@@ -1837,14 +1823,14 @@ (define_insn "*vsx_smin<mode>3"
(smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvmin<VSs> %x0,%x1,%x2"
+ "xvmin<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_sqrt<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvsqrt<VSs> %x0,%x1"
+ "xvsqrt<sd>p %x0,%x1"
[(set_attr "type" "<VStype_sqrt>")])
(define_insn "*vsx_rsqrte<mode>2"
@@ -1852,7 +1838,7 @@ (define_insn "*vsx_rsqrte<mode>2"
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_RSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvrsqrte<VSs> %x0,%x1"
+ "xvrsqrte<sd>p %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
;; *tsqrt* returning the fg flag
@@ -1886,7 +1872,7 @@ (define_insn "*vsx_tsqrt<mode>2_internal"
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_TSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>tsqrt<VSs> %0,%x1"
+ "x<VSv>tsqrt<sd>p %0,%x1"
[(set_attr "type" "<VStype_simple>")])
;; Fused vector multiply/add instructions. Support the classical Altivec
@@ -1928,8 +1914,8 @@ (define_insn "*vsx_fms<mode>4"
(match_operand:VSX_F 3 "vsx_register_operand" "0,wa"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
- xvmsuba<VSs> %x0,%x1,%x2
- xvmsubm<VSs> %x0,%x1,%x3"
+ xvmsuba<sd>p %x0,%x1,%x2
+ xvmsubm<sd>p %x0,%x1,%x3"
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfma<mode>4"
@@ -1941,8 +1927,8 @@ (define_insn "*vsx_nfma<mode>4"
(match_operand:VSX_F 3 "vsx_register_operand" "0,wa"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
- xvnmadda<VSs> %x0,%x1,%x2
- xvnmaddm<VSs> %x0,%x1,%x3"
+ xvnmadda<sd>p %x0,%x1,%x2
+ xvnmaddm<sd>p %x0,%x1,%x3"
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
@@ -1980,7 +1966,7 @@ (define_insn "vsx_eq<mode>"
(eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcmpeq<VSs> %x0,%x1,%x2"
+ "xvcmpeq<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_gt<mode>"
@@ -1988,7 +1974,7 @@ (define_insn "vsx_gt<mode>"
(gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcmpgt<VSs> %x0,%x1,%x2"
+ "xvcmpgt<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_ge<mode>"
@@ -1996,7 +1982,7 @@ (define_insn "*vsx_ge<mode>"
(ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcmpge<VSs> %x0,%x1,%x2"
+ "xvcmpge<sd>p %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
;; Compare vectors producing a vector result and a predicate, setting CR6 to
@@ -2011,7 +1997,7 @@ (define_insn "*vsx_eq_<mode>_p"
(eq:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcmpeq<VSs>. %x0,%x1,%x2"
+ "xvcmpeq<sd>p. %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_gt_<mode>_p"
@@ -2024,7 +2010,7 @@ (define_insn "*vsx_gt_<mode>_p"
(gt:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcmpgt<VSs>. %x0,%x1,%x2"
+ "xvcmpgt<sd>p. %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_ge_<mode>_p"
@@ -2037,7 +2023,7 @@ (define_insn "*vsx_ge_<mode>_p"
(ge:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcmpge<VSs>. %x0,%x1,%x2"
+ "xvcmpge<sd>p. %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
;; Vector select
@@ -2071,7 +2057,7 @@ (define_insn "vsx_copysign<mode>3"
(match_operand:VSX_F 2 "vsx_register_operand" "wa")]
UNSPEC_COPYSIGN))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcpsgn<VSs> %x0,%x2,%x1"
+ "xvcpsgn<sd>p %x0,%x2,%x1"
[(set_attr "type" "<VStype_simple>")])
;; For the conversions, limit the register class for the integer value to be
@@ -2084,52 +2070,52 @@ (define_insn "vsx_float<VSi><mode>2"
[(set (match_operand:VSX_F 0 "gpc_reg_operand" "=wa")
(float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcvsx<VSc><VSs> %x0,%x1"
+ "xvcvsx<VSc><sd>p %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_floatuns<VSi><mode>2"
[(set (match_operand:VSX_F 0 "gpc_reg_operand" "=wa")
(unsigned_float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvcvux<VSc><VSs> %x0,%x1"
+ "xvcvux<VSc><sd>p %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fix_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=wa")
(fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
+ "x<VSv>cv<sd>psx<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fixuns_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=wa")
(unsigned_fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
+ "x<VSv>cv<sd>pux<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
;; Math rounding functions
-(define_insn "vsx_x<VSv>r<VSs>i"
+(define_insn "vsx_x<VSv>r<sd>pi"
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=wa")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_ROUND_I))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>r<VSs>i %x0,%x1"
+ "x<VSv>r<sd>pi %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
-(define_insn "vsx_x<VSv>r<VSs>ic"
+(define_insn "vsx_x<VSv>r<sd>pic"
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=wa")
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_ROUND_IC))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>r<VSs>ic %x0,%x1"
+ "x<VSv>r<sd>pic %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_btrunc<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvr<VSs>iz %x0,%x1"
+ "xvr<sd>piz %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_b2trunc<mode>2"
@@ -2137,7 +2123,7 @@ (define_insn "*vsx_b2trunc<mode>2"
(unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")]
UNSPEC_FRIZ))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>r<VSs>iz %x0,%x1"
+ "x<VSv>r<sd>piz %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_floor<mode>2"
@@ -2145,7 +2131,7 @@ (define_insn "vsx_floor<mode>2"
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_FRIM))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvr<VSs>im %x0,%x1"
+ "xvr<sd>pim %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_ceil<mode>2"
@@ -2153,7 +2139,7 @@ (define_insn "vsx_ceil<mode>2"
(unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_FRIP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "xvr<VSs>ip %x0,%x1"
+ "xvr<sd>pip %x0,%x1"
[(set_attr "type" "<VStype_simple>")])
\f
@@ -4688,47 +4674,47 @@ (define_insn "*xststdc<sd>p"
[(set_attr "type" "fpcompare")])
;; VSX Vector Extract Exponent Double and Single Precision
-(define_insn "xvxexp<VSs>"
+(define_insn "xvxexp<sd>p"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(unspec:VSX_F
[(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_VXEXP))]
"TARGET_P9_VECTOR"
- "xvxexp<VSs> %x0,%x1"
+ "xvxexp<sd>p %x0,%x1"
[(set_attr "type" "vecsimple")])
;; VSX Vector Extract Significand Double and Single Precision
-(define_insn "xvxsig<VSs>"
+(define_insn "xvxsig<sd>p"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(unspec:VSX_F
[(match_operand:VSX_F 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_VXSIG))]
"TARGET_P9_VECTOR"
- "xvxsig<VSs> %x0,%x1"
+ "xvxsig<sd>p %x0,%x1"
[(set_attr "type" "vecsimple")])
;; VSX Vector Insert Exponent Double and Single Precision
-(define_insn "xviexp<VSs>"
+(define_insn "xviexp<sd>p"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(unspec:VSX_F
[(match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")]
UNSPEC_VSX_VIEXP))]
"TARGET_P9_VECTOR"
- "xviexp<VSs> %x0,%x1,%x2"
+ "xviexp<sd>p %x0,%x1,%x2"
[(set_attr "type" "vecsimple")])
;; VSX Vector Test Data Class Double and Single Precision
;; The corresponding elements of the result vector are all ones
;; if any of the conditions tested by operand 3 are satisfied.
-(define_insn "xvtstdc<VSs>"
+(define_insn "xvtstdc<sd>p"
[(set (match_operand:<VSI> 0 "vsx_register_operand" "=wa")
(unspec:<VSI>
[(match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_VTSTDC))]
"TARGET_P9_VECTOR"
- "xvtstdc<VSs> %x0,%x1,%2"
+ "xvtstdc<sd>p %x0,%x1,%2"
[(set_attr "type" "vecsimple")])
;; ISA 3.0 String Operations Support
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 09/12] rs6000: More simplification
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (4 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 06/12] rs6000: VSa->wa for some more cases Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 04/12] rs6000: ww -> wa Segher Boessenkool
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
A whole bunch of mode attributes are used only once. Things are
easier to read if we just expand those patterns. It's shorter, too.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md (define_mode_attr VSr4): Delete.
(define_mode_attr VSr5): Delete.
(define_mode_attr VStype_sqrt): Delete.
(define_mode_iterator VSX_SPDP): Delete.
(define_mode_attr VS_spdp_res): Delete.
(define_mode_attr VS_spdp_insn): Delete.
(define_mode_attr VS_spdp_type): Delete.
(*vsx_sqrt<mode>2): Adjust.
(vsx_<VS_spdp_insn>): Delete, split to...
(vsx_xscvdpsp): ... this. New. And...
(vsx_xvcvspdp): ... this. New. And...
(vsx_xvcvdpsp): ... this. New.
---
gcc/config/rs6000/vsx.md | 65 +++++++++++++++++-------------------------------
1 file changed, 23 insertions(+), 42 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4061a5e..b3ebc95 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -118,18 +118,6 @@ (define_mode_attr VSr3 [(V2DF "wa")
(KF "wq")
(TF "wp")])
-;; Map the register class for sp<->dp float conversions, destination
-(define_mode_attr VSr4 [(SF "wa")
- (DF "f")
- (V2DF "wa")
- (V4SF "v")])
-
-;; Map the register class for sp<->dp float conversions, source
-(define_mode_attr VSr5 [(SF "wa")
- (DF "f")
- (V2DF "v")
- (V4SF "wa")])
-
;; The VSX register class that a type can occupy, even if it is not the
;; preferred register class (VSr is the preferred register class that will get
;; allocated first).
@@ -213,29 +201,6 @@ (define_mode_attr VStype_div [(V2DF "vecdiv")
(V4SF "vecfdiv")
(DF "ddiv")])
-;; Appropriate type for sqrt ops. For now, just lump the vector sqrt with
-;; the scalar sqrt
-(define_mode_attr VStype_sqrt [(V2DF "dsqrt")
- (V4SF "ssqrt")
- (DF "dsqrt")])
-
-;; Iterator and modes for sp<->dp conversions
-;; Because scalar SF values are represented internally as double, use the
-;; V4SF type to represent this than SF.
-(define_mode_iterator VSX_SPDP [DF V4SF V2DF])
-
-(define_mode_attr VS_spdp_res [(DF "V4SF")
- (V4SF "V2DF")
- (V2DF "V4SF")])
-
-(define_mode_attr VS_spdp_insn [(DF "xscvdpsp")
- (V4SF "xvcvspdp")
- (V2DF "xvcvdpsp")])
-
-(define_mode_attr VS_spdp_type [(DF "fp")
- (V4SF "vecdouble")
- (V2DF "vecdouble")])
-
;; Map the scalar mode for a vector type
(define_mode_attr VS_scalar [(V1TI "TI")
(V2DF "DF")
@@ -1831,7 +1796,7 @@ (define_insn "*vsx_sqrt<mode>2"
(sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsqrt<sd>p %x0,%x1"
- [(set_attr "type" "<VStype_sqrt>")])
+ [(set_attr "type" "<sd>sqrt")])
(define_insn "*vsx_rsqrte<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
@@ -2149,13 +2114,29 @@ (define_insn "vsx_ceil<mode>2"
;; Don't use xscvspdp and xscvdpsp for scalar conversions, since the normal
;; scalar single precision instructions internally use the double format.
;; Prefer the altivec registers, since we likely will need to do a vperm
-(define_insn "vsx_<VS_spdp_insn>"
- [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?wa")
- (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,wa")]
+(define_insn "vsx_xscvdpsp"
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=f,?wa")
+ (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "f,wa")]
UNSPEC_VSX_CVSPDP))]
- "VECTOR_UNIT_VSX_P (<MODE>mode)"
- "<VS_spdp_insn> %x0,%x1"
- [(set_attr "type" "<VS_spdp_type>")])
+ "VECTOR_UNIT_VSX_P (DFmode)"
+ "xscvdpsp %x0,%x1"
+ [(set_attr "type" "fp")])
+
+(define_insn "vsx_xvcvspdp"
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
+ (unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
+ UNSPEC_VSX_CVSPDP))]
+ "VECTOR_UNIT_VSX_P (V4SFmode)"
+ "xvcvspdp %x0,%x1"
+ [(set_attr "type" "vecdouble")])
+
+(define_insn "vsx_xvcvdpsp"
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
+ (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")]
+ UNSPEC_VSX_CVSPDP))]
+ "VECTOR_UNIT_VSX_P (V2DFmode)"
+ "xvcvdpsp %x0,%x1"
+ [(set_attr "type" "vecdouble")])
;; xscvspdp, represent the scalar SF type as V4SF
(define_insn "vsx_xscvspdp"
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 06/12] rs6000: VSa->wa for some more cases
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (3 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 02/12] rs6000: Simplify <VSa> for VSX_W Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 09/12] rs6000: More simplification Segher Boessenkool
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md (vsx_<VS_spdp_insn>): Use wa instead of <VSa>.
(vsx_extract_<mode>_var): Ditto.
---
gcc/config/rs6000/vsx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6255823..519f1a0 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2164,8 +2164,8 @@ (define_insn "vsx_ceil<mode>2"
;; scalar single precision instructions internally use the double format.
;; Prefer the altivec registers, since we likely will need to do a vperm
(define_insn "vsx_<VS_spdp_insn>"
- [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?<VSa>")
- (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,<VSa>")]
+ [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?wa")
+ (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"<VS_spdp_insn> %x0,%x1"
@@ -3269,7 +3269,7 @@ (define_insn "vsx_vslo_<mode>"
;; Variable V2DI/V2DF extract
(define_insn_and_split "vsx_extract_<mode>_var"
- [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v,<VSa>,r")
+ [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v,wa,r")
(unspec:<VS_scalar> [(match_operand:VSX_D 1 "input_operand" "v,m,m")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
UNSPEC_VSX_EXTRACT))
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 04/12] rs6000: ww -> wa
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (5 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 09/12] rs6000: More simplification Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 05/12] rs6000: Simplify <VSa> for VSX_TI Segher Boessenkool
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
"ww" can always be "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "ww"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_ww.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 ---
gcc/config/rs6000/rs6000.c | 8 --------
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 8 ++++----
gcc/config/rs6000/vsx.md | 26 +++++++++++++-------------
gcc/doc/md.texi | 5 +----
6 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index f45102b..b1dcee2 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -76,9 +76,6 @@ (define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]"
(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
"General purpose register if 64-bit instructions are enabled or NO_REGS.")
-(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
- "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
-
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"Floating point register if the STFIWX instruction is enabled or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 84a8257..eef4572 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2512,7 +2512,6 @@ rs6000_debug_reg_global (void)
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
- "ww reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
"\n",
@@ -2524,7 +2523,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -3136,7 +3134,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wc - Reserved to represent individual CR bits (used in LLVM).
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
- ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores. */
if (TARGET_HARD_FLOAT)
@@ -3159,11 +3156,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
}
- if (TARGET_P8_VECTOR) /* SFmode */
- rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
- else if (TARGET_VSX)
- rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
-
if (TARGET_STFIWX)
rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d59f925..102fe1c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1260,7 +1260,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
- RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_MAX
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c0a7f76..2c86082 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -525,7 +525,7 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
; ISA 2.06 (power7). This includes instructions that normally target DF mode,
; but are used on SFmode, since internally SFmode values are kept in the DFmode
; format.
-(define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
+(define_mode_attr Fv [(SF "wa") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
@@ -7298,11 +7298,11 @@ (define_split
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
- Z, m, ww, !r, f, ww,
+ Z, m, wa, !r, f, wa,
!r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
- wa, r, j, j, f, ww,
+ wa, r, j, j, f, wa,
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
@@ -8695,7 +8695,7 @@ (define_insn_and_split "reload_gpr_from_vsx<mode>"
(define_insn_and_split "reload_gpr_from_vsxsf"
[(set (match_operand:SF 0 "register_operand" "=r")
- (unspec:SF [(match_operand:SF 1 "register_operand" "ww")]
+ (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))
(clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0e04455..d082645 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -116,7 +116,7 @@ (define_mode_attr VSr [(V16QI "v")
(V2DF "wa")
(DI "wa")
(DF "wa")
- (SF "ww")
+ (SF "wa")
(TF "wp")
(KF "wq")
(V1TI "v")
@@ -127,7 +127,7 @@ (define_mode_attr VSr [(V16QI "v")
(define_mode_attr VSr3 [(V2DF "wa")
(V4SF "wa")
(DF "wa")
- (SF "ww")
+ (SF "wa")
(DI "wa")
(KF "wq")
(TF "wp")])
@@ -155,7 +155,7 @@ (define_mode_attr VSa [(V16QI "wa")
(V2DF "wa")
(DI "wa")
(DF "wa")
- (SF "ww")
+ (SF "wa")
(V1TI "wa")
(TI "wa")
(TF "wp")
@@ -2182,7 +2182,7 @@ (define_insn "vsx_xscvspdp"
;; Same as vsx_xscvspdp, but use SF as the type
(define_insn "vsx_xscvspdp_scalar2"
- [(set (match_operand:SF 0 "vsx_register_operand" "=ww")
+ [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
@@ -2202,7 +2202,7 @@ (define_insn "vsx_xvcvhpsp"
;; format of scalars is actually DF.
(define_insn "vsx_xscvdpsp_scalar"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww")]
+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"xscvdpsp %x0,%x1"
@@ -2210,7 +2210,7 @@ (define_insn "vsx_xscvdpsp_scalar"
;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
(define_insn "vsx_xscvdpspn"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
@@ -2227,7 +2227,7 @@ (define_insn "vsx_xscvspdpn"
(define_insn "vsx_xscvdpspn_scalar"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww")]
+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
"xscvdpspn %x0,%x1"
@@ -2921,8 +2921,8 @@ (define_insn "*vsx_concat_<mode>_3"
(define_insn "vsx_concat_v2sf"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
(unspec:V2DF
- [(match_operand:SF 1 "vsx_register_operand" "ww")
- (match_operand:SF 2 "vsx_register_operand" "ww")]
+ [(match_operand:SF 1 "vsx_register_operand" "wa")
+ (match_operand:SF 2 "vsx_register_operand" "wa")]
UNSPEC_VSX_CONCAT))]
"VECTOR_MEM_VSX_P (V2DFmode)"
{
@@ -3287,7 +3287,7 @@ (define_insn_and_split "vsx_extract_<mode>_var"
;; Extract a SF element from V4SF
(define_insn_and_split "vsx_extract_v4sf"
- [(set (match_operand:SF 0 "vsx_register_operand" "=ww")
+ [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(vec_select:SF
(match_operand:V4SF 1 "vsx_register_operand" "wa")
(parallel [(match_operand:QI 2 "u5bit_cint_operand" "n")])))
@@ -3339,7 +3339,7 @@ (define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
;; Variable V4SF extract
(define_insn_and_split "vsx_extract_v4sf_var"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=ww,ww,?r")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,wa,?r")
(unspec:SF [(match_operand:V4SF 1 "input_operand" "v,m,m")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
UNSPEC_VSX_EXTRACT))
@@ -3786,7 +3786,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_df"
;; not double. First convert the value to double, and then to the desired
;; type.
(define_insn_and_split "*vsx_extract_si_<uns>float_<mode>"
- [(set (match_operand:VSX_EXTRACT_FL 0 "gpc_reg_operand" "=ww")
+ [(set (match_operand:VSX_EXTRACT_FL 0 "gpc_reg_operand" "=wa")
(any_float:VSX_EXTRACT_FL
(vec_select:SI
(match_operand:V4SI 1 "gpc_reg_operand" "v")
@@ -3920,7 +3920,7 @@ (define_insn_and_split "vsx_set_v4sf_p9"
[(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
(unspec:V4SF
[(match_operand:V4SF 1 "gpc_reg_operand" "0")
- (match_operand:SF 2 "gpc_reg_operand" "ww")
+ (match_operand:SF 2 "gpc_reg_operand" "wa")
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wa"))]
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 453296d..04618f6 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa},
-@code{wp}, @code{wq}, or @code{ww})
+@code{wp}, or @code{wq},
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
@@ -3260,9 +3260,6 @@ VSX register to use for IEEE 128-bit floating point, or NO_REGS.
@item wr
General purpose register if 64-bit instructions are enabled or NO_REGS.
-@item ww
-FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
-
@item wx
Floating point register if the STFIWX instruction is enabled or NO_REGS.
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 07/12] rs6000: ww->wa in testsuite
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (8 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 11/12] rs6000: Remove wp and wq Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 08/12] rs6000: <VSs> -> <sd>p Segher Boessenkool
2019-06-04 23:21 ` [PATCH 03/12] rs6000: Remove Ftrad, Fvsx, Fs; add s and sd Segher Boessenkool
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
I should have factored this series better. Oh well. Near the end,
let's call it loose ends.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
gcc/testsuite/
* gcc.target/powerpc/direct-move-float1.c: Use "wa" instead of "ww"
constraint.
---
gcc/testsuite/gcc.target/powerpc/direct-move-float1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
index 1bd1f14..14ba21e 100644
--- a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
@@ -13,6 +13,6 @@
#define TYPE float
#define IS_FLOAT 1
#define NO_ALTIVEC 1
-#define VSX_REG_ATTR "ww"
+#define VSX_REG_ATTR "wa"
#include "direct-move.h"
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 05/12] rs6000: Simplify <VSa> for VSX_TI
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (6 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 04/12] rs6000: ww -> wa Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 11/12] rs6000: Remove wp and wq Segher Boessenkool
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
When used in VSX_TI, <VSa> is always just "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_TI
with just "wa".
---
gcc/config/rs6000/vsx.md | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d082645..6255823 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -972,9 +972,9 @@ (define_split
;; special V1TI container class, which it is not appropriate to use vec_select
;; for the type.
(define_insn "*vsx_le_permute_<mode>"
- [(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=<VSa>,<VSa>,Z,&r,&r,Q")
+ [(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=wa,wa,Z,&r,&r,Q")
(rotate:VSX_TI
- (match_operand:VSX_TI 1 "input_operand" "<VSa>,Z,<VSa>,r,Q,r")
+ (match_operand:VSX_TI 1 "input_operand" "wa,Z,wa,r,Q,r")
(const_int 64)))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"@
@@ -988,10 +988,10 @@ (define_insn "*vsx_le_permute_<mode>"
(set_attr "type" "vecperm,vecload,vecstore,*,load,store")])
(define_insn_and_split "*vsx_le_undo_permute_<mode>"
- [(set (match_operand:VSX_TI 0 "vsx_register_operand" "=<VSa>,<VSa>")
+ [(set (match_operand:VSX_TI 0 "vsx_register_operand" "=wa,wa")
(rotate:VSX_TI
(rotate:VSX_TI
- (match_operand:VSX_TI 1 "vsx_register_operand" "0,<VSa>")
+ (match_operand:VSX_TI 1 "vsx_register_operand" "0,wa")
(const_int 64))
(const_int 64)))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 10/12] rs6000: Add p9kf and p9tf isa values
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
2019-06-04 23:20 ` [PATCH 01/12] rs6000: Simplify VS[ra]* for VSX_[BDF] Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 12/12] rs6000: Update direct-move* testcases Segher Boessenkool
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This adds "p9kf" and "p9tf" isa values, to be used for instruction
alternatives where KFmode resp. TFmode is used.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (define_attr "isa"): Add p9kf and p9tf.
(define_attr "enabled"): Handle those new isa values.
---
gcc/config/rs6000/rs6000.md | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b8b246a..b1f3bc3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -267,7 +267,7 @@ (define_attr "cpu"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v" (const_string "any"))
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf" (const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
(define_attr "enabled" ""
@@ -298,6 +298,14 @@ (define_attr "enabled" ""
(and (eq_attr "isa" "p9v")
(match_test "TARGET_P9_VECTOR"))
(const_int 1)
+
+ (and (eq_attr "isa" "p9kf")
+ (match_test "TARGET_FLOAT128_TYPE"))
+ (const_int 1)
+
+ (and (eq_attr "isa" "p9tf")
+ (match_test "FLOAT128_VECTOR_P (TFmode)"))
+ (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 02/12] rs6000: Simplify <VSa> for VSX_W
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
` (2 preceding siblings ...)
2019-06-04 23:21 ` [PATCH 12/12] rs6000: Update direct-move* testcases Segher Boessenkool
@ 2019-06-04 23:21 ` Segher Boessenkool
2019-06-04 23:21 ` [PATCH 06/12] rs6000: VSa->wa for some more cases Segher Boessenkool
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Segher Boessenkool @ 2019-06-04 23:21 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
When used in VSX_W, <VSa> is always just "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_W
with just "wa".
---
gcc/config/rs6000/vsx.md | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 11e50bf..d349091 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -468,7 +468,7 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>"
(set_attr "length" "8")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
(match_operand:VSX_W 1 "indexed_or_indirect_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"#"
@@ -705,7 +705,7 @@ (define_split
(define_insn "*vsx_le_perm_store_<mode>"
[(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z")
- (match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))]
+ (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"#"
[(set_attr "type" "vecstore")
@@ -2983,9 +2983,9 @@ (define_insn "*vsx_xxpermdi2_le_<mode>"
[(set_attr "type" "vecperm")])
(define_insn "*vsx_xxpermdi4_le_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
(vec_select:VSX_W
- (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -3032,7 +3032,7 @@ (define_insn "*vsx_lxvd2x2_le_<mode>"
[(set_attr "type" "vecload")])
(define_insn "*vsx_lxvd2x4_le_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
(vec_select:VSX_W
(match_operand:VSX_W 1 "memory_operand" "Z")
(parallel [(const_int 2) (const_int 3)
@@ -3083,7 +3083,7 @@ (define_insn "*vsx_stxvd2x2_le_<mode>"
(define_insn "*vsx_stxvd2x4_le_<mode>"
[(set (match_operand:VSX_W 0 "memory_operand" "=Z")
(vec_select:VSX_W
- (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR"
@@ -4156,10 +4156,10 @@ (define_insn_and_split "vsx_splat_v4sf"
;; V4SF/V4SI splat from a vector element
(define_insn "vsx_xxspltw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
(vec_duplicate:VSX_W
(vec_select:<VS_scalar>
- (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")
(parallel
[(match_operand:QI 2 "u5bit_cint_operand" "n")]))))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -4172,8 +4172,8 @@ (define_insn "vsx_xxspltw_<mode>"
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxspltw_<mode>_direct"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
- (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
+ (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wa")
(match_operand:QI 2 "u5bit_cint_operand" "i")]
UNSPEC_VSX_XXSPLTW))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -4208,11 +4208,11 @@ (define_insn "vsx_xxspltd_<mode>"
;; V4SF/V4SI interleave
(define_insn "vsx_xxmrghw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
(vec_select:VSX_W
(vec_concat:<VS_double>
- (match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>")
- (match_operand:VSX_W 2 "vsx_register_operand" "wa,<VSa>"))
+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_W 2 "vsx_register_operand" "wa"))
(parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -4225,11 +4225,11 @@ (define_insn "vsx_xxmrghw_<mode>"
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxmrglw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
(vec_select:VSX_W
(vec_concat:<VS_double>
- (match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>")
- (match_operand:VSX_W 2 "vsx_register_operand" "wa,?<VSa>"))
+ (match_operand:VSX_W 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_W 2 "vsx_register_operand" "wa"))
(parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
--
1.8.3.1
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-06-04 23:21 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-04 23:20 [PATCH 00/12] rs6000: Another batch of constraint simplification Segher Boessenkool
2019-06-04 23:20 ` [PATCH 01/12] rs6000: Simplify VS[ra]* for VSX_[BDF] Segher Boessenkool
2019-06-04 23:21 ` [PATCH 10/12] rs6000: Add p9kf and p9tf isa values Segher Boessenkool
2019-06-04 23:21 ` [PATCH 12/12] rs6000: Update direct-move* testcases Segher Boessenkool
2019-06-04 23:21 ` [PATCH 02/12] rs6000: Simplify <VSa> for VSX_W Segher Boessenkool
2019-06-04 23:21 ` [PATCH 06/12] rs6000: VSa->wa for some more cases Segher Boessenkool
2019-06-04 23:21 ` [PATCH 09/12] rs6000: More simplification Segher Boessenkool
2019-06-04 23:21 ` [PATCH 04/12] rs6000: ww -> wa Segher Boessenkool
2019-06-04 23:21 ` [PATCH 05/12] rs6000: Simplify <VSa> for VSX_TI Segher Boessenkool
2019-06-04 23:21 ` [PATCH 11/12] rs6000: Remove wp and wq Segher Boessenkool
2019-06-04 23:21 ` [PATCH 07/12] rs6000: ww->wa in testsuite Segher Boessenkool
2019-06-04 23:21 ` [PATCH 08/12] rs6000: <VSs> -> <sd>p Segher Boessenkool
2019-06-04 23:21 ` [PATCH 03/12] rs6000: Remove Ftrad, Fvsx, Fs; add s and sd Segher Boessenkool
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