From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 7DA7F3858C1F for ; Thu, 15 Jun 2023 05:05:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7DA7F3858C1F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0356516.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35F53Lh1009025; Thu, 15 Jun 2023 05:05:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=pt7b7+/lq0yN7qpNshzBZgbrQjG827UhUrcasWpaU0Q=; b=TKbD/im2QF+pc4IzeFW4tcEFItnZy4D4UnhSeN5xWyH+yaHYeZPmPmqSm86+po41Uk68 nt8yis6ypQVGCGipjAYL7Mo7eMWd5w2B7hFYBHeNN4KMPBmrtxSDl80OnoEPSAv9wfHl t6abiu0YSbd+J7Ma5Ui7x5r8x3UwbDnBltTGFkFvx8OdiR22mitkwok+OeYCWPaioW23 AptrVXpySa7s7d1M73rL+RaKmRBxSj3a9yv23Jk2WANG7YqXLMH8CrV4jMdKYiUnEqit powVQT4sqOemDRQCddADdIbZmaHot7kXy6ZW0bdLlpRoFRYl2I8pg2lRWIu5HbivQ51R mg== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3r7v5nr20s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 05:05:29 +0000 Received: from m0356516.ppops.net (m0356516.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 35F53iXq010101; Thu, 15 Jun 2023 05:05:29 GMT Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3r7v5nr1yh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 05:05:29 +0000 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 35F4saSE017521; Thu, 15 Jun 2023 05:05:27 GMT Received: from smtprelay07.fra02v.mail.ibm.com ([9.218.2.229]) by ppma03fra.de.ibm.com (PPS) with ESMTPS id 3r4gt52ftn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 05:05:27 +0000 Received: from smtpav07.fra02v.mail.ibm.com (smtpav07.fra02v.mail.ibm.com [10.20.54.106]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 35F55Nm063832464 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 15 Jun 2023 05:05:23 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CFBB520040; Thu, 15 Jun 2023 05:05:23 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B33C120043; Thu, 15 Jun 2023 05:05:21 +0000 (GMT) Received: from [9.177.83.19] (unknown [9.177.83.19]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Jun 2023 05:05:21 +0000 (GMT) Message-ID: Date: Thu, 15 Jun 2023 13:05:20 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCHv3, rs6000] Splat vector small V2DI constants with ISA 2.07 instructions [PR104124] Content-Language: en-US To: HAO CHEN GUI Cc: Segher Boessenkool , David , Peter Bergner , gcc-patches References: <1d6c8aa8-348c-89c2-cc59-4bb382e3c221@linux.ibm.com> From: "Kewen.Lin" In-Reply-To: <1d6c8aa8-348c-89c2-cc59-4bb382e3c221@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: sw4EvLolJY5Wfl2mNWnYpjseSXXMeCnh X-Proofpoint-ORIG-GUID: yvzJiUDeFPz89WbSnK92G5b5rez67kBC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-15_02,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306150042 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Haochen, on 2023/5/26 10:49, HAO CHEN GUI wrote: > Hi, > This patch adds a new insn for vector splat with small V2DI constants on P8. > If the value of constant is in RANGE (-16, 15) and not 0 or -1, it can be loaded > with vspltisw and vupkhsw on P8. It should be efficient than loading vector from > memory. > > Compared to last version, the main change is to set a default value for third > parameter of vspltisw_vupkhsw_constant_p and call the function with 2 arguments > when the third one doesn't matter. > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. > > Thanks > Gui Haochen > > ChangeLog > 2023-05-26 Haochen Gui > > gcc/ > PR target/104124 > * config/rs6000/altivec.md (*altivec_vupkhs_direct): Rename > to... > (altivec_vupkhs_direct): ...this. > * config/rs6000/constraints.md (wT constraint): New constant for a > vector constraint that can be loaded with vspltisw and vupkhsw. > * config/rs6000/predicates.md (vspltisw_vupkhsw_constant_split): New > predicate for wT constraint. > (easy_vector_constant): Call vspltisw_vupkhsw_constant_p to Check if > a vector constant can be synthesized with a vspltisw and a vupkhsw. > * config/rs6000/rs6000-protos.h (vspltisw_vupkhsw_constant_p): Declare. > * config/rs6000/rs6000.cc (vspltisw_vupkhsw_constant_p): Call > * (vspltisw_vupkhsw_constant_p): New function to return true if OP > mode is V2DI and can be synthesized with vupkhsw and vspltisw. > * config/rs6000/vsx.md (*vspltisw_v2di_split): New insn to load up > constants with vspltisw and vupkhsw. > > gcc/testsuite/ > PR target/104124 > * gcc.target/powerpc/pr104124.c: New. > > patch.diff > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index 49b0c964f4d..2c932854c33 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -2542,7 +2542,7 @@ (define_insn "altivec_vupkhs" > } > [(set_attr "type" "vecperm")]) > > -(define_insn "*altivec_vupkhs_direct" > +(define_insn "altivec_vupkhs_direct" > [(set (match_operand:VP 0 "register_operand" "=v") > (unspec:VP [(match_operand: 1 "register_operand" "v")] > UNSPEC_VUNPACK_HI_SIGN_DIRECT))] > diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md > index c4a6ccf4efb..e7f185660c0 100644 > --- a/gcc/config/rs6000/constraints.md > +++ b/gcc/config/rs6000/constraints.md > @@ -144,6 +144,10 @@ (define_constraint "wS" > "@internal Vector constant that can be loaded with XXSPLTIB & sign extension." > (match_test "xxspltib_constant_split (op, mode)")) > > +(define_constraint "wT" > + "@internal Vector constant that can be loaded with vspltisw & vupkhsw." > + (match_test "vspltisw_vupkhsw_constant_split (op, mode)")) Could we avoid to add this new constraint? Instead put this check vspltisw_vupkhsw_constant_split (op, mode) to the condition of the define_insn_and_split "*vspltisw_v2di_split, and update the constraint with existing constraint which stands for a superset of vspltisw & vupkhsw constants, such as: W? > + > ;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form. > ;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four > ;; offset is enforced for 32-bit too. > diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md > index 52c65534e51..1ed770bffa6 100644 > --- a/gcc/config/rs6000/predicates.md > +++ b/gcc/config/rs6000/predicates.md > @@ -694,6 +694,14 @@ (define_predicate "xxspltib_constant_split" > return num_insns > 1; > }) > > +;; Return true if the operand is a constant that can be loaded with a vspltisw > +;; instruction and then a vupkhsw instruction. > + > +(define_predicate "vspltisw_vupkhsw_constant_split" > + (match_code "const_vector") > +{ > + return vspltisw_vupkhsw_constant_p (op, mode); > +}) Maybe simpler with: and (match_code "const_vector") (match_test "vspltisw_vupkhsw_constant_p (op, mode)") > > ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB > ;; instruction. > @@ -742,6 +750,11 @@ (define_predicate "easy_vector_constant" > && xxspltib_constant_p (op, mode, &num_insns, &value)) > return true; > > + /* V2DI constant within RANGE (-16, 15) can be synthesized with a > + vspltisw and a vupkhsw. */ > + if (vspltisw_vupkhsw_constant_p (op, mode, &value)) > + return true; > + > return easy_altivec_constant (op, mode); > } > > diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h > index 1a4fc1df668..00cb2d82953 100644 > --- a/gcc/config/rs6000/rs6000-protos.h > +++ b/gcc/config/rs6000/rs6000-protos.h > @@ -32,6 +32,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, > > extern int easy_altivec_constant (rtx, machine_mode); > extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); > +extern bool vspltisw_vupkhsw_constant_p (rtx, machine_mode, int * = nullptr); > extern int vspltis_shifted (rtx); > extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); > extern bool macho_lo_sum_memory_operand (rtx, machine_mode); > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index 3be5860dd9b..ae34a02b282 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -6638,6 +6638,36 @@ xxspltib_constant_p (rtx op, > return true; > } > > +/* Return true if OP mode is V2DI and can be synthesized with ISA 2.07 > + instructions vupkhsw and vspltisw. > + > + Return the constant that is being split via CONSTANT_PTR. */ > + > +bool > +vspltisw_vupkhsw_constant_p (rtx op, machine_mode mode, int *constant_ptr) > +{ > + HOST_WIDE_INT value; > + rtx elt; > + > + if (!TARGET_P8_VECTOR) > + return false; > + > + if (mode != V2DImode) > + return false; > + > + if (!const_vec_duplicate_p (op, &elt)) > + return false; > + > + value = INTVAL (elt); > + if (value == 0 || value == 1 > + || !EASY_VECTOR_15 (value)) > + return false; > + > + if (constant_ptr) > + *constant_ptr = (int) value; > + return true; > +} > + > const char * > output_vec_const_move (rtx *operands) > { > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 7d845df5c2d..200261f8b44 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -1174,6 +1174,30 @@ (define_insn_and_split "*xxspltib__split" > [(set_attr "type" "vecperm") > (set_attr "length" "8")]) > > +(define_insn_and_split "*vspltisw_v2di_split" > + [(set (match_operand:V2DI 0 "altivec_register_operand" "=v") > + (match_operand:V2DI 1 "vspltisw_vupkhsw_constant_split" "wT"))] > + "TARGET_P8_VECTOR" > + "#" > + "&& 1" > + [(const_int 0)] > +{ > + rtx op0 = operands[0]; > + rtx op1 = operands[1]; > + rtx tmp = can_create_pseudo_p () > + ? gen_reg_rtx (V4SImode) > + : gen_lowpart (V4SImode, op0); > + int value; > + > + vspltisw_vupkhsw_constant_p (op1, V2DImode, &value); > + emit_insn (gen_altivec_vspltisw (tmp, GEN_INT (value))); > + emit_insn (gen_altivec_vupkhsw_direct (op0, tmp)); > + > + DONE; > +} > + [(set_attr "type" "vecperm") > + (set_attr "length" "8")]) > + > > ;; Prefer using vector registers over GPRs. Prefer using ISA 3.0's XXSPLTISB > ;; or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC to set a register to all 0's or > diff --git a/gcc/testsuite/gcc.target/powerpc/pr104124.c b/gcc/testsuite/gcc.target/powerpc/pr104124.c > new file mode 100644 > index 00000000000..c70d8e1277a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr104124.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mdejagnu-cpu=power8 -mpower8-vector -O2" } */ > +/* { dg-require-effective-target powerpc_p8vector_ok } */ > +/* { dg-final { scan-assembler "vspltisw" } } */ > +/* { dg-final { scan-assembler "vupkhsw" } } */ > +/* { dg-final { scan-assembler-not "lvx" } } */ Maybe better by adding \m and \M for the match patterns. The others look good to me, thanks! BR, Kewen > + > +#include > + > +vector unsigned long long > +foo () > +{ > + return vec_splats ((unsigned long long) 12); > +}