From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id 892A73858D39 for ; Thu, 27 Jul 2023 20:46:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 892A73858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1bb8e45185bso9233455ad.1 for ; Thu, 27 Jul 2023 13:46:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690490785; x=1691095585; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=sosL8zppqpxgN/nxIE1cCnMIIv7BKeh24yXAlEck1QM=; b=0/7W8QB+iJiYzyMWOiuwl/uAC4LDXu+lGICctvXqKf+t837E3MHLtyXeJSPLLxrrmq si6L/0DERogLSJxPMyftUuH4H2cWg3nx2Hmuq2+63F8dSeNaQtBNxvpwf+bTs2+Zs/Yt D8V70tZbHU3TWfCJDNEcxuJhn0Nevfmb3V00S0nLYYE180iXmHl5aUPZdl+dmEgmpFXi ug3bSbuxMrRK+GL9FbzRgo+Sn+mTE+JLg2QZH/hbWMB+CdVMS4ohvZvaWTEsEFvjRvA/ 7NIHh+d256NNjpUTKi85YRCEEDkat35iohDD++R4QAYGFCFK+vvtHiq2twew7kjKnLAC mTnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690490785; x=1691095585; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sosL8zppqpxgN/nxIE1cCnMIIv7BKeh24yXAlEck1QM=; b=SGivDFA2/UA++75YMo83MahMd2m90ir8cVexxqvKdtT4nnoL9ovU594icSAPTQ401K YagImgGr+BYXkoYGKVgmi1+WLjS6WLSYPKw3elGlZCvFTgQSQvv3TTMZQV7+5/X+5O7b x/lF8ukM9aGzvquAzr8p8wOtKYJ7UG41JiQw+4mU6EaRqZpc9bHCiLxaUXm0f/xxu+/i WTymCLTcPfDwN05flFuhz2LE3+o9/JspDScmEzDB5PrdMP0hhdX8BIiAjaRk7E/zG7Rw 6CRfyspH2p4oS8J4jac9XC3mCKeWdIsfTzaLuvg4sY1siuQjht2VPEMhQLaw9jtKFW96 Qzaw== X-Gm-Message-State: ABy/qLZ83qnhfBu3wYdTt/33I6K0pZHFlSBpDTVWUos2ONS8BVIgQr8J sCzW4VJN1yEIrNSgf509+03Rsg== X-Google-Smtp-Source: APBJJlGvER4UZRANiYhqnINmR0HVl7BVZ35G2UyBSwscQ8ofiQlGR7Aqo/6nkNxzc3cyAO6gno2gaA== X-Received: by 2002:a17:902:e842:b0:1b9:e913:b585 with SMTP id t2-20020a170902e84200b001b9e913b585mr434857plg.13.1690490785016; Thu, 27 Jul 2023 13:46:25 -0700 (PDT) Received: from [10.0.17.156] ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id w5-20020a170902d3c500b001bbd1562e75sm2071111plb.55.2023.07.27.13.46.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jul 2023 13:46:24 -0700 (PDT) Content-Type: multipart/alternative; boundary="------------7l3SP0DZVYC6fHhKz06P5Ncg" Message-ID: Date: Thu, 27 Jul 2023 13:46:23 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative Content-Language: en-US To: Kito Cheng , "juzhe.zhong@rivai.ai" Cc: "demin.han" , gcc-patches References: <20230727094859.3884298-1-demin.han@starfivetech.com> <4F1CE7168EFB3E1A+2023072718223714228879@rivai.ai> From: Patrick O'Neill In-Reply-To: X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------7l3SP0DZVYC6fHhKz06P5Ncg Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit The newly added testcase fails on rv32 targets with this message: FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize (test for excess errors) verbose log: compiler exited with status 1 output is: cc1: error: ABI requires '-march=rv32' Something like this appears to fix the issue: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c index 14a9802667e..e10a9e9d0f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c @@ -1,5 +1,5 @@  /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */  long  foo (long *__restrict a, long *__restrict b, long n) On 7/27/23 04:57, Kito Cheng via Gcc-patches wrote: > My first impression is those emit_insn (gen_rtx_SET()) seems > necessary, but I got the point after I checked vector.md :P > > Committed to trunk, thanks :) > > > On Thu, Jul 27, 2023 at 6:23 PMjuzhe.zhong@rivai.ai > wrote: >> Oh, YES. >> >> Thanks for fixing it. It makes sense since the ternary operations in "vector.md" >> generate "vmv.v.v" according to RA. >> >> Thanks for fixing it. >> >> @kito: Could you confirm it? If it's ok to you, commit it for Han (I am lazy to commit patches :). >> >> >> >> juzhe.zhong@rivai.ai >> >> From: demin.han >> Date: 2023-07-27 17:48 >> To:gcc-patches@gcc.gnu.org >> CC:kito.cheng@gmail.com;juzhe.zhong@rivai.ai >> Subject: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative >> When pass split2 starts, which_alternative is random depending on >> last set of certain pass. >> >> Even initialized, the generated movement is redundant. >> The movement can be generated by assembly output template. >> >> Signed-off-by: demin.han >> >> gcc/ChangeLog: >> >> * config/riscv/autovec.md: Delete which_alternative use in split >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test. >> >> --- >> gcc/config/riscv/autovec.md | 12 ------------ >> .../gcc.target/riscv/rvv/autovec/madd-split2-1.c | 13 +++++++++++++ >> 2 files changed, 13 insertions(+), 12 deletions(-) >> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >> >> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md >> index d899922586a..b7ea3101f5a 100644 >> --- a/gcc/config/riscv/autovec.md >> +++ b/gcc/config/riscv/autovec.md >> @@ -1012,8 +1012,6 @@ (define_insn_and_split "*fma" >> [(const_int 0)] >> { >> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >> - if (which_alternative == 2) >> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >> riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (mode), >> riscv_vector::RVV_TERNOP, ops, operands[4]); >> @@ -1058,8 +1056,6 @@ (define_insn_and_split "*fnma" >> [(const_int 0)] >> { >> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >> - if (which_alternative == 2) >> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >> riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), >> riscv_vector::RVV_TERNOP, ops, operands[4]); >> @@ -1102,8 +1098,6 @@ (define_insn_and_split "*fma" >> [(const_int 0)] >> { >> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >> - if (which_alternative == 2) >> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, mode), >> riscv_vector::RVV_TERNOP, ops, operands[4]); >> @@ -1148,8 +1142,6 @@ (define_insn_and_split "*fnma" >> [(const_int 0)] >> { >> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >> - if (which_alternative == 2) >> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, mode), >> riscv_vector::RVV_TERNOP, ops, operands[4]); >> @@ -1194,8 +1186,6 @@ (define_insn_and_split "*fms" >> [(const_int 0)] >> { >> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >> - if (which_alternative == 2) >> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, mode), >> riscv_vector::RVV_TERNOP, ops, operands[4]); >> @@ -1242,8 +1232,6 @@ (define_insn_and_split "*fnms" >> [(const_int 0)] >> { >> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >> - if (which_alternative == 2) >> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, mode), >> riscv_vector::RVV_TERNOP, ops, operands[4]); >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >> new file mode 100644 >> index 00000000000..14a9802667e >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >> @@ -0,0 +1,13 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */ >> + >> +long >> +foo (long *__restrict a, long *__restrict b, long n) >> +{ >> + long i; >> + for (i = 0; i < n; ++i) >> + a[i] = b[i] + i * 8; >> + return a[1]; >> +} >> + >> +/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */ >> -- >> 2.41.0 >> >> --------------7l3SP0DZVYC6fHhKz06P5Ncg--