From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id 6169B3858293 for ; Wed, 28 Sep 2022 08:41:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6169B3858293 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1664354482; bh=I3nWAoj8+bhpZTTrX0MO6SVLv1BYg3Z+eyc4ASyYg64=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=R/4kaGvbRCXU4PLg31x3sy/tEBoaWHxL5ENMh0GmLWMhdne8YUtwy6LJo2c2YHMXt QvHsSAjPXojGcwyHS91yVs3vZ4f3hUHucBvFU4VgXjgo0R/Sj1uEvaP5XFs332TCk1 i9wf+LXZb894ko9tomnEOPWM9JHDcRIJ5Jt/RtxI= Received: from [192.168.124.3] (unknown [124.115.222.149]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384)) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 11F07667EB; Wed, 28 Sep 2022 04:41:20 -0400 (EDT) Message-ID: Subject: Re: [PATCH] LoongArch: Add prefetch instruction From: Xi Ruoyao To: Lulu Cheng , gcc-patches@gcc.gnu.org Cc: Wang Xuerui , Chenghua Xu Date: Wed, 28 Sep 2022 16:41:18 +0800 In-Reply-To: <274b4e27-6f4f-3d97-84ad-b5aae19e1002@loongson.cn> References: <20220925112537.2209847-1-xry111@xry111.site> <274b4e27-6f4f-3d97-84ad-b5aae19e1002@loongson.cn> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.0 MIME-Version: 1.0 X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FROM_SUSPICIOUS_NTLD,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_PDS_OTHER_BAD_TLD autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 2022-09-28 at 16:31 +0800, Lulu Cheng wrote: > Hi, >=20 > My colleague is testing the performance data of prefetch and > prefetchx. >=20 > And will submit both supports together if there is no problem. Ok, so mark this one as "superseded". >=20 > =E5=9C=A8 2022/9/25 =E4=B8=8B=E5=8D=887:25, Xi Ruoyao =E5=86=99=E9=81=93: > > The test pr106397.c fails on LoongArch because we don't have defined > > prefetch instruction.=C2=A0 We can silence the test for LoongArch, but > > it's > > not too difficult to add the prefetch instruction so add it now. > >=20 > > -- >8 -- > >=20 > > gcc/ChangeLog: > >=20 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* config/loongarch/cons= traints.md (ZD): New address > > constraint. > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* config/loongarch/loon= garch.md (prefetch): New insn. > > --- > > =C2=A0 gcc/config/loongarch/constraints.md |=C2=A0 6 ++++++ > > =C2=A0 gcc/config/loongarch/loongarch.md=C2=A0=C2=A0 | 14 +++++++++++++= + > > =C2=A0 2 files changed, 20 insertions(+) > >=20 > > diff --git a/gcc/config/loongarch/constraints.md > > b/gcc/config/loongarch/constraints.md > > index 43cb7b5f0f5..93da5970958 100644 > > --- a/gcc/config/loongarch/constraints.md > > +++ b/gcc/config/loongarch/constraints.md > > @@ -190,3 +190,9 @@ (define_memory_constraint "ZB" > > =C2=A0=C2=A0=C2=A0 The offset is zero" > > =C2=A0=C2=A0=C2=A0 (and (match_code "mem") > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (match_test "REG_P (XE= XP (op, 0))"))) > > + > > +(define_address_constraint "ZD" > > +=C2=A0 "An address operand whose address is formed by a base register > > and offset > > +=C2=A0=C2=A0 that is suitable for use in instructions with the same > > addressing mode > > +=C2=A0=C2=A0 as @code{preld}." > > +=C2=A0=C2=A0 (match_test "loongarch_12bit_offset_address_p (op, mode)"= )) > > diff --git a/gcc/config/loongarch/loongarch.md > > b/gcc/config/loongarch/loongarch.md > > index 214b14bddd3..84c1bd1c0d6 100644 > > --- a/gcc/config/loongarch/loongarch.md > > +++ b/gcc/config/loongarch/loongarch.md > > @@ -2137,6 +2137,20 @@ (define_insn "loongarch_dbar" > > =C2=A0=C2=A0=C2=A0 "" > > =C2=A0=C2=A0=C2=A0 "dbar\t%0") > > =C2=A0=20 > > +(define_insn "prefetch" > > +=C2=A0 [(prefetch (match_operand 0 "address_operand" "ZD") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (ma= tch_operand 1 "const_uimm5_operand" "i") > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (ma= tch_operand 2 "const_int_operand" "n"))] > > +=C2=A0 "" > > +{ > > +=C2=A0 switch (INTVAL (operands[1])) > > +=C2=A0 { > > +=C2=A0=C2=A0=C2=A0 case 0: return "preld\t0,%a0"; > > +=C2=A0=C2=A0=C2=A0 case 1: return "preld\t8,%a0"; > > +=C2=A0=C2=A0=C2=A0 default: gcc_unreachable (); > > +=C2=A0 } > > +}) > > + > > =C2=A0 =0C > > =C2=A0=20 > > =C2=A0 ;; Privileged state instruction >=20 --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University