From: will schmidt <will_schmidt@vnet.ibm.com>
To: Bill Schmidt <wschmidt@linux.ibm.com>, gcc-patches@gcc.gnu.org
Cc: segher@kernel.crashing.org
Subject: Re: [PATCH 49/55] rs6000: Builtin expansion, part 6
Date: Tue, 27 Jul 2021 16:07:11 -0500 [thread overview]
Message-ID: <b6f025f00ff4f48e441b9402ad8a01f427215df6.camel@vnet.ibm.com> (raw)
In-Reply-To: <743ac5ef9741fbd8028f5e78ecef1c6a55496181.1623941442.git.wschmidt@linux.ibm.com>
On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
> 2021-03-24 Bill Schmidt <wschmidt@linux.ibm.com>
>
> gcc/
> * config/rs6000/rs6000-call.c (new_htm_spr_num): New function.
> (new_htm_expand_builtin): Implement.
> (rs6000_expand_new_builtin): Handle 32-bit and endian cases.
> ---
> gcc/config/rs6000/rs6000-call.c | 202 ++++++++++++++++++++++++++++++++
> 1 file changed, 202 insertions(+)
>
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index e1b685fb874..6b60f0852ef 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -15068,11 +15068,171 @@ new_mma_expand_builtin (tree exp, rtx target, insn_code icode,
> return target;
> }
>
> +/* Return the appropriate SPR number associated with the given builtin. */
> +static inline HOST_WIDE_INT
> +new_htm_spr_num (enum rs6000_gen_builtins code)
> +{
> + if (code == RS6000_BIF_GET_TFHAR
> + || code == RS6000_BIF_SET_TFHAR)
> + return TFHAR_SPR;
> + else if (code == RS6000_BIF_GET_TFIAR
> + || code == RS6000_BIF_SET_TFIAR)
> + return TFIAR_SPR;
> + else if (code == RS6000_BIF_GET_TEXASR
> + || code == RS6000_BIF_SET_TEXASR)
> + return TEXASR_SPR;
> + gcc_assert (code == RS6000_BIF_GET_TEXASRU
> + || code == RS6000_BIF_SET_TEXASRU);
> + return TEXASRU_SPR;
> +}
Ok,
> +
> /* Expand the HTM builtin in EXP and store the result in TARGET. */
> static rtx
> new_htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode,
> tree exp, rtx target)
> {
> + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
> + bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
> +
> + if (!TARGET_POWERPC64
> + && (fcode == RS6000_BIF_TABORTDC
> + || fcode == RS6000_BIF_TABORTDCI))
> + {
> + error ("builtin %qs is only valid in 64-bit mode", bifaddr->bifname);
> + return const0_rtx;
> + }
ok
> +
> + rtx op[MAX_HTM_OPERANDS], pat;
> + int nopnds = 0;
> + tree arg;
> + call_expr_arg_iterator iter;
> + insn_code icode = bifaddr->icode;
> + bool uses_spr = bif_is_htmspr (*bifaddr);
> + rtx cr = NULL_RTX;
> +
> + if (uses_spr)
> + icode = rs6000_htm_spr_icode (nonvoid);
> + const insn_operand_data *insn_op = &insn_data[icode].operand[0];
> +
> + if (nonvoid)
> + {
> + machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
> + if (!target
> + || GET_MODE (target) != tmode
> + || (uses_spr && !(*insn_op->predicate) (target, tmode)))
> + target = gen_reg_rtx (tmode);
> + if (uses_spr)
> + op[nopnds++] = target;
> + }
> +
> + FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
> + {
> + if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
> + return const0_rtx;
> +
> + insn_op = &insn_data[icode].operand[nopnds];
> + op[nopnds] = expand_normal (arg);
> +
> + if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
> + {
> + if (!strcmp (insn_op->constraint, "n"))
> + {
> + int arg_num = (nonvoid) ? nopnds : nopnds + 1;
> + if (!CONST_INT_P (op[nopnds]))
> + error ("argument %d must be an unsigned literal", arg_num);
> + else
> + error ("argument %d is an unsigned literal that is "
> + "out of range", arg_num);
> + return const0_rtx;
> + }
> + op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
> + }
> +
> + nopnds++;
> + }
> +
> + /* Handle the builtins for extended mnemonics. These accept
> + no arguments, but map to builtins that take arguments. */
> + switch (fcode)
> + {
> + case RS6000_BIF_TENDALL: /* Alias for: tend. 1 */
> + case RS6000_BIF_TRESUME: /* Alias for: tsr. 1 */
> + op[nopnds++] = GEN_INT (1);
> + break;
> + case RS6000_BIF_TSUSPEND: /* Alias for: tsr. 0 */
> + op[nopnds++] = GEN_INT (0);
> + break;
> + default:
> + break;
> + }
ok
> +
> + /* If this builtin accesses SPRs, then pass in the appropriate
> + SPR number and SPR regno as the last two operands. */
> + if (uses_spr)
> + {
> + machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
> + op[nopnds++] = gen_rtx_CONST_INT (mode, new_htm_spr_num (fcode));
> + }
> + /* If this builtin accesses a CR, then pass in a scratch
> + CR as the last operand. */
> + else if (bif_is_htmcr (*bifaddr))
Given this is an if/else, presumably there are no builtins that use
both a SPR and access a CR ?
> + {
> + cr = gen_reg_rtx (CCmode);
> + op[nopnds++] = cr;
> + }
> +
> + switch (nopnds)
> + {
> + case 1:
> + pat = GEN_FCN (icode) (op[0]);
> + break;
> + case 2:
> + pat = GEN_FCN (icode) (op[0], op[1]);
> + break;
> + case 3:
> + pat = GEN_FCN (icode) (op[0], op[1], op[2]);
> + break;
> + case 4:
> + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
> + break;
> + default:
> + gcc_unreachable ();
> + }
> + if (!pat)
> + return NULL_RTX;
> + emit_insn (pat);
ok
> +
> + if (bif_is_htmcr (*bifaddr))
> + {
> + if (fcode == RS6000_BIF_TBEGIN)
> + {
> + /* Emit code to set TARGET to true or false depending on
> + whether the tbegin. instruction successfully or failed
> + to start a transaction. We do this by placing the 1's
> + complement of CR's EQ bit into TARGET. */
s/successfully/succeeded/ ?
> + rtx scratch = gen_reg_rtx (SImode);
> + emit_insn (gen_rtx_SET (scratch,
> + gen_rtx_EQ (SImode, cr,
> + const0_rtx)));
> + emit_insn (gen_rtx_SET (target,
> + gen_rtx_XOR (SImode, scratch,
> + GEN_INT (1))));
> + }
> + else
> + {
> + /* Emit code to copy the 4-bit condition register field
> + CR into the least significant end of register TARGET. */
> + rtx scratch1 = gen_reg_rtx (SImode);
> + rtx scratch2 = gen_reg_rtx (SImode);
> + rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
> + emit_insn (gen_movcc (subreg, cr));
> + emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
> + emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
> + }
> + }
> +
> + if (nonvoid)
> + return target;
ok
> return const0_rtx;
> }
>
> @@ -15316,6 +15476,48 @@ rs6000_expand_new_builtin (tree exp, rtx target,
> if (bif_is_htm (*bifaddr))
> return new_htm_expand_builtin (bifaddr, fcode, exp, target);
>
> + if (bif_is_32bit (*bifaddr) && TARGET_32BIT)
> + {
> + if (fcode == RS6000_BIF_MFTB)
> + icode = CODE_FOR_rs6000_mftb_si;
> + else
> + gcc_unreachable ();
> + }
ok
> +
> + if (bif_is_endian (*bifaddr) && BYTES_BIG_ENDIAN)
> + {
> + if (fcode == RS6000_BIF_LD_ELEMREV_V1TI)
> + icode = CODE_FOR_vsx_load_v1ti;
> + else if (fcode == RS6000_BIF_LD_ELEMREV_V2DF)
> + icode = CODE_FOR_vsx_load_v2df;
> + else if (fcode == RS6000_BIF_LD_ELEMREV_V2DI)
> + icode = CODE_FOR_vsx_load_v2di;
> + else if (fcode == RS6000_BIF_LD_ELEMREV_V4SF)
> + icode = CODE_FOR_vsx_load_v4sf;
> + else if (fcode == RS6000_BIF_LD_ELEMREV_V4SI)
> + icode = CODE_FOR_vsx_load_v4si;
> + else if (fcode == RS6000_BIF_LD_ELEMREV_V8HI)
> + icode = CODE_FOR_vsx_load_v8hi;
> + else if (fcode == RS6000_BIF_LD_ELEMREV_V16QI)
> + icode = CODE_FOR_vsx_load_v16qi;
> + else if (fcode == RS6000_BIF_ST_ELEMREV_V1TI)
> + icode = CODE_FOR_vsx_store_v1ti;
> + else if (fcode == RS6000_BIF_ST_ELEMREV_V2DF)
> + icode = CODE_FOR_vsx_store_v2df;
> + else if (fcode == RS6000_BIF_ST_ELEMREV_V2DI)
> + icode = CODE_FOR_vsx_store_v2di;
> + else if (fcode == RS6000_BIF_ST_ELEMREV_V4SF)
> + icode = CODE_FOR_vsx_store_v4sf;
> + else if (fcode == RS6000_BIF_ST_ELEMREV_V4SI)
> + icode = CODE_FOR_vsx_store_v4si;
> + else if (fcode == RS6000_BIF_ST_ELEMREV_V8HI)
> + icode = CODE_FOR_vsx_store_v8hi;
> + else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI)
> + icode = CODE_FOR_vsx_store_v16qi;
> + else
> + gcc_unreachable ();
ok
lgtm,
thanks
-Will
> + }
> +
> rtx pat;
> const int MAX_BUILTIN_ARGS = 6;
> tree arg[MAX_BUILTIN_ARGS];
next prev parent reply other threads:[~2021-07-27 21:07 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 15:18 [PATCHv3 00/55] Replace the Power target-specific builtin machinery Bill Schmidt
2021-06-17 15:18 ` [PATCH 01/55] Support scanning of build-time GC roots in gengtype Bill Schmidt
2021-06-17 15:18 ` [PATCH 02/55] rs6000: Initial create of rs6000-gen-builtins.c Bill Schmidt
2021-06-17 15:18 ` [PATCH 03/55] rs6000: Add initial input files Bill Schmidt
2021-06-17 15:18 ` [PATCH 04/55] rs6000: Add file support and functions for diagnostic support Bill Schmidt
2021-06-17 15:18 ` [PATCH 05/55] rs6000: Add helper functions for parsing Bill Schmidt
2021-07-09 19:32 ` will schmidt
2021-07-14 22:58 ` Segher Boessenkool
2021-07-14 23:32 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 06/55] rs6000: Add functions for matching types, part 1 of 3 Bill Schmidt
2021-06-17 15:18 ` [PATCH 07/55] rs6000: Add functions for matching types, part 2 " Bill Schmidt
2021-06-17 15:18 ` [PATCH 08/55] rs6000: Add functions for matching types, part 3 " Bill Schmidt
2021-06-17 15:18 ` [PATCH 09/55] rs6000: Red-black tree implementation for balanced tree search Bill Schmidt
2021-06-17 15:18 ` [PATCH 10/55] rs6000: Main function with stubs for parsing and output Bill Schmidt
2021-07-19 19:15 ` Segher Boessenkool
2021-07-20 22:19 ` Bill Schmidt
2021-07-20 23:22 ` Segher Boessenkool
2021-07-21 1:51 ` Bill Schmidt
2021-07-21 15:43 ` Segher Boessenkool
2021-07-21 16:08 ` Bill Schmidt
2021-07-21 16:16 ` Bill Schmidt
2021-06-17 15:18 ` [PATCH 11/55] rs6000: Parsing built-in input file, part 1 of 3 Bill Schmidt
2021-07-19 20:39 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 12/55] rs6000: Parsing built-in input file, part 2 " Bill Schmidt
2021-07-19 22:07 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 13/55] rs6000: Parsing built-in input file, part 3 " Bill Schmidt
2021-07-19 22:13 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 14/55] rs6000: Parsing of overload input file Bill Schmidt
2021-07-19 23:09 ` Segher Boessenkool
2021-06-17 15:18 ` [PATCH 15/55] rs6000: Build and store function type identifiers Bill Schmidt
2021-07-20 0:04 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 16/55] rs6000: Write output to the builtin definition include file Bill Schmidt
2021-07-20 23:27 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 17/55] rs6000: Write output to the builtins header file Bill Schmidt
2021-07-20 23:40 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 18/55] rs6000: Write output to the builtins init file, part 1 of 3 Bill Schmidt
2021-07-20 23:51 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 19/55] rs6000: Write output to the builtins init file, part 2 " Bill Schmidt
2021-07-20 23:53 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 20/55] rs6000: Write output to the builtins init file, part 3 " Bill Schmidt
2021-07-21 17:08 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 21/55] rs6000: Write static initializations for built-in table Bill Schmidt
2021-07-21 17:14 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 22/55] rs6000: Write static initializations for overload tables Bill Schmidt
2021-07-21 17:40 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 23/55] rs6000: Incorporate new builtins code into the build machinery Bill Schmidt
2021-07-21 18:58 ` Segher Boessenkool
2021-07-27 3:26 ` Bill Schmidt
2021-07-27 14:23 ` Segher Boessenkool
2021-07-27 17:38 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 24/55] rs6000: Add gengtype handling to " Bill Schmidt
2021-06-17 15:19 ` [PATCH 25/55] rs6000: Add the rest of the [altivec] stanza to the builtins file Bill Schmidt
2021-06-17 15:19 ` [PATCH 26/55] rs6000: Add VSX builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 27/55] rs6000: Add available-everywhere and ancient builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 28/55] rs6000: Add power7 and power7-64 builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 29/55] rs6000: Add power8-vector builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 30/55] rs6000: Add Power9 builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 31/55] rs6000: Add more type nodes to support builtin processing Bill Schmidt
2021-06-17 15:19 ` [PATCH 32/55] rs6000: Add Power10 builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 33/55] rs6000: Add MMA builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 34/55] rs6000: Add miscellaneous builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 35/55] rs6000: Add Cell builtins Bill Schmidt
2021-06-17 15:19 ` [PATCH 36/55] rs6000: Add remaining overloads Bill Schmidt
2021-06-17 15:19 ` [PATCH 37/55] rs6000: Execute the automatic built-in initialization code Bill Schmidt
2021-06-17 15:19 ` [PATCH 38/55] rs6000: Darwin builtin support Bill Schmidt
2021-06-17 15:19 ` [PATCH 39/55] rs6000: Add sanity to V2DI_type_node definitions Bill Schmidt
2021-06-17 15:19 ` [PATCH 40/55] rs6000: Always initialize vector_pair and vector_quad nodes Bill Schmidt
2021-06-17 15:19 ` [PATCH 41/55] rs6000: Handle overloads during program parsing Bill Schmidt
2021-06-17 15:19 ` [PATCH 42/55] rs6000: Handle gimple folding of target built-ins Bill Schmidt
2021-07-28 21:21 ` will schmidt
2021-07-29 12:42 ` Bill Schmidt
2021-08-02 13:31 ` Bill Schmidt
2021-08-02 23:43 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 43/55] rs6000: Support for vectorizing built-in functions Bill Schmidt
2021-06-17 15:19 ` [PATCH 44/55] rs6000: Builtin expansion, part 1 Bill Schmidt
2021-07-27 21:06 ` will schmidt
2021-07-28 3:30 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 45/55] rs6000: Builtin expansion, part 2 Bill Schmidt
2021-07-27 21:06 ` will schmidt
2021-06-17 15:19 ` [PATCH 46/55] rs6000: Builtin expansion, part 3 Bill Schmidt
2021-07-27 21:06 ` will schmidt
2021-08-03 23:40 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 47/55] rs6000: Builtin expansion, part 4 Bill Schmidt
2021-07-27 21:06 ` will schmidt
2021-08-03 23:46 ` Segher Boessenkool
2021-08-04 0:34 ` Segher Boessenkool
2021-08-12 16:17 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 48/55] rs6000: Builtin expansion, part 5 Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-06-17 15:19 ` [PATCH 49/55] rs6000: Builtin expansion, part 6 Bill Schmidt
2021-07-27 21:07 ` will schmidt [this message]
2021-07-28 20:38 ` Bill Schmidt
2021-06-17 15:19 ` [PATCH 50/55] rs6000: Update rs6000_builtin_decl Bill Schmidt
2021-07-27 21:08 ` will schmidt
2021-08-04 0:38 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 51/55] rs6000: Miscellaneous uses of rs6000_builtin_decls_x Bill Schmidt
2021-07-27 21:08 ` will schmidt
2021-06-17 15:19 ` [PATCH 52/55] rs6000: Debug support Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-08-04 0:49 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 53/55] rs6000: Update altivec.h for automated interfaces Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-07-28 20:58 ` Bill Schmidt
2021-08-04 0:58 ` Segher Boessenkool
2021-06-17 15:19 ` [PATCH 54/55] rs6000: Test case adjustments Bill Schmidt
2021-06-17 15:19 ` [PATCH 55/55] rs6000: Enable the new builtin support Bill Schmidt
2021-07-27 21:07 ` will schmidt
2021-06-25 15:25 ` [PATCHv3 00/55] Replace the Power target-specific builtin machinery Bill Schmidt
2021-07-13 13:52 ` Bill Schmidt
-- strict thread matches above, loose matches on Subject: below --
2021-06-08 18:26 [PATCHv2 " Bill Schmidt
2021-06-08 18:26 ` [PATCH 49/55] rs6000: Builtin expansion, part 6 Bill Schmidt
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