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From: Andreas Krebbel <krebbel@linux.ibm.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] Adjust docu of TARGET_VECTORIZE_VEC_PERM_CONST
Date: Wed, 28 Jul 2021 10:19:17 +0200	[thread overview]
Message-ID: <b718c6d7-a894-d6d4-64fb-65cb01b2e553@linux.ibm.com> (raw)
In-Reply-To: <CAFiYyc2YW647n5YNjRCwZkLtCBt5ioi3NXrST=7iSHGpJcBUZQ@mail.gmail.com>

On 7/28/21 9:43 AM, Richard Biener wrote:
> On Wed, Jul 28, 2021 at 8:44 AM Andreas Krebbel via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
>>
>> There are also memory operands passed for in0 and in1.
>>
>> Ok for mainline?
> 
> They can also be constant vectors, I'd just not specify the operand
> kind - usually
> expanders are not limited as to what they feed down.

Right, I'll just replace "registers" with "operands" then. Ok?

 also to emit such a permutation.  In the former case @var{in0}, @var{in1}\n\
 and @var{out} are all null.  In the latter case @var{in0} and @var{in1} are\n\
 the source vectors and @var{out} is the destination vector; all three are\n\
-registers of mode @var{mode}.  @var{in1} is the same as @var{in0} if\n\
+operands of mode @var{mode}.  @var{in1} is the same as @var{in0} if\n\
 @var{sel} describes a permutation on one vector instead of two.\n\
 \n\
 Return true if the operation is possible, emitting instructions for it\n\

Andreas

  reply	other threads:[~2021-07-28  8:19 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28  6:43 Andreas Krebbel
2021-07-28  7:43 ` Richard Biener
2021-07-28  8:19   ` Andreas Krebbel [this message]
2021-07-28 12:24     ` Richard Biener

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