From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id E64D63856DE2 for ; Thu, 18 May 2023 21:12:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E64D63856DE2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=us.ibm.com Received: from pps.filterd (m0353724.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34IL9aJc013936; Thu, 18 May 2023 21:12:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : subject : from : to : cc : date : in-reply-to : references : content-type : mime-version : content-transfer-encoding; s=pp1; bh=AqYPABS0/4tOFfZjUdwAgex4Th7fEOVLc76Puqi3c0E=; b=YT6cheicu3HktKl1wvP4hXkxQl6/FSEiqJAogN68I01nntKxUUmycbQLGDQyoPCIP6jK B/DgvUlOpDED1UeA6R2M6sWQyrENVSqTSbYiZ14yZhzFgVUXYTKVUZm3mwzwCKpfyofz IE/egTy0AAs/KCBO7Wphvs2Qk/DIwHxzsBBwvI2MmGc7MUq0/kuaOeBmhBRb3bL8Jpdo YO8bcnYObktoh5+jCORPOb5FMY+hZUHQJzYDuZ0UrFOrdLnVO2jCRiFX6fsBO07/yH8l Bdhm4+bAJDUD9m4dk4bvP/omJOU+Xl7PsBn8yNYPMBY8KRP9l4b27Obs6flOytdCNwn5 qg== Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qnudsghw1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 21:12:54 +0000 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 34IKKpOf017804; Thu, 18 May 2023 21:12:53 GMT Received: from smtprelay02.dal12v.mail.ibm.com ([9.208.130.97]) by ppma05wdc.us.ibm.com (PPS) with ESMTPS id 3qj26649mg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 21:12:53 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay02.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 34ILCqg025494146 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 18 May 2023 21:12:52 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 667B35805C; Thu, 18 May 2023 21:12:52 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 18DBE5805A; Thu, 18 May 2023 21:12:52 +0000 (GMT) Received: from li-e362e14c-2378-11b2-a85c-87d605f3c641.ibm.com (unknown [9.163.31.184]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 18 May 2023 21:12:52 +0000 (GMT) Message-ID: Subject: [PATCH v2] rs6000: Add buildin for mffscrn instructions From: Carl Love To: Segher Boessenkool , gcc-patches@gcc.gnu.org Cc: Peter Bergner Date: Thu, 18 May 2023 14:12:51 -0700 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: YstBHnDKDGGS-oTd2DjW3qg_RaDsC9Cl X-Proofpoint-ORIG-GUID: YstBHnDKDGGS-oTd2DjW3qg_RaDsC9Cl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-18_15,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 mlxlogscore=629 priorityscore=1501 bulkscore=0 spamscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180173 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: GCC maintainers: version 2. Fixed an issue with the test case. The dg-options line was missing. The following patch adds an overloaded builtin. There are two possible arguments for the builtin. The builtin definitions are: double __builtin_mffscrn (unsigned long int); double __builtin_mffscrn (double); The patch has been tested on Power 10 with no regressions. Please let me know if the patch is acceptable for mainline. Thanks. Carl ------------------------------------------------ rs6000: Add buildin for mffscrn instructions This patch adds overloaded __builtin_mffscrn for the move From FPSCR Control & Set R instruction with an immediate argument. It also adds the builtin with a floating point register argument. A new runnable test is added for the new builtin. gcc/ * config/rs6000/rs6000-builtins.def (__builtin_mffscrni, __builtin_mffscrnd): Add builtin definitions. * config/rs6000/rs6000-overload.def (__builtin_mffscrn): Add overloaded definition. * doc/extend.texi: Add documentation for __builtin_mffscrn. gcc/testsuite/ * gcc.target/powerpc/builtin-mffscrn.c: Add testcase for new builtin. --- gcc/config/rs6000/rs6000-builtins.def | 7 ++ gcc/config/rs6000/rs6000-overload.def | 5 + gcc/doc/extend.texi | 8 ++ .../gcc.target/powerpc/builtin-mffscrn.c | 106 ++++++++++++++++++ 4 files changed, 126 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 92d9b46e1b9..67125473684 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -2875,6 +2875,13 @@ pure vsc __builtin_vsx_xl_len_r (void *, signed long); XL_LEN_R xl_len_r {} +; Immediate instruction only uses the least significant two bits of the +; const int. + double __builtin_mffscrni (const int<2>); + MFFSCRNI rs6000_mffscrni {} + + double __builtin_mffscrnd (double); + MFFSCRNF rs6000_mffscrn {} ; Builtins requiring hardware support for IEEE-128 floating-point. [ieee128-hw] diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def index c582490c084..adda2df69ea 100644 --- a/gcc/config/rs6000/rs6000-overload.def +++ b/gcc/config/rs6000/rs6000-overload.def @@ -78,6 +78,11 @@ ; like after a required newline, but nowhere else. Lines beginning with ; a semicolon are also treated as blank lines. +[MFFSCR, __builtin_mffscrn, __builtin_mffscrn] + double __builtin_mffscrn (const int<2>); + MFFSCRNI + double __builtin_mffscrn (double); + MFFSCRNF [BCDADD, __builtin_bcdadd, __builtin_vec_bcdadd] vsq __builtin_vec_bcdadd (vsq, vsq, const int); diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index ed8b9c8a87b..f16c046051a 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -18455,6 +18455,9 @@ int __builtin_dfp_dtstsfi_ov_td (unsigned int comparison, _Decimal128 value); double __builtin_mffsl(void); +double __builtin_mffscrn (unsigned long int); +double __builtin_mffscrn (double); + @end smallexample The @code{__builtin_byte_in_set} function requires a 64-bit environment supporting ISA 3.0 or later. This function returns @@ -18511,6 +18514,11 @@ the FPSCR. The instruction is a lower latency version of the @code{mffs} instruction. If the @code{mffsl} instruction is not available, then the builtin uses the older @code{mffs} instruction to read the FPSCR. +The @code{__builtin_mffscrn} returns the contents of the control bits in the +FPSCR, bits 29:31 (DRN) and bits 56:63 (VE, OE, UE, ZE, XE, NI, RN). The +contents of bits [62:63] of the unsigned long int or double argument are placed +into bits [62:63] of the FPSCR (RN). + @node Basic PowerPC Built-in Functions Available on ISA 3.1 @subsubsection Basic PowerPC Built-in Functions Available on ISA 3.1 diff --git a/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c b/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c new file mode 100644 index 00000000000..26c666a4091 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c @@ -0,0 +1,106 @@ +/* { dg-do run } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mpower9-vector -mdejagnu-cpu=power9" } */ + +#include + +#ifdef DEBUG +#include +#endif + +#define MASK 0x3 +#define EXPECTED1 0x1 +#define EXPECTED2 0x2 + +void abort (void); + +int +main() +{ + unsigned long mask, result, expected; + double double_arg; + + union convert_t { + double d; + unsigned long ul; + } val; + + /* Test immediate version of __builtin_mffscrn. */ + /* Read FPSCR and set RN bits in FPSCR[62:63]. */ + val.d = __builtin_mffscrn (EXPECTED2); + + /* Read FPSCR, bits [62:63] should have been set to 0x2 by previous builtin + call. */ + val.d = __builtin_mffscrn (EXPECTED1); + /* The expected result is the argument for the previous call to + __builtin_mffscrn. */ + expected = EXPECTED2; + result = MASK & val.ul; + + if (EXPECTED2 != result) +#ifdef DEBUG + printf("Result of mffscrn immediate doesn't match EXPECTED2. Result was 0x%lx\n", + result); +#else + abort(); +#endif + + /* Read FPSCR, bits [62:63] should have been set to 0x1 by previous builtin + call*/ + val.d = __builtin_mffscrn (EXPECTED1); + expected = EXPECTED1; + result = MASK & val.ul; + + if (EXPECTED1 != result) +#ifdef DEBUG + printf("Result of mffscrn immediate doesn't match EXPECTED1. Result was 0x%lx\n", + result); +#else + abort(); +#endif + + + /* Test double argument version of __builtin_mffscrn */ + val.ul = EXPECTED2; + double_arg = val.d; + + /* Read FPSCR and set RN bits in FPSCR[62:63]. */ + val.d = __builtin_mffscrn (double_arg); + + /* Read FPSCR, bits [62:63] should have been set to 0x2 by previous builtin + call. */ + + val.ul = EXPECTED1; + double_arg = val.d; + + val.d = __builtin_mffscrn (double_arg); + /* The expected result is the argument for the previous call to + __builtin_mffscrn. */ + expected = EXPECTED2; + result = MASK & val.ul; + + if (EXPECTED2 != result) +#ifdef DEBUG + printf("Result of mffscrn double arg doesn't match EXPECTED2. Result was 0x%lx\n", + result); +#else + abort(); +#endif + + /* Read FPSCR, bits [62:63] should have been set to 0x1 by previous builtin + call*/ + val.ul = EXPECTED1; + double_arg = val.d; + + val.d = __builtin_mffscrn (double_arg); + expected = EXPECTED1; + result = MASK & val.ul; + + if (EXPECTED1 != result) +#ifdef DEBUG + printf("Result of mffscrn double arg doesn't match EXPECTED1. Result was 0x%lx\n", + result); +#else + abort(); +#endif +} -- 2.37.2