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From: Jeff Law <jeffreyalaw@gmail.com>
To: Kito Cheng <kito.cheng@gmail.com>, Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com
Subject: Re: [PATCH] RISC-V: Enable movmisalign for VLS modes
Date: Tue, 29 Aug 2023 08:23:46 -0600	[thread overview]
Message-ID: <b8c7c51b-38a2-86ca-85ff-1ff71c157662@gmail.com> (raw)
In-Reply-To: <CA+yXCZBPb+7ihaNrSXpHs1Oj0rHvF=Simo7LRcV3agg62HrJjQ@mail.gmail.com>



On 8/29/23 07:54, Kito Cheng via Gcc-patches wrote:
>> +    /* To support misalign data movement, we should use
>> +       minimum element alignment load/store.  */
>> +    unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode));
>> +    poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode) * size;
>> +    machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
>> +    operands[0] = gen_lowpart (mode, operands[0]);
>> +    operands[1] = gen_lowpart (mode, operands[1]);
>> +    if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
>> +      operands[1] = force_reg (mode, operands[1]);
> 
> Does force_reg safe for movmisalign?
It should be.  It's a pretty common idiom.  Essentially it's going to 
result in generating this for the MEM->MEM case:

MEM->REG
REG->MEM


Both of which are likely to go through the misalign expander.

I was about to ACK when I had to leave for a few minutes.

OK for the trunk.

jeff

  reply	other threads:[~2023-08-29 14:23 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-29 10:07 Juzhe-Zhong
2023-08-29 13:54 ` Kito Cheng
2023-08-29 14:23   ` Jeff Law [this message]
2023-08-29 22:27     ` 钟居哲
2023-08-30  1:29       ` Li, Pan2

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