On 12/14/2021 9:53 AM, Jakub Jelinek via Gcc-patches wrote:
> On Thu, Dec 09, 2021 at 05:32:02PM +0000, Hafiz Abid Qadeer wrote:
>> Commit 13b6c7639cf assumed that registers in a span will be in a certain
>> order. But that assumption is not true at least for the big endian targets.
>> Currently amdgcn is probably only target where CFA is split into multiple
>> registers so build_span_loc is only gets called for it. However, the
>> dwf_cfa_reg function where this ICE was seen can be called for any
>> architecture from the comparison dwf_cfa_reg (src) == cur_cfa->reg in
>> dwarf2out_frame_debug_expr. So dwf_cfa_reg should not assume certain
>> order of registers.
>>
>> I was tempted to modify the assert to handle big-endian cases but that will
>> still be error prone and may fail on some other targets.
> Do you have a preprocessed testcase on which the ICE triggers on ARM EB?
> I think I'd like to see what we were emitting in debug info for it before
> r12-5833 and what we emit with this assert removed after it.
> I assumed it wouldn't affect anything but GCN during the review.
> Seems the arm span hook for EB will swap pairs in the list:
>        for (i = 0; i < nregs; i += 2)
>          if (TARGET_BIG_END)
>            {
>              parts[i] = gen_rtx_REG (SImode, regno + i + 1);
>              parts[i + 1] = gen_rtx_REG (SImode, regno + i);
>            }
>
> BTW, I wonder about those
>    dw_stack_pointer_regnum = dwf_cfa_reg (gen_rtx_REG (Pmode,
>                                                        STACK_POINTER_REGNUM));
> and
>    dw_frame_pointer_regnum
>      = dwf_cfa_reg (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM));
> Can't those use
>    dw_stack_pointer_regnum = dwf_cfa_reg (stack_pointer_rtx);
> and
>    dw_frame_pointer_regnum = dwf_cfa_reg (hard_frame_pointer_rtx);
> ?
I think the attached testcase should trigger on c6x with -mbig-endian -O2 -g

Jeff