From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 95CAC3858C5F for ; Mon, 6 Mar 2023 05:59:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 95CAC3858C5F Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1678082363; bh=p1/kX0j7ulXUbtxtpOvMqCinagoFktk40BTTQSx3wjA=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=er+vNIwd59RZ/TT8I+mlAwHETMYksKmsJE46Bp/95finWlzUi78Uee2/0xrIsvjZp NbbCb1CUgpOmp3sqCNHGe2Tk0GMPT6msxp4syAGhS5mOm9B70LpHidjZM93zmBz/Jb XsoihcXNleigMJnxuV1Nod2wcqm8sbE2757BF+9s= Received: from [IPv6:240e:358:118d:7900:dc73:854d:832e:6] (unknown [IPv6:240e:358:118d:7900:dc73:854d:832e:6]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 20C2B6640E; Mon, 6 Mar 2023 00:59:19 -0500 (EST) Message-ID: Subject: Re: [PATCH 0/2] LoongArch: testsuite: Fix tests related to stack From: Xi Ruoyao To: Lulu Cheng Cc: gcc-patches@gcc.gnu.org, WANG Xuerui , Chenghua Xu , Yujie Yang , Mike Stump Date: Mon, 06 Mar 2023 13:59:15 +0800 In-Reply-To: References: <20230303084011.8989-1-xry111@xry111.site> <9b7181b2-00b5-9fd1-316e-979cf580e6e1@loongson.cn> <87e2942cfc448710c4759aedbbe0f34f05a76aeb.camel@xry111.site> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4 MIME-Version: 1.0 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 2023-03-06 at 11:16 +0800, Xi Ruoyao wrote: /* snip */ > > > Sorry for the late reply, the first patch I think is fine. But I have= n't=20 > > > reproduced the problem of the second mail. > > >=20 > > > Is there any special option in the configuration? > >=20 > > Oh some strange thing might be happening... I'll try to figure out what > > has caused the behavior difference. >=20 > Oh no, the difference is caused by --enable-default-pie. >=20 > Maybe I should just add -fno-PIE for the dg-options.=C2=A0 But now I'm st= ill > puzzled: why would -fPIE affect code generation on LoongArch?=C2=A0 AFAIK= all > the code we are generating is position independent (at least for now). Without -fPIE, the compiler stores a register with no reason: $ cat t.c int test(int x) { char buf[128 << 10]; return buf[x]; } $ ./gcc/cc1 t.c -nostdinc -O2 -fdump-rtl-all -o- 2>/dev/null | grep test: = -A20 test: .LFB0 =3D . lu12i.w $r13,-135168>>12 # 0xfffffffffffdf000 ori $r13,$r13,4080 add.d $r3,$r3,$r13 .LCFI0 =3D . lu12i.w $r12,-131072>>12 # 0xfffffffffffe0000 lu12i.w $r13,131072>>12 # 0x20000 add.d $r13,$r13,$r12 addi.d $r12,$r3,16 add.d $r12,$r13,$r12 lu12i.w $r13,131072>>12 # 0x20000 st.d $r12,$r3,8 ori $r13,$r13,16 ldx.b $r4,$r12,$r4 add.d $r3,$r3,$r13 .LCFI1 =3D . jr $r1 .LFE0: .size test, .-test .section .eh_frame,"aw",@progbits Note the "st.d $r12,$r3,8" instruction is completely meaningless. The t.c.300r.ira dump contains some "interesting" thing: Pass 0 for finding pseudo/allocno costs a0 (r87,l0) best GR_REGS, allocno GR_REGS a1 (r84,l0) best NO_REGS, allocno NO_REGS a2 (r83,l0) best GR_REGS, allocno GR_REGS a0(r87,l0) costs: SIBCALL_REGS:2000,2000 JIRL_REGS:2000,2000 CSR_REGS:200= 0,2000 GR_REGS:2000,2000 FP_REGS:8000,8000 ALL_REGS:32000,32000 MEM:8000,80= 00 a1(r84,l0) costs: SIBCALL_REGS:1000000,1000000 JIRL_REGS:1000000,1000000 = CSR_REGS:1000000,1000000 GR_REGS:1000000,1000000 FP_REGS:1004000,1004000 AL= L_REGS:1016000,1016000 MEM:1004000,1004000 a2(r83,l0) costs: SIBCALL_REGS:1000000,1000000 JIRL_REGS:1000000,1000000 = CSR_REGS:1000000,1000000 GR_REGS:1000000,1000000 FP_REGS:1004000,1004000 AL= L_REGS:1008000,1008000 MEM:1004000,1004000 Here r84 is the pseudo register for ($frame - 131072). Any idea why the compiler selects "NO_REGS" here? FWIW RISC-V port suffers the same issue: https://godbolt.org/z/aPorqj73b. --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University