From: Xi Ruoyao <xry111@xry111.site>
To: Lulu Cheng <chenglulu@loongson.cn>, gcc-patches@gcc.gnu.org
Cc: i@xen0n.name, xuchenghua@loongson.cn
Subject: Re: [PATCH v2] LoongArch: Optimize immediate load.
Date: Tue, 01 Nov 2022 16:02:02 +0800 [thread overview]
Message-ID: <bb6d9b747e02b8133470ad4e0636f0d6b20fde69.camel@xry111.site> (raw)
In-Reply-To: <20221101061915.1677615-1-chenglulu@loongson.cn>
On Tue, 2022-11-01 at 14:19 +0800, Lulu Cheng wrote:
> +;; Load immediate to the 32-63 bits of the source register.
> +(define_insn_and_split "load_hi32"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (ior:DI
> + (and:DI (match_operand:DI 1 "register_operand" "0")
> + (match_operand 2 "hi32_mask_operand"))
> + (match_operand 3 "const_hi32_operand" "x")))]
> + "TARGET_64BIT"
> + "#"
> + ""
> + [(set (match_dup 0)
> + (ior:DI
> + (zero_extend:DI
> + (subreg:SI (match_dup 1) 0))
> + (match_dup 4)))
> + (set (match_dup 0)
> + (ior:DI
> + (and:DI (match_dup 0)
> + (match_dup 6))
> + (match_dup 5)))]
> +{
> + operands[4] = GEN_INT (INTVAL (operands[3]) << 12 >> 12);
It's an undefined behavior if INTVAL (operands[3]) is negative.
> + operands[5] = GEN_INT (INTVAL (operands[3]) & 0xfff0000000000000);
> + operands[6] = GEN_INT (0xfffffffffffff);
> +}
> + [(set_attr "insn_count" "2")])
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
next prev parent reply other threads:[~2022-11-01 8:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 6:19 Lulu Cheng
2022-11-01 8:02 ` Xi Ruoyao [this message]
2022-11-01 8:45 ` Lulu Cheng
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