From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 82DD03858005 for ; Mon, 17 Jul 2023 03:41:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 82DD03858005 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=linux.vnet.ibm.com Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36H3CNbZ023885; Mon, 17 Jul 2023 03:41:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : from : subject : references : to : cc : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=Jtat7vpBqO3fq9b/uYX8PzsnVpFaNqLwsdi6bqApsH8=; b=shjh3VBadr1QFA6N/jxmnXXRGlLiyaNW/3zu+L4YLXuUnOU2k5qrkMPzHC13AjoKnMQc p0/Xkilrcp+lUt1FcmWshE4U6eaXY6cJ3uzQfqtICIK3pCnEuHT7gNF9aGkus9ktatAd 2OMCTinYYzdkSPLwGOCkYbgAs87CdM1XwF/JiGUI+zoWA81B4Hl2NBD/ZguY6PneNOS/ DuZoOC5COfce2AEdgvA5uSvekPbsqoCP4hAJLGcM/9sXvdgCx4AAnIx0FfwQo5UKi4es sJU3euVRCAZvpax7ubD/T7HZDVQx78CDFIxSns+oRJySa3qQ7tpqS2bbA0NEoOxcwpDN bQ== Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rvw6trp24-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Jul 2023 03:41:03 +0000 Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 36GGeGW7003390; Mon, 17 Jul 2023 03:41:02 GMT Received: from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3rv65x9ebh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 17 Jul 2023 03:41:02 +0000 Received: from smtpav06.wdc07v.mail.ibm.com (smtpav06.wdc07v.mail.ibm.com [10.39.53.233]) by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 36H3f15H57082164 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 17 Jul 2023 03:41:01 GMT Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1E1785803F; Mon, 17 Jul 2023 03:41:01 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 75A955804E; Mon, 17 Jul 2023 03:40:59 +0000 (GMT) Received: from [9.109.208.149] (unknown [9.109.208.149]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTP; Mon, 17 Jul 2023 03:40:59 +0000 (GMT) Message-ID: Date: Mon, 17 Jul 2023 09:10:57 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 From: P Jeevitha Subject: [PATCH V2] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320] References: <99f9935c-5430-dcd7-1235-ccad50fb6122@linux.vnet.ibm.com> Content-Language: en-US To: Segher Boessenkool , "Kewen.Lin" , gcc-patches@gcc.gnu.org Cc: Peter Bergner In-Reply-To: <99f9935c-5430-dcd7-1235-ccad50fb6122@linux.vnet.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: UkCgd4_fd1LSr31UadZSuDtxCH-6EavL X-Proofpoint-GUID: UkCgd4_fd1LSr31UadZSuDtxCH-6EavL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-17_03,2023-07-13_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 impostorscore=0 mlxscore=0 phishscore=0 adultscore=0 mlxlogscore=841 clxscore=1015 priorityscore=1501 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307170032 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile register. However, it can be used as volatile for PCREL addressing. Therefore, modified r2 to be non-fixed in FIXED_REGISTERS and set it to fixed if it is not PCREL and also when the user explicitly requests TOC or fixed. If the register r2 is fixed, it is made as non-volatile. Changes in register preservation roles can be accomplished with the help of available target hooks (TARGET_CONDITIONAL_REGISTER_USAGE). 2023-07-12 Jeevitha Palanisamy gcc/ PR target/PR110320 * config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change GPR2 to volatile and non-fixed register for PCREL. gcc/testsuite/ PR target/PR110320 * gcc.target/powerpc/pr110320-1.c: New testcase. * gcc.target/powerpc/pr110320-2.c: New testcase. * gcc.target/powerpc/pr110320-3.c: New testcase. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 44b448d2ba6..9aa04ec5d57 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10193,9 +10193,13 @@ rs6000_conditional_register_usage (void) for (i = 32; i < 64; i++) fixed_regs[i] = call_used_regs[i] = 1; + /* For non PC-relative code, GPR2 is unavailable for register allocation. */ + if (FIXED_R2 && !rs6000_pcrel_p ()) + fixed_regs[2] = 1; + /* The TOC register is not killed across calls in a way that is visible to the compiler. */ - if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + if (fixed_regs[2] && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)) call_used_regs[2] = 0; if (DEFAULT_ABI == ABI_V4 && flag_pic == 2) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3503614efbd..2a24fbdf9fd 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -812,7 +812,7 @@ enum data_align { align_abi, align_opt, align_both }; #define FIXED_REGISTERS \ {/* GPRs */ \ - 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* FPRs */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-1.c b/gcc/testsuite/gcc.target/powerpc/pr110320-1.c new file mode 100644 index 00000000000..a4ad34d9303 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320-1.c @@ -0,0 +1,22 @@ +/* PR target/110320 */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r11 and r12. That leaves RA to choose from r2 and the more + expensive non-volatile registers for the temporary to be assigned to, and + RA will always chooses the cheaper volatile r2 register. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler {\madd 2,3,4\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-2.c b/gcc/testsuite/gcc.target/powerpc/pr110320-2.c new file mode 100644 index 00000000000..9d6aefedd2e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320-2.c @@ -0,0 +1,21 @@ +/* PR target/110320 */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-pcrel -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we don't use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r11 and r12. That only leaves RA to choose from the more + expensive non-volatile registers for the temporary to be assigned to. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-3.c b/gcc/testsuite/gcc.target/powerpc/pr110320-3.c new file mode 100644 index 00000000000..ea6c6188c8d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320-3.c @@ -0,0 +1,21 @@ +/* PR target/110320 */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r2 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we don't use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r2, r11 and r12. That only leaves RA to choose from the more + expensive non-volatile registers for the temporary to be assigned to. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */