From: Jeff Law <jeffreyalaw@gmail.com>
To: Jivan Hakobyan <jivanhakobyan9@gmail.com>, gcc-patches@gcc.gnu.org
Subject: Re: RISC-V: Use extension instructions instead of bitwise "and"
Date: Mon, 29 May 2023 07:57:59 -0600 [thread overview]
Message-ID: <bd006eca-b9b9-554d-62b6-86bdd4ddea4e@gmail.com> (raw)
In-Reply-To: <CAHso6sMORuCuONZGQEzATJh3T0aqidjoki=gZZLsT7EJMA_KKA@mail.gmail.com>
On 5/23/23 13:46, Jivan Hakobyan via Gcc-patches wrote:
> In the case where the target supports extension instructions,
> it is preferable to use that instead of doing the same in other ways.
> For the following case
>
> void foo (unsigned long a, unsigned long* ptr) {
> ptr[0] = a & 0xffffffffUL;
> ptr[1] &= 0xffffffffUL;
> }
>
> GCC generates
> foo:
> li a5,-1
> srli a5,a5,32
> and a0,a0,a5
> sd a0,0(a1)
> ld a4,8(a1)
> and a5,a4,a5
> sd a5,8(a1)
> ret
>
> but it will be profitable to generate this one
>
> foo:
> zext.w a0,a0
> sd a0,0(a1)
> lwu a5,8(a1)
> sd a5,8(a1)
> ret
>
> This patch fixes mentioned issue.
> It supports HI -> DI, HI->SI and SI -> DI extensions.
>
> gcc/ChangeLog:
> * config/riscv/riscv.md (and<mode>3): New expander.
> (*and<mode>3) New pattern.
> * config/riscv/predicates.md (arith_operand_or_mode_mask): New
> predicate.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/and-extend-1.c: New test
> * gcc.target/riscv/and-extend-2.c: New test
Thanks. I made some minor whitespace fixes and pushed this to the trunk.
Jeff
prev parent reply other threads:[~2023-05-29 13:58 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 19:46 Jivan Hakobyan
2023-05-29 13:57 ` Jeff Law [this message]
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