From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id B842B3890435 for ; Mon, 10 Jan 2022 03:18:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B842B3890435 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 209L8bNT009317; Mon, 10 Jan 2022 03:18:47 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3dfm6pg171-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jan 2022 03:18:47 +0000 Received: from m0098399.ppops.net (m0098399.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 20A3Il5q029335; Mon, 10 Jan 2022 03:18:47 GMT Received: from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com [149.81.74.106]) by mx0a-001b2d01.pphosted.com with ESMTP id 3dfm6pg16g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jan 2022 03:18:46 +0000 Received: from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1]) by ppma04fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 20A3Hv6J024829; Mon, 10 Jan 2022 03:18:44 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma04fra.de.ibm.com with ESMTP id 3df288yn1w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jan 2022 03:18:44 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20A3Ifcn42860800 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Jan 2022 03:18:41 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0BB85A405C; Mon, 10 Jan 2022 03:18:41 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8EE46A4067; Mon, 10 Jan 2022 03:18:39 +0000 (GMT) Received: from [9.200.100.183] (unknown [9.200.100.183]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 10 Jan 2022 03:18:39 +0000 (GMT) Message-ID: Date: Mon, 10 Jan 2022 11:18:37 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: Ping^1 [PATCH] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453] Content-Language: en-US From: HAO CHEN GUI To: gcc-patches Cc: Segher Boessenkool , David , Bill Schmidt References: <6def3e90-2c3f-e628-8325-650969e8b8c2@linux.ibm.com> In-Reply-To: <6def3e90-2c3f-e628-8325-650969e8b8c2@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Zihsu8PkKcuRsoMOgo9VXla0d2NltebL X-Proofpoint-GUID: 5tLBex1q_GfOwtHHCob6AccFPJj76jFx Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-10_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201100020 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Jan 2022 03:18:50 -0000 Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2021-December/586304.html Thanks On 7/12/2021 下午 4:28, HAO CHEN GUI wrote: > Hi, > This patch modifies the combine pattern with a helper - change_pseudo_and_mask when recog fails. > The helper converts a single pseudo to the pseudo AND with a mask if the outer operator is IOR/XOR/PLUS > and the inner operator is ASHIFT/LSHIFTRT/AND. The conversion helps on shift + ior pattern. > > Not sure if the helper should be a target hook or not. Please advice. > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is this okay for trunk? > Any recommendations? Thanks a lot. > > ChangeLog > 2021-12-07 Haochen Gui > > gcc/ > * combine.c (change_pseudo_and_mask): New. > (recog_for_combine): If recog fails, try again with the pattern > modified by change_pseudo_and_mask. > * config/rs6000/rs6000.md (plus_ior_xor): Removed. > (anonymous split pattern for plus_ior_xor): Likewise. > > gcc/testsuite/ > * gcc.target/powerpc/20050603-3.c: Modify dump check conditions. > * gcc.target/powerpc/rlwimi-2.c: Likewise. > > patch.diff > diff --git a/gcc/combine.c b/gcc/combine.c > index 03e9a780919..53500e8c6a0 100644 > --- a/gcc/combine.c > +++ b/gcc/combine.c > @@ -11539,6 +11539,36 @@ change_zero_ext (rtx pat) > return changed; > } > > +/* When the outer code of set_src is IOR/XOR/PLUS and the inner code is > + ASHIFT/LSHIFTRT/AND, convert a pseudo to psuedo AND with a mask if its > + nonzero_bits is less than its mode mask. The nonzero_bits in other pass > + doesn't return the same value as it does in combine pass. */ > +static bool > +change_pseudo_and_mask (rtx pat) > +{ > + rtx src = SET_SRC (pat); > + if ((GET_CODE (src) == IOR > + || GET_CODE (src) == XOR > + || GET_CODE (src) == PLUS) > + && (((GET_CODE (XEXP (src, 0)) == ASHIFT > + || GET_CODE (XEXP (src, 0)) == LSHIFTRT > + || GET_CODE (XEXP (src, 0)) == AND) > + && REG_P (XEXP (src, 1))))) > + { > + rtx *reg = &XEXP (SET_SRC (pat), 1); > + machine_mode mode = GET_MODE (*reg); > + unsigned HOST_WIDE_INT nonzero = nonzero_bits (*reg, mode); > + if (nonzero < GET_MODE_MASK (mode)) > + { > + rtx x = gen_rtx_AND (mode, *reg, GEN_INT (nonzero)); > + SUBST (*reg, x); > + maybe_swap_commutative_operands (SET_SRC (pat)); > + return true; > + } > + } > + return false; > +} > + > /* Like recog, but we receive the address of a pointer to a new pattern. > We try to match the rtx that the pointer points to. > If that fails, we may try to modify or replace the pattern, > @@ -11586,7 +11616,10 @@ recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes) > } > } > else > - changed = change_zero_ext (pat); > + { > + changed = change_pseudo_and_mask (pat); > + changed |= change_zero_ext (pat); > + } > } > else if (GET_CODE (pat) == PARALLEL) > { > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index 6bec2bddbde..5adbe9e9d27 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -4149,24 +4149,6 @@ (define_insn "rotl3_insert_3" > } > [(set_attr "type" "insert")]) > > -(define_code_iterator plus_ior_xor [plus ior xor]) > - > -(define_split > - [(set (match_operand:GPR 0 "gpc_reg_operand") > - (plus_ior_xor:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand") > - (match_operand:SI 2 "const_int_operand")) > - (match_operand:GPR 3 "gpc_reg_operand")))] > - "nonzero_bits (operands[3], mode) > - < HOST_WIDE_INT_1U << INTVAL (operands[2])" > - [(set (match_dup 0) > - (ior:GPR (and:GPR (match_dup 3) > - (match_dup 4)) > - (ashift:GPR (match_dup 1) > - (match_dup 2))))] > -{ > - operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1); > -}) > - > (define_insn "*rotl3_insert_4" > [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") > (ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0") > diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-3.c b/gcc/testsuite/gcc.target/powerpc/20050603-3.c > index 4017d34f429..e628be11532 100644 > --- a/gcc/testsuite/gcc.target/powerpc/20050603-3.c > +++ b/gcc/testsuite/gcc.target/powerpc/20050603-3.c > @@ -12,7 +12,7 @@ void rotins (unsigned int x) > b.y = (x<<12) | (x>>20); > } > > -/* { dg-final { scan-assembler-not {\mrlwinm} } } */ > +/* { dg-final { scan-assembler-not {\mrlwinm} { target ilp32 } } } */ > /* { dg-final { scan-assembler-not {\mrldic} } } */ > /* { dg-final { scan-assembler-not {\mrot[lr]} } } */ > /* { dg-final { scan-assembler-not {\ms[lr][wd]} } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c > index bafa371db73..ffb5f9e450f 100644 > --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c > +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c > @@ -2,14 +2,14 @@ > /* { dg-options "-O2" } */ > > /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 14121 { target ilp32 } } } */ > -/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 20217 { target lp64 } } } */ > +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 21279 { target lp64 } } } */ > /* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ > /* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */ > /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ > /* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */ > > /* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */ > -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */ > +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target lp64 } } } */ > > /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */ >