From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 74978 invoked by alias); 4 Jun 2015 09:57:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 74961 invoked by uid 89); 4 Jun 2015 09:57:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mx0a-0016f401.pphosted.com Received: from mx0a-0016f401.pphosted.com (HELO mx0a-0016f401.pphosted.com) (67.231.148.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 04 Jun 2015 09:57:41 +0000 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.14.5/8.14.5) with SMTP id t549sHbg012918; Thu, 4 Jun 2015 02:57:29 -0700 Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 1usq1cmjet-1 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NOT); Thu, 04 Jun 2015 02:57:28 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Thu, 4 Jun 2015 02:57:27 -0700 Received: from SC-EXCH04.marvell.com ([fe80::3421:5963:5d4c:ce13]) by SC-EXCH04.marvell.com ([fe80::3421:5963:5d4c:ce13%21]) with mapi id 15.00.1044.021; Thu, 4 Jun 2015 02:57:27 -0700 From: Shiva Chen To: Richard Earnshaw , Kyrill Tkachov , Shiva Chen CC: Ramana Radhakrishnan , GCC Patches , "nickc@redhat.com" Subject: RE: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code Date: Thu, 04 Jun 2015 10:01:00 -0000 Message-ID: References: <556EBB3F.7090603@arm.com> <556EBBAC.2020504@arm.com> <556EBC77.3060601@arm.com> <5570097C.2010706@arm.com> <55700F63.2060700@foss.arm.com> In-Reply-To: <55700F63.2060700@foss.arm.com> x-ms-exchange-transport-fromentityheader: Hosted Content-Type: multipart/mixed; boundary="_002_c0159834abd5499990a3ef6e77df96f0SCEXCH04marvellcom_" MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.14.151,1.0.33,0.0.0000 definitions=2015-06-04_05:2015-06-03,2015-06-04,1970-01-01 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=7.0.1-1402240000 definitions=main-1506040126 X-SW-Source: 2015-06/txt/msg00392.txt.bz2 --_002_c0159834abd5499990a3ef6e77df96f0SCEXCH04marvellcom_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Content-length: 4794 Hi, Kyrill Thanks for the tips of syntax. It seems that correct syntax for ldrb with condition code is ldreqb =09 ldab with condition code is ldabeq So I modified the pattern as follow { enum memmodel model =3D (enum memmodel) INTVAL (operands[2]); if (model =3D=3D MEMMODEL_RELAXED || model =3D=3D MEMMODEL_CONSUME || model =3D=3D MEMMODEL_RELEASE) return \"ldr%?\\t%0, %1\"; else return \"lda%?\\t%0, %1\"; } [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")]) It seems we don't have to worry about thumb mode,=20 Because we already set "predicable" "yes" and predicable_short_it" "no" for= the pattern. The new patch could build gcc and run gcc regression test successfully. Please correct me if I still missing something. Thanks, Shiva=20=20=20 -----Original Message----- From: Richard Earnshaw [mailto:Richard.Earnshaw@foss.arm.com]=20 Sent: Thursday, June 04, 2015 4:42 PM To: Kyrill Tkachov; Shiva Chen Cc: Ramana Radhakrishnan; GCC Patches; nickc@redhat.com; Shiva Chen Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl= missing conditional code On 04/06/15 09:17, Kyrill Tkachov wrote: > Hi Shiva, >=20 > On 04/06/15 04:13, Shiva Chen wrote: >> Hi, Ramana >> >> Currently, I work for Marvell and the company have copyright assignment = on file. >> >> Hi, all >> >> After adding the attribute and rebuild gcc, I got the assembler error=20 >> message >> >> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >> >> When i look into armv8 ISA document, it seems ldrb Encoding A1 have=20 >> conditional code field. >> >> Does it mean we should also patch assembler or I just miss=20 >> understanding something ? >> >> Following command use to generate load_n.s: >> >> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnu >> eabihf-hard/gcc-final/./gcc/cc1 -fpreprocessed load_n.i -quiet=20 >> -dumpbase load_n.c -march=3Darmv8-a -mfloat-abi=3Dhard -mfpu=3Dfp-armv8= =20=20 >> -mtls-dialect=3Dgnu -auxbase-strip .libs/load_1_.o -g3 -O2 -Wall=20 >> -Werror -version -fPIC -funwind-tables -o load_n.s >> >> >> The test.c is a simple test case to reproduce missing conditional=20 >> code in mmap.c. >> >> Any suggestion ? >=20 > I reproduced the assembler failure with your patch. >=20 > The reason is that for arm mode we use divided syntax, where the=20 > condition field goes in a different place. So, while ldrbeq r0,[r0] is re= jected, ldreqb r0, [r0] works. > Since we always use divided syntax for arm mode, I think you'll need=20 > to put the condition field in the right place depending on arm or thumb m= ode. > Ugh, this is becoming ugly :( >=20 Use %(%)\t%1, %0\"; R. > Kyrill >=20 >> >> >> Shiva >> >> 2015-06-03 17:29 GMT+08:00 Shiva Chen : >>> Hi, Ramana >>> >>> I'm not sure what copyright assignment means ? >>> >>> Does it mean the patch have copyright assignment or not ? >>> >>> I update the patch to add "predicable" and "predicable_short_it" >>> attribute as suggestion. >>> >>> However, I don't have svn write access yet. >>> >>> Shiva >>> >>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov : >>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>> This pattern is not predicable though, i.e. it doesn't have the=20 >>>>>> "predicable" attribute set to "yes". >>>>>> Therefore the compiler should be trying to branch around here=20 >>>>>> rather than try to do a cond_exec. >>>>>> Why does the generated code above look like it's converted to=20 >>>>>> conditional execution? >>>>>> Could you produce a self-contained reduced testcase for this? >>>>> CCFSM state machine in ARM state. >>>>> >>>>> arm.c (final_prescan_insn). >>>> >>>> Ah ok. >>>> This patch makes sense then. >>>> As Ramana mentioned, please mark the pattern with "predicable" and=20 >>>> also set the "predicable_short_it" attribute to "no" so that it=20 >>>> will not be conditionalised in Thumb2 mode or when -mrestrict-it is en= abled. >>>> >>>> Thanks, >>>> Kyrill >>>> >>>> >>>> >>>>> Ramana >>>>> >>>>>> Thanks, >>>>>> Kyrill >>>>>> >>>>>>> @@ -91,9 +91,9 @@ >>>>>>> { >>>>>>> enum memmodel model =3D memmodel_from_int (INTVAL (operand= s[2])); >>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) ||=20 >>>>>>> is_mm_acquire (model)) >>>>>>> - return \"str\t%1, %0\"; >>>>>>> + return \"str%?\t%1, %0\"; >>>>>>> else >>>>>>> - return \"stl\t%1, %0\"; >>>>>>> + return \"stl%?\t%1, %0\"; >>>>>>> } >>>>>>> ) >>>>>>> >=20 --_002_c0159834abd5499990a3ef6e77df96f0SCEXCH04marvellcom_ Content-Type: application/octet-stream; name="Fix_slt_lda_missing_conditional_code.diff" Content-Description: Fix_slt_lda_missing_conditional_code.diff Content-Disposition: attachment; filename="Fix_slt_lda_missing_conditional_code.diff"; size=1274; creation-date="Wed, 03 Jun 2015 09:01:58 GMT"; modification-date="Thu, 04 Jun 2015 09:11:06 GMT" Content-Transfer-Encoding: base64 Content-length: 1729 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYXJtL3N5bmMubWQgYi9nY2MvY29u ZmlnL2FybS9zeW5jLm1kCmluZGV4IDQ0Y2RhNjEuLmM4OTk3OGEgMTAwNjQ0 Ci0tLSBhL2djYy9jb25maWcvYXJtL3N5bmMubWQKKysrIGIvZ2NjL2NvbmZp Zy9hcm0vc3luYy5tZApAQCAtNzUsMTEgKzc1LDEyIEBACiAgIHsKICAgICBl bnVtIG1lbW1vZGVsIG1vZGVsID0gbWVtbW9kZWxfZnJvbV9pbnQgKElOVFZB TCAob3BlcmFuZHNbMl0pKTsKICAgICBpZiAoaXNfbW1fcmVsYXhlZCAobW9k ZWwpIHx8IGlzX21tX2NvbnN1bWUgKG1vZGVsKSB8fCBpc19tbV9yZWxlYXNl IChtb2RlbCkpCi0gICAgICByZXR1cm4gXCJsZHI8c3luY19zZng+XFx0JTAs ICUxXCI7CisgICAgICByZXR1cm4gXCJsZHIlPzxzeW5jX3NmeD5cXHQlMCwg JTFcIjsKICAgICBlbHNlCi0gICAgICByZXR1cm4gXCJsZGE8c3luY19zZng+ XFx0JTAsICUxXCI7CisgICAgICByZXR1cm4gXCJsZGE8c3luY19zZng+JT9c XHQlMCwgJTFcIjsKICAgfQotKQorICBbKHNldF9hdHRyICJwcmVkaWNhYmxl IiAieWVzIikKKyAgIChzZXRfYXR0ciAicHJlZGljYWJsZV9zaG9ydF9pdCIg Im5vIildKQogCiAoZGVmaW5lX2luc24gImF0b21pY19zdG9yZTxtb2RlPiIK ICAgWyhzZXQgKG1hdGNoX29wZXJhbmQ6UUhTSSAwICJtZW1vcnlfb3BlcmFu ZCIgIj1RIikKQEAgLTkxLDExICs5MiwxMiBAQAogICB7CiAgICAgZW51bSBt ZW1tb2RlbCBtb2RlbCA9IG1lbW1vZGVsX2Zyb21faW50IChJTlRWQUwgKG9w ZXJhbmRzWzJdKSk7CiAgICAgaWYgKGlzX21tX3JlbGF4ZWQgKG1vZGVsKSB8 fCBpc19tbV9jb25zdW1lIChtb2RlbCkgfHwgaXNfbW1fYWNxdWlyZSAobW9k ZWwpKQotICAgICAgcmV0dXJuIFwic3RyPHN5bmNfc2Z4Plx0JTEsICUwXCI7 CisgICAgICByZXR1cm4gXCJzdHIlPzxzeW5jX3NmeD5cdCUxLCAlMFwiOwog ICAgIGVsc2UKLSAgICAgIHJldHVybiBcInN0bDxzeW5jX3NmeD5cdCUxLCAl MFwiOworICAgICAgcmV0dXJuIFwic3RsPHN5bmNfc2Z4PiU/XHQlMSwgJTBc IjsKICAgfQotKQorICBbKHNldF9hdHRyICJwcmVkaWNhYmxlIiAieWVzIikK KyAgIChzZXRfYXR0ciAicHJlZGljYWJsZV9zaG9ydF9pdCIgIm5vIildKQog CiA7OyBOb3RlIHRoYXQgbGRyZCBhbmQgdmxkciBhcmUgKm5vdCogZ3VhcmFu dGVlZCB0byBiZSBzaW5nbGUtY29weSBhdG9taWMsCiA7OyBldmVuIGZvciBh IDY0LWJpdCBhbGlnbmVkIGFkZHJlc3MuICBJbnN0ZWFkIHdlIHVzZSBhIGxk cmV4ZCB1bnBhcmllZAo= --_002_c0159834abd5499990a3ef6e77df96f0SCEXCH04marvellcom_--