* Re: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-06-21 13:42 [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132] Xi Ruoyao
@ 2021-07-01 8:11 ` Xi Ruoyao
2021-07-09 6:50 ` PING^2: " Xi Ruoyao
2021-07-16 5:57 ` PING^3: " Xi Ruoyao
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Xi Ruoyao @ 2021-07-01 8:11 UTC (permalink / raw)
To: gcc-patches
Cc: xry111, Martin Li�0�8ka, Matthew Fortune,
Richard Sandiford, Jeff Law
Ping.
On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
> Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
> ICE on MIPS with MSA enabled. Add the pattern to prevent it.
>
> Bootstrapped and regression tested on mips64el-linux-gnu.
> Ok for trunk?
>
> gcc/
>
> * config/mips/mips-protos.h (mips_expand_vec_cmp_expr):
> Declare.
> * config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
> * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
> expander.
> (vec_cmpu<IMSA:mode><mode_i>): New expander.
> ---
> gcc/config/mips/mips-msa.md | 22 ++++++++++++++++++++++
> gcc/config/mips/mips-protos.h | 1 +
> gcc/config/mips/mips.c | 11 +++++++++++
> 3 files changed, 34 insertions(+)
>
> diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
> index 3ecf2bde19f..3a67f25be56 100644
> --- a/gcc/config/mips/mips-msa.md
> +++ b/gcc/config/mips/mips-msa.md
> @@ -435,6 +435,28 @@
> DONE;
> })
>
> +(define_expand "vec_cmp<MSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:MSA 2 "register_operand")
> + (match_operand:MSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> +(define_expand "vec_cmpu<IMSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:IMSA 2 "register_operand")
> + (match_operand:IMSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> (define_insn "msa_insert_<msafmt_f>"
> [(set (match_operand:MSA 0 "register_operand" "=f,f")
> (vec_merge:MSA
> diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-
> protos.h
> index 2cf4ed50292..a685f7f7dd5 100644
> --- a/gcc/config/mips/mips-protos.h
> +++ b/gcc/config/mips/mips-protos.h
> @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum
> rtx_code);
>
> extern void mips_register_frame_header_opt (void);
> extern void mips_expand_vec_cond_expr (machine_mode, machine_mode,
> rtx *);
> +extern void mips_expand_vec_cmp_expr (rtx *);
>
> /* Routines implemented in mips-d.c */
> extern void mips_d_target_versions (void);
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 00a8eef96aa..8f043399a8e 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code
> cond, rtx op0, rtx op1)
> }
> }
>
> +void
> +mips_expand_vec_cmp_expr (rtx *operands)
> +{
> + rtx cond = operands[1];
> + rtx op0 = operands[2];
> + rtx op1 = operands[3];
> + rtx res = operands[0];
> +
> + mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
> +}
> +
> /* Expand VEC_COND_EXPR, where:
> MODE is mode of the result
> VIMODE equivalent integer mode
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread* PING^2: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-07-01 8:11 ` Xi Ruoyao
@ 2021-07-09 6:50 ` Xi Ruoyao
0 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2021-07-09 6:50 UTC (permalink / raw)
To: gcc-patches
Cc: Martin Li�0�8ka, Matthew Fortune,
Richard Sandiford, Jeff Law
PING again.
On Thu, 2021-07-01 at 16:11 +0800, Xi Ruoyao wrote:
> Ping.
>
> On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
> > Middle-end started to emit vec_cmp and vec_cmpu since GCC 11,
> > causing
> > ICE on MIPS with MSA enabled. Add the pattern to prevent it.
> >
> > Bootstrapped and regression tested on mips64el-linux-gnu.
> > Ok for trunk?
> >
> > gcc/
> >
> > * config/mips/mips-protos.h (mips_expand_vec_cmp_expr):
> > Declare.
> > * config/mips/mips.c (mips_expand_vec_cmp_expr): New
> > function.
> > * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
> > expander.
> > (vec_cmpu<IMSA:mode><mode_i>): New expander.
> > ---
> > gcc/config/mips/mips-msa.md | 22 ++++++++++++++++++++++
> > gcc/config/mips/mips-protos.h | 1 +
> > gcc/config/mips/mips.c | 11 +++++++++++
> > 3 files changed, 34 insertions(+)
> >
> > diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-
> > msa.md
> > index 3ecf2bde19f..3a67f25be56 100644
> > --- a/gcc/config/mips/mips-msa.md
> > +++ b/gcc/config/mips/mips-msa.md
> > @@ -435,6 +435,28 @@
> > DONE;
> > })
> >
> > +(define_expand "vec_cmp<MSA:mode><mode_i>"
> > + [(match_operand:<VIMODE> 0 "register_operand")
> > + (match_operator 1 ""
> > + [(match_operand:MSA 2 "register_operand")
> > + (match_operand:MSA 3 "register_operand")])]
> > + "ISA_HAS_MSA"
> > +{
> > + mips_expand_vec_cmp_expr (operands);
> > + DONE;
> > +})
> > +
> > +(define_expand "vec_cmpu<IMSA:mode><mode_i>"
> > + [(match_operand:<VIMODE> 0 "register_operand")
> > + (match_operator 1 ""
> > + [(match_operand:IMSA 2 "register_operand")
> > + (match_operand:IMSA 3 "register_operand")])]
> > + "ISA_HAS_MSA"
> > +{
> > + mips_expand_vec_cmp_expr (operands);
> > + DONE;
> > +})
> > +
> > (define_insn "msa_insert_<msafmt_f>"
> > [(set (match_operand:MSA 0 "register_operand" "=f,f")
> > (vec_merge:MSA
> > diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-
> > protos.h
> > index 2cf4ed50292..a685f7f7dd5 100644
> > --- a/gcc/config/mips/mips-protos.h
> > +++ b/gcc/config/mips/mips-protos.h
> > @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn
> > (enum
> > rtx_code);
> >
> > extern void mips_register_frame_header_opt (void);
> > extern void mips_expand_vec_cond_expr (machine_mode, machine_mode,
> > rtx *);
> > +extern void mips_expand_vec_cmp_expr (rtx *);
> >
> > /* Routines implemented in mips-d.c */
> > extern void mips_d_target_versions (void);
> > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> > index 00a8eef96aa..8f043399a8e 100644
> > --- a/gcc/config/mips/mips.c
> > +++ b/gcc/config/mips/mips.c
> > @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum
> > rtx_code
> > cond, rtx op0, rtx op1)
> > }
> > }
> >
> > +void
> > +mips_expand_vec_cmp_expr (rtx *operands)
> > +{
> > + rtx cond = operands[1];
> > + rtx op0 = operands[2];
> > + rtx op1 = operands[3];
> > + rtx res = operands[0];
> > +
> > + mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
> > +}
> > +
> > /* Expand VEC_COND_EXPR, where:
> > MODE is mode of the result
> > VIMODE equivalent integer mode
>
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread
* PING^3: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-06-21 13:42 [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132] Xi Ruoyao
2021-07-01 8:11 ` Xi Ruoyao
@ 2021-07-16 5:57 ` Xi Ruoyao
2021-07-23 12:46 ` PING^4: " Xi Ruoyao
2021-07-30 4:56 ` PING^5: " Xi Ruoyao
3 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2021-07-16 5:57 UTC (permalink / raw)
To: gcc-patches
Cc: Martin Li�0�8ka, Matthew Fortune,
Richard Sandiford, Jeff Law, Maciej W. Rozycki, xry111
Ping again.
I heard that Matthew is too busy to deal with MIPS things from someone's
private mail. Hope someone else can review it.
On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
> Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
> ICE on MIPS with MSA enabled. Add the pattern to prevent it.
>
> Bootstrapped and regression tested on mips64el-linux-gnu.
> Ok for trunk?
>
> gcc/
>
> * config/mips/mips-protos.h (mips_expand_vec_cmp_expr):
> Declare.
> * config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
> * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
> expander.
> (vec_cmpu<IMSA:mode><mode_i>): New expander.
> ---
> gcc/config/mips/mips-msa.md | 22 ++++++++++++++++++++++
> gcc/config/mips/mips-protos.h | 1 +
> gcc/config/mips/mips.c | 11 +++++++++++
> 3 files changed, 34 insertions(+)
>
> diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
> index 3ecf2bde19f..3a67f25be56 100644
> --- a/gcc/config/mips/mips-msa.md
> +++ b/gcc/config/mips/mips-msa.md
> @@ -435,6 +435,28 @@
> DONE;
> })
>
> +(define_expand "vec_cmp<MSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:MSA 2 "register_operand")
> + (match_operand:MSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> +(define_expand "vec_cmpu<IMSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:IMSA 2 "register_operand")
> + (match_operand:IMSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> (define_insn "msa_insert_<msafmt_f>"
> [(set (match_operand:MSA 0 "register_operand" "=f,f")
> (vec_merge:MSA
> diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-
> protos.h
> index 2cf4ed50292..a685f7f7dd5 100644
> --- a/gcc/config/mips/mips-protos.h
> +++ b/gcc/config/mips/mips-protos.h
> @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum
> rtx_code);
>
> extern void mips_register_frame_header_opt (void);
> extern void mips_expand_vec_cond_expr (machine_mode, machine_mode,
> rtx *);
> +extern void mips_expand_vec_cmp_expr (rtx *);
>
> /* Routines implemented in mips-d.c */
> extern void mips_d_target_versions (void);
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 00a8eef96aa..8f043399a8e 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code
> cond, rtx op0, rtx op1)
> }
> }
>
> +void
> +mips_expand_vec_cmp_expr (rtx *operands)
> +{
> + rtx cond = operands[1];
> + rtx op0 = operands[2];
> + rtx op1 = operands[3];
> + rtx res = operands[0];
> +
> + mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
> +}
> +
> /* Expand VEC_COND_EXPR, where:
> MODE is mode of the result
> VIMODE equivalent integer mode
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread* PING^4: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-06-21 13:42 [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132] Xi Ruoyao
2021-07-01 8:11 ` Xi Ruoyao
2021-07-16 5:57 ` PING^3: " Xi Ruoyao
@ 2021-07-23 12:46 ` Xi Ruoyao
2021-07-30 4:56 ` PING^5: " Xi Ruoyao
3 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2021-07-23 12:46 UTC (permalink / raw)
To: gcc-patches
Cc: Martin Li�0�8ka, Matthew Fortune,
Maciej W. Rozycki, Richard Sandiford, xry111
Ping again.
On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
> Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
> ICE on MIPS with MSA enabled. Add the pattern to prevent it.
>
> Bootstrapped and regression tested on mips64el-linux-gnu.
> Ok for trunk?
>
> gcc/
>
> * config/mips/mips-protos.h (mips_expand_vec_cmp_expr): Declare.
> * config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
> * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
> expander.
> (vec_cmpu<IMSA:mode><mode_i>): New expander.
> ---
> gcc/config/mips/mips-msa.md | 22 ++++++++++++++++++++++
> gcc/config/mips/mips-protos.h | 1 +
> gcc/config/mips/mips.c | 11 +++++++++++
> 3 files changed, 34 insertions(+)
>
> diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
> index 3ecf2bde19f..3a67f25be56 100644
> --- a/gcc/config/mips/mips-msa.md
> +++ b/gcc/config/mips/mips-msa.md
> @@ -435,6 +435,28 @@
> DONE;
> })
>
> +(define_expand "vec_cmp<MSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:MSA 2 "register_operand")
> + (match_operand:MSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> +(define_expand "vec_cmpu<IMSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:IMSA 2 "register_operand")
> + (match_operand:IMSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> (define_insn "msa_insert_<msafmt_f>"
> [(set (match_operand:MSA 0 "register_operand" "=f,f")
> (vec_merge:MSA
> diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
> index 2cf4ed50292..a685f7f7dd5 100644
> --- a/gcc/config/mips/mips-protos.h
> +++ b/gcc/config/mips/mips-protos.h
> @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum rtx_code);
>
> extern void mips_register_frame_header_opt (void);
> extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
> +extern void mips_expand_vec_cmp_expr (rtx *);
>
> /* Routines implemented in mips-d.c */
> extern void mips_d_target_versions (void);
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 00a8eef96aa..8f043399a8e 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1)
> }
> }
>
> +void
> +mips_expand_vec_cmp_expr (rtx *operands)
> +{
> + rtx cond = operands[1];
> + rtx op0 = operands[2];
> + rtx op1 = operands[3];
> + rtx res = operands[0];
> +
> + mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
> +}
> +
> /* Expand VEC_COND_EXPR, where:
> MODE is mode of the result
> VIMODE equivalent integer mode
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread* PING^5: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-06-21 13:42 [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132] Xi Ruoyao
` (2 preceding siblings ...)
2021-07-23 12:46 ` PING^4: " Xi Ruoyao
@ 2021-07-30 4:56 ` Xi Ruoyao
2021-07-30 8:04 ` Richard Sandiford
3 siblings, 1 reply; 12+ messages in thread
From: Xi Ruoyao @ 2021-07-30 4:56 UTC (permalink / raw)
To: gcc-patches
Cc: Martin Li�0�8ka, Matthew Fortune,
Maciej W. Rozycki, Richard Sandiford, xry111
Ping again.
On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
> Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
> ICE on MIPS with MSA enabled. Add the pattern to prevent it.
>
> Bootstrapped and regression tested on mips64el-linux-gnu.
> Ok for trunk?
>
> gcc/
>
> * config/mips/mips-protos.h (mips_expand_vec_cmp_expr):
> Declare.
> * config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
> * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
> expander.
> (vec_cmpu<IMSA:mode><mode_i>): New expander.
> ---
> gcc/config/mips/mips-msa.md | 22 ++++++++++++++++++++++
> gcc/config/mips/mips-protos.h | 1 +
> gcc/config/mips/mips.c | 11 +++++++++++
> 3 files changed, 34 insertions(+)
>
> diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
> index 3ecf2bde19f..3a67f25be56 100644
> --- a/gcc/config/mips/mips-msa.md
> +++ b/gcc/config/mips/mips-msa.md
> @@ -435,6 +435,28 @@
> DONE;
> })
>
> +(define_expand "vec_cmp<MSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:MSA 2 "register_operand")
> + (match_operand:MSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> +(define_expand "vec_cmpu<IMSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:IMSA 2 "register_operand")
> + (match_operand:IMSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> (define_insn "msa_insert_<msafmt_f>"
> [(set (match_operand:MSA 0 "register_operand" "=f,f")
> (vec_merge:MSA
> diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-
> protos.h
> index 2cf4ed50292..a685f7f7dd5 100644
> --- a/gcc/config/mips/mips-protos.h
> +++ b/gcc/config/mips/mips-protos.h
> @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum
> rtx_code);
>
> extern void mips_register_frame_header_opt (void);
> extern void mips_expand_vec_cond_expr (machine_mode, machine_mode,
> rtx *);
> +extern void mips_expand_vec_cmp_expr (rtx *);
>
> /* Routines implemented in mips-d.c */
> extern void mips_d_target_versions (void);
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 00a8eef96aa..8f043399a8e 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code
> cond, rtx op0, rtx op1)
> }
> }
>
> +void
> +mips_expand_vec_cmp_expr (rtx *operands)
> +{
> + rtx cond = operands[1];
> + rtx op0 = operands[2];
> + rtx op1 = operands[3];
> + rtx res = operands[0];
> +
> + mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
> +}
> +
> /* Expand VEC_COND_EXPR, where:
> MODE is mode of the result
> VIMODE equivalent integer mode
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: PING^5: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-07-30 4:56 ` PING^5: " Xi Ruoyao
@ 2021-07-30 8:04 ` Richard Sandiford
2021-07-30 8:17 ` Xi Ruoyao
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Richard Sandiford @ 2021-07-30 8:04 UTC (permalink / raw)
To: Xi Ruoyao; +Cc: gcc-patches, marxin, Matthew Fortune, Maciej W. Rozycki
Xi Ruoyao <xry111@mengyan1223.wang> writes:
> Ping again.
Sorry that this has gone unreviewed for so long. I think in practice
the MIPS port is essentially unmaintained at this point -- it would
be great if someone would volunteer :-)
It isn't really appropriate for me to review MIPS stuff given that I work
for a company that has a competing architecture. I think Jeff expressed
similar concerns given his new role.
That said, the patch looks clearly correct to me, so please go ahead
and apply (to trunk and GCC 11). Thanks for your patience.
Richard
> On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
>> Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
>> ICE on MIPS with MSA enabled. Add the pattern to prevent it.
>>
>> Bootstrapped and regression tested on mips64el-linux-gnu.
>> Ok for trunk?
>>
>> gcc/
>>
>> * config/mips/mips-protos.h (mips_expand_vec_cmp_expr):
>> Declare.
>> * config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
>> * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
>> expander.
>> (vec_cmpu<IMSA:mode><mode_i>): New expander.
>> ---
>> gcc/config/mips/mips-msa.md | 22 ++++++++++++++++++++++
>> gcc/config/mips/mips-protos.h | 1 +
>> gcc/config/mips/mips.c | 11 +++++++++++
>> 3 files changed, 34 insertions(+)
>>
>> diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
>> index 3ecf2bde19f..3a67f25be56 100644
>> --- a/gcc/config/mips/mips-msa.md
>> +++ b/gcc/config/mips/mips-msa.md
>> @@ -435,6 +435,28 @@
>> DONE;
>> })
>>
>> +(define_expand "vec_cmp<MSA:mode><mode_i>"
>> + [(match_operand:<VIMODE> 0 "register_operand")
>> + (match_operator 1 ""
>> + [(match_operand:MSA 2 "register_operand")
>> + (match_operand:MSA 3 "register_operand")])]
>> + "ISA_HAS_MSA"
>> +{
>> + mips_expand_vec_cmp_expr (operands);
>> + DONE;
>> +})
>> +
>> +(define_expand "vec_cmpu<IMSA:mode><mode_i>"
>> + [(match_operand:<VIMODE> 0 "register_operand")
>> + (match_operator 1 ""
>> + [(match_operand:IMSA 2 "register_operand")
>> + (match_operand:IMSA 3 "register_operand")])]
>> + "ISA_HAS_MSA"
>> +{
>> + mips_expand_vec_cmp_expr (operands);
>> + DONE;
>> +})
>> +
>> (define_insn "msa_insert_<msafmt_f>"
>> [(set (match_operand:MSA 0 "register_operand" "=f,f")
>> (vec_merge:MSA
>> diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-
>> protos.h
>> index 2cf4ed50292..a685f7f7dd5 100644
>> --- a/gcc/config/mips/mips-protos.h
>> +++ b/gcc/config/mips/mips-protos.h
>> @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum
>> rtx_code);
>>
>> extern void mips_register_frame_header_opt (void);
>> extern void mips_expand_vec_cond_expr (machine_mode, machine_mode,
>> rtx *);
>> +extern void mips_expand_vec_cmp_expr (rtx *);
>>
>> /* Routines implemented in mips-d.c */
>> extern void mips_d_target_versions (void);
>> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
>> index 00a8eef96aa..8f043399a8e 100644
>> --- a/gcc/config/mips/mips.c
>> +++ b/gcc/config/mips/mips.c
>> @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code
>> cond, rtx op0, rtx op1)
>> }
>> }
>>
>> +void
>> +mips_expand_vec_cmp_expr (rtx *operands)
>> +{
>> + rtx cond = operands[1];
>> + rtx op0 = operands[2];
>> + rtx op1 = operands[3];
>> + rtx res = operands[0];
>> +
>> + mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
>> +}
>> +
>> /* Expand VEC_COND_EXPR, where:
>> MODE is mode of the result
>> VIMODE equivalent integer mode
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: PING^5: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-07-30 8:04 ` Richard Sandiford
@ 2021-07-30 8:17 ` Xi Ruoyao
2021-07-30 18:06 ` committed: " Xi Ruoyao
2021-07-30 8:30 ` PING^5: " Richard Biener
2021-07-30 15:57 ` Jeff Law
2 siblings, 1 reply; 12+ messages in thread
From: Xi Ruoyao @ 2021-07-30 8:17 UTC (permalink / raw)
To: Richard Sandiford; +Cc: gcc-patches, marxin, Matthew Fortune, Maciej W. Rozycki
On Fri, 2021-07-30 at 09:04 +0100, Richard Sandiford wrote:
> Xi Ruoyao <xry111@mengyan1223.wang> writes:
> > Ping again.
>
> Sorry that this has gone unreviewed for so long. I think in practice
> the MIPS port is essentially unmaintained at this point -- it would
> be great if someone would volunteer :-)
A company working on MIPS has contacted me and said one of their
employees may contact the SC and take the role of MIPS maintainer. Not
sure their progress though.
> It isn't really appropriate for me to review MIPS stuff given that I
> work
> for a company that has a competing architecture. I think Jeff
> expressed
> similar concerns given his new role.
> That said, the patch looks clearly correct to me, so please go ahead
> and apply (to trunk and GCC 11). Thanks for your patience.
Thanks!
It has been 5 weeks so it's better to rebase and bootstrap & test it
again. I'll commit it if there is no regression.
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread
* committed: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-07-30 8:17 ` Xi Ruoyao
@ 2021-07-30 18:06 ` Xi Ruoyao
0 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2021-07-30 18:06 UTC (permalink / raw)
To: Richard Sandiford; +Cc: marxin, Matthew Fortune, gcc-patches, Maciej W. Rozycki
On Fri, 2021-07-30 at 16:17 +0800, Xi Ruoyao via Gcc-patches wrote:
> On Fri, 2021-07-30 at 09:04 +0100, Richard Sandiford wrote:
> > Xi Ruoyao <xry111@mengyan1223.wang> writes:
> > > Ping again.
> >
> > Sorry that this has gone unreviewed for so long. I think in
> > practice
> > the MIPS port is essentially unmaintained at this point -- it would
> > be great if someone would volunteer :-)
>
> A company working on MIPS has contacted me and said one of their
> employees may contact the SC and take the role of MIPS maintainer.
> Not
> sure their progress though.
>
> > It isn't really appropriate for me to review MIPS stuff given that I
> > work
> > for a company that has a competing architecture. I think Jeff
> > expressed
> > similar concerns given his new role.
>
> > That said, the patch looks clearly correct to me, so please go ahead
> > and apply (to trunk and GCC 11). Thanks for your patience.
>
> Thanks!
>
> It has been 5 weeks so it's better to rebase and bootstrap & test it
> again. I'll commit it if there is no regression.
Committed to master at 45cb789e and releases/gcc-11 at 2a47ee78.
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: PING^5: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-07-30 8:04 ` Richard Sandiford
2021-07-30 8:17 ` Xi Ruoyao
@ 2021-07-30 8:30 ` Richard Biener
2021-07-30 12:13 ` Maciej W. Rozycki
2021-07-30 15:57 ` Jeff Law
2 siblings, 1 reply; 12+ messages in thread
From: Richard Biener @ 2021-07-30 8:30 UTC (permalink / raw)
To: Richard Sandiford, Xi Ruoyao, GCC Patches, marxin,
Matthew Fortune, Maciej W. Rozycki
On Fri, Jul 30, 2021 at 10:06 AM Richard Sandiford via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Xi Ruoyao <xry111@mengyan1223.wang> writes:
> > Ping again.
>
> Sorry that this has gone unreviewed for so long. I think in practice
> the MIPS port is essentially unmaintained at this point -- it would
> be great if someone would volunteer :-)
>
> It isn't really appropriate for me to review MIPS stuff given that I work
> for a company that has a competing architecture. I think Jeff expressed
> similar concerns given his new role.
I think that should be a non-issue unless it is an issue between you
and your employer (I realize some companies even restrict what you
can do in your spare time). We trust maintainers / reviewers to do
the right thing(TM) for the GCC project even when it is against the
interest of the company they are employed by. That is, not push
crap even if it is in the area of your maintainership.
Richard.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: PING^5: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-07-30 8:30 ` PING^5: " Richard Biener
@ 2021-07-30 12:13 ` Maciej W. Rozycki
0 siblings, 0 replies; 12+ messages in thread
From: Maciej W. Rozycki @ 2021-07-30 12:13 UTC (permalink / raw)
To: Richard Biener
Cc: Richard Sandiford, Xi Ruoyao, GCC Patches, marxin, Matthew Fortune
On Fri, 30 Jul 2021, Richard Biener wrote:
> > It isn't really appropriate for me to review MIPS stuff given that I work
> > for a company that has a competing architecture. I think Jeff expressed
> > similar concerns given his new role.
>
> I think that should be a non-issue unless it is an issue between you
> and your employer (I realize some companies even restrict what you
> can do in your spare time).
That is exactly the point, and I understand the ethical concerns even if
such activity has not been explicitly restricted by an employment contract
one has entered into and has been bound by.
> We trust maintainers / reviewers to do
> the right thing(TM) for the GCC project even when it is against the
> interest of the company they are employed by. That is, not push
> crap even if it is in the area of your maintainership.
That I think is undoubtable.
Maciej
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: PING^5: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
2021-07-30 8:04 ` Richard Sandiford
2021-07-30 8:17 ` Xi Ruoyao
2021-07-30 8:30 ` PING^5: " Richard Biener
@ 2021-07-30 15:57 ` Jeff Law
2 siblings, 0 replies; 12+ messages in thread
From: Jeff Law @ 2021-07-30 15:57 UTC (permalink / raw)
To: Xi Ruoyao, gcc-patches, marxin, Matthew Fortune,
Maciej W. Rozycki, richard.sandiford
On 7/30/2021 2:04 AM, Richard Sandiford via Gcc-patches wrote:
> Xi Ruoyao <xry111@mengyan1223.wang> writes:
>> Ping again.
> Sorry that this has gone unreviewed for so long. I think in practice
> the MIPS port is essentially unmaintained at this point -- it would
> be great if someone would volunteer :-)
Yup.
>
> It isn't really appropriate for me to review MIPS stuff given that I work
> for a company that has a competing architecture. I think Jeff expressed
> similar concerns given his new role.
Right, I'm largely in the same boat as well. I've been given a degree
of freedom, but I'm very cognizant of not raising conflict of interest
concerns with my employer. Some trivial patch review for a port is OK,
but the more substantial it is, the closer it is to the line that I
don't want to cross.
Jeff
^ permalink raw reply [flat|nested] 12+ messages in thread