Ping: [PATCH v2] rs6000: Convert the vector element register to SImode [PR98914]

[Xionghu Luo <luoxhu@linux.ibm.com>]

On 2021/2/25 14:33, Xionghu Luo via Gcc-patches wrote:
> 
> 
> On 2021/2/25 00:57, Segher Boessenkool wrote:
>> Hi!
>>
>> On Wed, Feb 24, 2021 at 09:06:24AM +0800, Xionghu Luo wrote:
>>> vec_insert defines the element argument type to be signed int by ELFv2
>>> ABI, When expanding a vector with a variable rtx, convert the rtx type
>>> SImode.
>>
>> But that is true for the intrinsics, not for all other callers of
>> rs6000_expand_vector_init.  See
>> <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98914#c2> as well?
>>
>> So I don't think you do this in the right place.  You can convince me
>> with good arguments of course :-)
> 
> Thanks for pointing out, it seems we should convert the type to DImode in
> rs6000_expand_vector_set_var_p9 and rs6000_expand_vector_set_var_p8
> to support both usage?
> 
> 
> PS: for "vec_insert (i, u, n)" usage when n is long, what should the front-end
> do in altivec_resolve_overloaded_builtin to follow the ELFv2 rule?  Currently,
> no warning/error message or conversion there, INTEGRAL_TYPE_P range is much larger
> than signed int.

long to int should follow implicit transformation, so no need change here.
Ping the patch, thanks.


BR,
Xionghu

> 
> 
> 
> Updated the back-end patch as below.
> 
> 
> 0001-rs6000-Convert-the-vector-set-variable-idx-to-DImode.patch
> 
> 
> vec_insert defines the element argument type to be signed int by ELFv2
> ABI.  When expanding a vector with a variable rtx, convert the rtx type
> to DImode to support both intrinsic usage and other callers from
> rs6000_expand_vector_init produced by v[k] = val when k is long type.
> 
> gcc/ChangeLog:
> 
> 2021-02-25  Xionghu Luo  <luoxhu@linux.ibm.com>
> 
> 	PR target/98914
> 	* config/rs6000/rs6000.c (rs6000_expand_vector_set_var_p9):
> 	Convert idx to DImode.
> 	(rs6000_expand_vector_set_var_p8): Likewise.
> 
> gcc/testsuite/ChangeLog:
> 
> 2021-02-25  Xionghu Luo  <luoxhu@linux.ibm.com>
> 
> 	PR target/98914
> 	* gcc.target/powerpc/pr98914.c: New test.
> ---
>   gcc/config/rs6000/rs6000.c                 | 33 +++++++++++++---------
>   gcc/testsuite/gcc.target/powerpc/pr98914.c | 11 ++++++++
>   2 files changed, 30 insertions(+), 14 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/powerpc/pr98914.c
> 
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index ec068c58aa5..48eb91132a9 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -7000,11 +7000,15 @@ rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
> 
>     gcc_assert (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (idx));
> 
> -  gcc_assert (GET_MODE (idx) == E_SImode);
> -
>     machine_mode inner_mode = GET_MODE (val);
> 
> -  rtx tmp = gen_reg_rtx (GET_MODE (idx));
> +  machine_mode idx_mode = GET_MODE (idx);
> +  rtx tmp = gen_reg_rtx (DImode);
> +  if (idx_mode != DImode)
> +    tmp = convert_modes (DImode, idx_mode, idx, 0);
> +  else
> +    tmp = idx;
> +
>     int width = GET_MODE_SIZE (inner_mode);
> 
>     gcc_assert (width >= 1 && width <= 8);
> @@ -7012,9 +7016,7 @@ rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
>     int shift = exact_log2 (width);
>     /* Generate the IDX for permute shift, width is the vector element size.
>        idx = idx * width.  */
> -  emit_insn (gen_ashlsi3 (tmp, idx, GEN_INT (shift)));
> -
> -  tmp = convert_modes (DImode, SImode, tmp, 1);
> +  emit_insn (gen_ashldi3 (tmp, tmp, GEN_INT (shift)));
> 
>     /*  lvsr    v1,0,idx.  */
>     rtx pcvr = gen_reg_rtx (V16QImode);
> @@ -7047,27 +7049,31 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
> 
>     gcc_assert (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (idx));
> 
> -  gcc_assert (GET_MODE (idx) == E_SImode);
> -
>     machine_mode inner_mode = GET_MODE (val);
>     HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
> 
> -  rtx tmp = gen_reg_rtx (GET_MODE (idx));
>     int width = GET_MODE_SIZE (inner_mode);
> 
> +  machine_mode idx_mode = GET_MODE (idx);
> +  rtx tmp = gen_reg_rtx (DImode);
> +  if (idx_mode != DImode)
> +    tmp = convert_modes (DImode, idx_mode, idx, 0);
> +  else
> +    tmp = idx;
> +
>     gcc_assert (width >= 1 && width <= 4);
> 
>     if (!BYTES_BIG_ENDIAN)
>       {
>         /*  idx = idx * width.  */
> -      emit_insn (gen_mulsi3 (tmp, idx, GEN_INT (width)));
> +      emit_insn (gen_muldi3 (tmp, tmp, GEN_INT (width)));
>         /*  idx = idx + 8.  */
> -      emit_insn (gen_addsi3 (tmp, tmp, GEN_INT (8)));
> +      emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (8)));
>       }
>     else
>       {
> -      emit_insn (gen_mulsi3 (tmp, idx, GEN_INT (width)));
> -      emit_insn (gen_subsi3 (tmp, GEN_INT (24 - width), tmp));
> +      emit_insn (gen_muldi3 (tmp, idx, GEN_INT (width)));
> +      emit_insn (gen_subdi3 (tmp, GEN_INT (24 - width), tmp));
>       }
> 
>     /*  lxv vs33, mask.
> @@ -7118,7 +7124,6 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
>     emit_insn (gen_rtx_SET (val_v16qi, sub_val));
> 
>     /*  lvsl    13,0,idx.  */
> -  tmp = convert_modes (DImode, SImode, tmp, 1);
>     rtx pcv = gen_reg_rtx (V16QImode);
>     emit_insn (gen_altivec_lvsl_reg (pcv, tmp));
> 
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr98914.c b/gcc/testsuite/gcc.target/powerpc/pr98914.c
> new file mode 100644
> index 00000000000..e4d78e3e6b3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr98914.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_p8vector_ok } */
> +/* { dg-options "-Og -mvsx" } */
> +
> +vector int
> +foo (vector int v)
> +{
> +  for (long k = 0; k < 1; ++k)
> +    v[k] = 0;
> +  return v;
> +}
> 

-- 
Thanks,
Xionghu