From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.ex10.biz (ikhexhub04.ex10.biz [178.170.125.68]) by sourceware.org (Postfix) with ESMTPS id 663973858430 for ; Tue, 18 Jul 2023 09:50:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 663973858430 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=sipearl.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sipearl.com Received: from ex13mbxc01n02.ikhex.ikoula.com (178.170.74.67) by ikhexhub04.ikhex.ikoula.com (178.170.125.68) with Microsoft SMTP Server (TLS) id 14.3.487.0; Tue, 18 Jul 2023 11:50:30 +0200 Received: from ex13mbxc01n01.ikhex.ikoula.com (2002:b2aa:4a42::b2aa:4a42) by ex13mbxc01n02.ikhex.ikoula.com (2002:b2aa:4a43::b2aa:4a43) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 18 Jul 2023 11:50:18 +0200 Received: from ex13mbxc01n01.ikhex.ikoula.com ([fe80::7cfa:8f3a:5d4b:2d27]) by ex13mbxc01n01.ikhex.ikoula.com ([fe80::7cfa:8f3a:5d4b:2d27%15]) with mapi id 15.00.1497.044; Tue, 18 Jul 2023 11:50:18 +0200 From: Serval Martinot-Lagarde To: "gcc-patches@gcc.gnu.org" CC: Etienne Renault Subject: [PATCH] aarch64: remove useless pairs of rev instructions Thread-Topic: [PATCH] aarch64: remove useless pairs of rev instructions Thread-Index: Adm5WVcvhBV9J1WoShmM7LuU7QskIQ== Date: Tue, 18 Jul 2023 09:50:18 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [178.170.125.114] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: SVE generates superflous rev instructions that can be replaced by single mov instruction or a pair of (rev, mov) instructions gcc/ * config/aarch64/aarch64-sve.md: New peephole2. * testsuite/gcc.target/aarch64/sve/revrev.c: New dg test. Signed-off-by: Serval Martinot-Lagarde --- gcc/config/aarch64/aarch64-sve.md | 21 +++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/revrev.c | 13 ++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/revrev.c diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64= -sve.md index da5534c3e32..e5e0c7ddfc5 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8836,6 +8836,27 @@ "TARGET_SVE" "rev\t%0., %1.") =20 +(define_peephole2 + [(set (match_operand:SVE_ALL 0 "register_operand" "") + (unspec:SVE_ALL + [(match_operand:SVE_ALL 1 "register_operand" "")] UNSPEC_REV)) + (set (match_operand:SVE_ALL 2 "register_operand" "") + (unspec:SVE_ALL + [(match_dup 0)] UNSPEC_REV))] + "TARGET_SVE" + [(const_int 0)] + { + if (REGNO (operands[2]) !=3D REGNO (operands[0])) + { + emit_insn (gen_rtx_SET (operands[2], operands[1])); + rtx rev =3D gen_rtx_UNSPEC (mode, gen_rtvec (1, operands[1]), = UNSPEC_REV); + emit_insn (gen_rtx_SET (operands[0], rev)); + } + else + emit_insn (gen_rtx_SET (operands[0], operands[1])); + DONE; + }) + ;; -----------------------------------------------------------------------= -- ;; ---- [INT,FP] Special-purpose binary permutes ;; -----------------------------------------------------------------------= -- diff --git a/gcc/testsuite/gcc.target/aarch64/sve/revrev.c b/gcc/testsuite/= gcc.target/aarch64/sve/revrev.c new file mode 100644 index 00000000000..04af6eed291 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/revrev.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#include + +void +test (uint8_t a[], uint8_t b[], uint64_t N) +{ + for (uint64_t i =3D N; i > 0; i--) + a[i - 1] =3D b[i - 1]; +} + +/* { dg-final { scan-assembler-not {\trev\t(z[0-9]+\.h), \1\n\trev\t\1, \1= \n} } } */ --=20 2.21.0