From: Jeff Law <jeffreyalaw@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Kito Cheng <kito.cheng@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/2] RISC-V: Make bit manipulation value / round number and shift amount types for builtins unsigned
Date: Sun, 17 Sep 2023 09:58:12 -0600 [thread overview]
Message-ID: <c1bdf0e3-332a-4c7d-8c6c-5cb1c557adde@gmail.com> (raw)
In-Reply-To: <addbfa6b9ff68058beb7e248812d12d408a5afe6.1694482087.git.research_trasio@irq.a4lg.com>
On 9/11/23 19:28, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> For bit manipulation operations, input(s) and the manipulated output are
> better to be unsigned like other target-independent builtins like
> __builtin_bswap32 and __builtin_popcount.
>
> Although this is not completely compatible as before (as the type changes),
> most code will run normally, even without warnings (with -Wall -Wextra).
>
> To make consistent to the LLVM commit 599421ae36c3 ("[RISCV] Use unsigned
> instead of signed types for Zk* and Zb* builtins."), round numbers and
> shift amount on the scalar crypto instructions are also changed
> to unsigned.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-builtins.cc (RISCV_ATYPE_UQI): New for
> uint8_t. (RISCV_ATYPE_UHI): New for uint16_t.
> (RISCV_ATYPE_QI, RISCV_ATYPE_HI, RISCV_ATYPE_SI, RISCV_ATYPE_DI):
> Removed as no longer used.
> (RISCV_ATYPE_UDI): New for uint64_t.
> * config/riscv/riscv-cmo.def: Make types unsigned for not working
> "zicbop_cbo_prefetchi" and working bit manipulation clmul builtin
> argument/return types.
> * config/riscv/riscv-ftypes.def: Make bit manipulation, round
> number and shift amount types unsigned.
> * config/riscv/riscv-scalar-crypto.def: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zbc32.c: Make signed type to unsigned.
> * gcc.target/riscv/zbc64.c: Ditto.
> * gcc.target/riscv/zbkb32.c: Ditto.
> * gcc.target/riscv/zbkb64.c: Ditto.
> * gcc.target/riscv/zbkc32.c: Ditto.
> * gcc.target/riscv/zbkc64.c: Ditto.
> * gcc.target/riscv/zbkx32.c: Ditto.
> * gcc.target/riscv/zbkx64.c: Ditto.
> * gcc.target/riscv/zknd32.c: Ditto.
> * gcc.target/riscv/zknd64.c: Ditto.
> * gcc.target/riscv/zkne32.c: Ditto.
> * gcc.target/riscv/zkne64.c: Ditto.
> * gcc.target/riscv/zknh-sha256.c: Ditto.
> * gcc.target/riscv/zknh-sha512-32.c: Ditto.
> * gcc.target/riscv/zknh-sha512-64.c: Ditto.
> * gcc.target/riscv/zksed32.c: Ditto.
> * gcc.target/riscv/zksed64.c: Ditto.
> * gcc.target/riscv/zksh32.c: Ditto.
> * gcc.target/riscv/zksh64.c: Ditto.
OK
Jeff
> ---
next prev parent reply other threads:[~2023-09-17 15:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-07 2:17 [RFC PATCH 0/2] RISC-V: Change RISC-V bit manipulation / scalar crypto builtin types Tsukasa OI
2023-09-07 2:17 ` [RFC PATCH 1/2] RISC-V: Make bit manipulation value / round number and shift amount types for builtins unsigned Tsukasa OI
2023-09-07 2:17 ` [RFC PATCH 2/2] RISC-V: Update testsuite for type-changed builtins Tsukasa OI
2023-09-17 15:58 ` Jeff Law
2023-09-08 1:03 ` [RFC PATCH 0/1] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t Tsukasa OI
2023-09-08 1:03 ` [RFC PATCH 1/1] " Tsukasa OI
2023-09-12 1:28 ` [PATCH 0/2] RISC-V: Change RISC-V bit manipulation / scalar crypto builtin types Tsukasa OI
2023-09-12 1:28 ` [PATCH 1/2] RISC-V: Make bit manipulation value / round number and shift amount types for builtins unsigned Tsukasa OI
2023-09-17 15:58 ` Jeff Law [this message]
2023-09-12 1:28 ` [PATCH 2/2] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t Tsukasa OI
2023-09-12 2:44 ` Kito Cheng
2023-09-12 3:20 ` Tsukasa OI
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