From: "Kewen.Lin" <linkw@linux.ibm.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Bill Schmidt <wschmidt@linux.ibm.com>,
"bin.cheng" <bin.cheng@linux.alibaba.com>,
Richard Guenther <rguenther@suse.de>
Subject: [PATCH 4/4 v2 GCC11] rs6000: P9 D-form test cases
Date: Mon, 10 Feb 2020 06:25:00 -0000 [thread overview]
Message-ID: <c2905934-8cfb-ee76-c53e-c04803049a67@linux.ibm.com> (raw)
In-Reply-To: <20200120131948.GY3191@gate.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 1013 bytes --]
Hi Segher,
Updated as below according to your suggestion.
BR,
Kewen
--------
gcc/testsuite/ChangeLog
2020-02-10 Kelvin Nilsen <kelvin@gcc.gnu.org>
Kewen Lin <linkw@gcc.gnu.org>
* gcc.target/powerpc/p9-dform-0.c: New test.
* gcc.target/powerpc/p9-dform-1.c: New test.
* gcc.target/powerpc/p9-dform-2.c: New test.
* gcc.target/powerpc/p9-dform-3.c: New test.
* gcc.target/powerpc/p9-dform-4.c: New test.
* gcc.target/powerpc/p9-dform-generic.h: New test.
on 2020/1/20 脧脗脦莽9:19, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Jan 16, 2020 at 05:42:41PM +0800, Kewen.Lin wrote:
>> +/* At time the dform optimization pass was merged with trunk, 12
>> + lxv instructions were emitted in place of the same number of lxvx
>> + instructions. No need to require exactly this number, as it may
>> + change when other optimization passes evolve. */
>> +
>> +/* { dg-final { scan-assembler {\mlxv\M} } } */
>
> Maybe you can also test there ar no lxvx insns generated?
>
Done, thanks!
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---
gcc/testsuite/gcc.target/powerpc/p9-dform-0.c | 44 +++++++++++++++++
gcc/testsuite/gcc.target/powerpc/p9-dform-1.c | 57 ++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/p9-dform-2.c | 14 ++++++
gcc/testsuite/gcc.target/powerpc/p9-dform-3.c | 17 +++++++
gcc/testsuite/gcc.target/powerpc/p9-dform-4.c | 14 ++++++
.../gcc.target/powerpc/p9-dform-generic.h | 34 +++++++++++++
6 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-dform-0.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-dform-1.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-dform-2.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-dform-3.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-dform-4.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-dform-generic.h
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dform-0.c b/gcc/testsuite/gcc.target/powerpc/p9-dform-0.c
new file mode 100644
index 0000000..68b0434
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dform-0.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-O3 -mdejagnu-cpu=power9 -funroll-loops" } */
+
+/* This test confirms that the dform instructions are selected in the
+ translation of this main program. */
+
+extern void first_dummy ();
+extern void dummy (double sacc, int n);
+extern void other_dummy ();
+
+extern float opt_value;
+extern char *opt_desc;
+
+#define M 128
+#define N 512
+
+double x [N];
+double y [N];
+
+int main (int argc, char *argv []) {
+ double sacc;
+
+ first_dummy ();
+ for (int j = 0; j < M; j++) {
+
+ sacc = 0.00;
+ for (unsigned long long int i = 0; i < N; i++) {
+ sacc += x[i] * y[i];
+ }
+ dummy (sacc, N);
+ }
+ opt_value = ((float) N) * 2 * ((float) M);
+ opt_desc = "flops";
+ other_dummy ();
+}
+
+/* At time the dform optimization pass was merged with trunk, 12
+ lxv instructions were emitted in place of the same number of lxvx
+ instructions. No need to require exactly this number, as it may
+ change when other optimization passes evolve. */
+
+/* { dg-final { scan-assembler {\mlxv\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvx\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dform-1.c b/gcc/testsuite/gcc.target/powerpc/p9-dform-1.c
new file mode 100644
index 0000000..b80ffbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dform-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-O3 -mdejagnu-cpu=power9 -funroll-loops" } */
+
+/* This test confirms that the dform instructions are selected in the
+ translation of this main program. */
+
+extern void first_dummy ();
+extern void dummy (double sacc, int n);
+extern void other_dummy ();
+
+extern float opt_value;
+extern char *opt_desc;
+
+#define M 128
+#define N 512
+
+double x [N];
+double y [N];
+double z [N];
+
+int main (int argc, char *argv []) {
+ double sacc;
+
+ first_dummy ();
+ for (int j = 0; j < M; j++) {
+
+ sacc = 0.00;
+ for (unsigned long long int i = 0; i < N; i++) {
+ z[i] = x[i] * y[i];
+ sacc += z[i];
+ }
+ dummy (sacc, N);
+ }
+ opt_value = ((float) N) * 2 * ((float) M);
+ opt_desc = "flops";
+ other_dummy ();
+}
+
+
+
+/* At time the dform optimization pass was merged with trunk, 12
+ lxv instructions were emitted in place of the same number of lxvx
+ instructions. No need to require exactly this number, as it may
+ change when other optimization passes evolve. */
+
+/* { dg-final { scan-assembler {\mlxv\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvx\M} } } */
+
+/* At time the dform optimization pass was merged with trunk, 6
+ stxv instructions were emitted in place of the same number of stxvx
+ instructions. No need to require exactly this number, as it may
+ change when other optimization passes evolve. */
+
+/* { dg-final { scan-assembler {\mstxv\M} } } */
+/* { dg-final { scan-assembler-not {\mstxvx\M} } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dform-2.c b/gcc/testsuite/gcc.target/powerpc/p9-dform-2.c
new file mode 100644
index 0000000..51789d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dform-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-O3 -mdejagnu-cpu=power9 -funroll-loops" } */
+
+#define TYPE int
+#include "p9-dform-generic.h"
+
+/* The precise number of lxv and stxv instructions may be impacted by
+ complex interactions between optimization passes, but we expect at
+ least one of each. */
+/* { dg-final { scan-assembler {\mlxv\M} } } */
+/* { dg-final { scan-assembler {\mstxv\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvx\M} } } */
+/* { dg-final { scan-assembler-not {\mstxvx\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dform-3.c b/gcc/testsuite/gcc.target/powerpc/p9-dform-3.c
new file mode 100644
index 0000000..1a4b6c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dform-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-O3 -mdejagnu-cpu=power9 -funroll-loops" } */
+
+#define TYPE double
+#include "p9-dform-generic.h"
+
+/* At time the dform optimization pass was merged with trunk, 6
+ lxv instructions were emitted in place of the same number of lxvx
+ instructions and 8 stxv instructions replace the same number of
+ stxvx instructions. No need to require exactly this number, as it
+ may change when other optimization passes evolve. */
+
+/* { dg-final { scan-assembler {\mlxv\M} } } */
+/* { dg-final { scan-assembler {\mstxv\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvx\M} } } */
+/* { dg-final { scan-assembler-not {\mstxvx\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dform-4.c b/gcc/testsuite/gcc.target/powerpc/p9-dform-4.c
new file mode 100644
index 0000000..752f987
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dform-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9 -funroll-loops -mfloat128" } */
+
+#define TYPE __float128
+#include "p9-dform-generic.h"
+
+/* The precise number of lxv and stxv instructions may be impacted by
+ complex interactions between optimization passes, but we expect at
+ least one of each. */
+/* { dg-final { scan-assembler {\mlxv\M} } } */
+/* { dg-final { scan-assembler {\mstxv\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvx\M} } } */
+/* { dg-final { scan-assembler-not {\mstxvx\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dform-generic.h b/gcc/testsuite/gcc.target/powerpc/p9-dform-generic.h
new file mode 100644
index 0000000..3caed25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dform-generic.h
@@ -0,0 +1,34 @@
+
+#define ITERATIONS 1000000
+
+#define SIZE (16384/sizeof(TYPE))
+
+static TYPE x[SIZE] __attribute__ ((aligned (16)));
+static TYPE y[SIZE] __attribute__ ((aligned (16)));
+static TYPE a;
+
+void obfuscate(void *a, ...);
+
+static void __attribute__((noinline)) do_one(void)
+{
+ unsigned long i;
+
+ obfuscate(x, y, &a);
+
+ for (i = 0; i < SIZE; i++)
+ y[i] = a * x[i];
+
+ obfuscate(x, y, &a);
+
+}
+
+int main(void)
+{
+ unsigned long i;
+
+ for (i = 0; i < ITERATIONS; i++)
+ do_one();
+
+ return 0;
+
+}
--
2.7.4
next prev parent reply other threads:[~2020-02-10 6:25 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-16 9:41 [PATCH 0/4 GCC11] IVOPTs consider step cost for different forms when unrolling Kewen.Lin
2020-01-16 9:43 ` [PATCH 1/4 GCC11] Add middle-end unroll factor estimation Kewen.Lin
2020-01-20 13:12 ` Segher Boessenkool
2020-02-10 6:20 ` [PATCH 1/4 v2 " Kewen.Lin
2020-02-10 23:34 ` Segher Boessenkool
2020-02-11 6:51 ` [PATCH 1/4 v3 " Kewen.Lin
2020-02-11 7:00 ` Segher Boessenkool
2020-02-11 2:15 ` [PATCH 1/4 v2 " Jiufu Guo
2020-02-11 3:04 ` Kewen.Lin
2020-01-16 10:02 ` [PATCH 2/4 GCC11] Add target hook stride_dform_valid_p Kewen.Lin
2020-01-20 10:53 ` Richard Sandiford
2020-01-20 11:47 ` Richard Biener
2020-01-20 13:20 ` Segher Boessenkool
2020-02-25 9:46 ` Kewen.Lin
2020-03-02 11:09 ` Richard Sandiford
2020-03-03 12:26 ` Kewen.Lin
2020-05-13 5:50 ` Kewen.Lin
2020-05-28 2:17 ` Ping^1 [PATCH 2/4 V3] " Kewen.Lin
2020-05-28 10:54 ` Richard Sandiford
2020-01-16 10:06 ` [PATCH 3/4 GCC11] IVOPTs Consider cost_step on different forms during unrolling Kewen.Lin
2020-02-25 9:48 ` [PATCH 3/4 V2 " Kewen.Lin
2020-05-13 5:42 ` [PATCH 3/4 V3 " Kewen.Lin
2020-01-16 10:12 ` [PATCH 4/4 GCC11] rs6000: P9 D-form test cases Kewen.Lin
2020-01-20 13:37 ` Segher Boessenkool
2020-02-10 6:25 ` Kewen.Lin [this message]
2020-02-10 23:51 ` [PATCH 4/4 v2 " Segher Boessenkool
2020-01-20 13:03 ` [PATCH 0/4 GCC11] IVOPTs consider step cost for different forms when unrolling Segher Boessenkool
2020-02-10 6:17 ` Kewen.Lin
2020-02-10 21:29 ` Segher Boessenkool
2020-02-11 2:56 ` Kewen.Lin
2020-02-11 7:34 ` Richard Biener
2020-02-11 7:49 ` Segher Boessenkool
2020-02-11 8:01 ` Richard Biener
2020-02-11 12:46 ` Roman Zhuykov
2020-02-11 13:58 ` Richard Biener
2020-02-11 18:00 ` Segher Boessenkool
2020-02-12 8:07 ` Richard Biener
2020-02-12 21:53 ` Segher Boessenkool
2020-02-11 18:12 ` Segher Boessenkool
2020-02-12 8:13 ` Richard Biener
2020-02-12 10:02 ` Segher Boessenkool
2020-02-12 10:53 ` Richard Biener
2020-02-12 22:05 ` Segher Boessenkool
2020-02-13 7:48 ` Richard Biener
2020-02-13 9:02 ` Segher Boessenkool
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