From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id BEC203858CD1 for ; Fri, 23 Jun 2023 16:49:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BEC203858CD1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=linux.vnet.ibm.com Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35NGCQIM008352; Fri, 23 Jun 2023 16:49:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : from : subject : to : cc : content-type : content-transfer-encoding; s=pp1; bh=gMNUCejfpn5tm27C08GHBcfZbR+P4+7tyO1LN3c2frA=; b=ZYWxMrhg9/eHvredDYOE6326ZmTcDs74LW/ZuXYBKngpiPemMK8yFfBqy2ZuCML9Jx7H 46xZGFkn+ccaaAEb0beS7s5TOONjrYfMmjEr39/I1928wcaM7dKVwGlxQxTGQSpYgizP 0d+IJNxX1VYYdlo8xtnRNJzOPKrmNNRuX0KoOxwQ2CPlFGToJzf2qaZWTQy78x5sMh3W 6QFPYcyIWJ/G+MlTqboWqWA5HVFXsArNrq7LitzdknIU26wdmVMefxV28rzfY6WKf9q+ GRlSfUeeOquewe9Ao1qdes6WTBpuaDCP9seVCr2Nf5l6R6rLxHzUDobB3FAJFrVmk2bd mw== Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rdecf1du8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 16:49:25 +0000 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 35NGVBwT023777; Fri, 23 Jun 2023 16:49:24 GMT Received: from smtprelay03.dal12v.mail.ibm.com ([9.208.130.98]) by ppma04wdc.us.ibm.com (PPS) with ESMTPS id 3r94f67td2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 16:49:24 +0000 Received: from smtpav03.wdc07v.mail.ibm.com (smtpav03.wdc07v.mail.ibm.com [10.39.53.230]) by smtprelay03.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 35NGnMgd1311448 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 23 Jun 2023 16:49:23 GMT Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B7B295805A; Fri, 23 Jun 2023 16:49:22 +0000 (GMT) Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D967358054; Fri, 23 Jun 2023 16:49:20 +0000 (GMT) Received: from [9.43.38.144] (unknown [9.43.38.144]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTP; Fri, 23 Jun 2023 16:49:20 +0000 (GMT) Message-ID: Date: Fri, 23 Jun 2023 22:19:18 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Content-Language: en-US From: P Jeevitha Subject: [PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320] To: Segher Boessenkool , linkw@linux.ibm.com, gcc-patches@gcc.gnu.org Cc: Peter Bergner Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: gW2VWf7Hy9U86bwwqLC5cf4ybKfm3PRh X-Proofpoint-ORIG-GUID: gW2VWf7Hy9U86bwwqLC5cf4ybKfm3PRh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306230148 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile register. However, it can be used as volatile for PCREL addressing. Therefore, if the code is PCREL and the user is not explicitly requesting TOC addressing, then the register r2 can be changed to volatile and non-fixed register. Changes in register preservation roles can be accomplished with the help of available target hooks (TARGET_CONDITIONAL_REGISTER_USAGE). 2023-06-23 Jeevitha Palanisamy gcc/ PR target/PR110320 * config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change GPR2 to volatile and non-fixed register for pc-relative code. gcc/testsuite/ PR target/PR110320 * gcc.target/powerpc/pr110320_1.c: New testcase. * gcc.target/powerpc/pr110320_2.c: New testcase. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 546c353029b..9e978f85f9d 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10169,6 +10169,35 @@ rs6000_conditional_register_usage (void) if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) call_used_regs[2] = 0; + /* The TOC register is not needed for functions using the PC-relative ABI + extension, so make it available for register allocation as a volatile + register. */ + if (FIXED_R2 && rs6000_pcrel_p ()) + { + bool cli_fixedr2 = false; + + /* Verify the user has not explicitly asked for GPR2 to be fixed. */ + if (common_deferred_options) + { + unsigned int idx; + cl_deferred_option *opt; + vec v; + v = *((vec *) common_deferred_options); + FOR_EACH_VEC_ELT (v, idx, opt) + if (opt->opt_index == OPT_ffixed_ && strcmp (opt->arg,"r2") == 0) + { + cli_fixedr2 = true; + break; + } + } + + /* If GPR2 is not FIXED (eg, not a TOC register), then it is volatile. */ + if (!cli_fixedr2) + { + fixed_regs[2] = 0; + call_used_regs[2] = 1; + } + } if (DEFAULT_ABI == ABI_V4 && flag_pic == 2) fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_1.c b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c new file mode 100644 index 00000000000..42143fbf889 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c @@ -0,0 +1,23 @@ +/* PR target/110320 */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r11 and r12. That leaves RA to choose from r2 and the more + expensive non-volatile registers for the temporary to be assigned to, and + RA will always chooses the cheaper volatile r2 register. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler {\madd 2,3,4\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_2.c b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c new file mode 100644 index 00000000000..9d0da5b9695 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c @@ -0,0 +1,22 @@ +/* PR target/110320 */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-require-effective-target powerpc_pcrel } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-pcrel -ffixed-r0 -ffixed-r11 -ffixed-r12" } */ + +/* Ensure we don't use r2 as a normal volatile register for the code below. + The test case ensures all of the parameter registers r3 - r10 are used + and needed after we compute the expression "x + y" which requires a + temporary. The -ffixed-r* options disallow using the other volatile + registers r0, r11 and r12. That only leaves RA to choose from the more + expensive non-volatile registers for the temporary to be assigned to. */ + +extern long bar (long, long, long, long, long, long, long, long *); + +long +foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10) +{ + *r10 = r3 + r4; + return bar (r3, r4, r5, r6, r7, r8, r9, r10); +} + +/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */