From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 253223858C52 for ; Thu, 21 Dec 2023 11:56:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 253223858C52 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 253223858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703159770; cv=none; b=Mxf0han8uqKD7je++fjZ0de2M8agoKI0PEN2HSDicO618+NfTkWplRAXrY1gfTApM/bHGfYOeZjVzYf3A0aa3R9jfOzRjZFzt2vUk9b6kJkSLOjOIVHhzZuy6Hp8izT7pk+qngd1QKduy5lNpxV/xfN2fEsl8hc92KFwmOu6riw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703159770; c=relaxed/simple; bh=yLNZlcEySgnIIQsomJOMqSRiIwIXS7pv9mQGPbML6WI=; h=DKIM-Signature:Message-ID:Subject:From:To:Date:MIME-Version; b=HjCROWANP1OvMfpaYWRjwrR8KzbBiMU8iK2O9P6H7OLmoRJ8UtsYUmsjhuFuFChX3xtk/v7frzbBmFPrerb/WJJiC50MRbvTGXsvEDSTur+B6MZd8NQZDjssCRH3bC+bW2vxFGFh5tzq+OfWoV0WSNhLzc8VgXbEUz92wBPshS4= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1703159766; bh=yLNZlcEySgnIIQsomJOMqSRiIwIXS7pv9mQGPbML6WI=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=Tt5eURyBgFCP8Ukg66Z1Nauobgjch75F+0aR03cmNubS5AjKih+ZcFU18ObMiqP22 eiuvkqpSElixfMbzhiMoG7KQFURAaR4lv8qzgSjDrNeE3bq5kSuu826lJBELTgJfig AgF6la5mslKF1wUQLZNK6yr4L5jH/nu1PEZtB4gw= Received: from [127.0.0.1] (unknown [IPv6:2001:470:683e::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 2655866A73; Thu, 21 Dec 2023 06:56:05 -0500 (EST) Message-ID: Subject: Ping: [PATCH] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn Date: Thu, 21 Dec 2023 19:56:04 +0800 In-Reply-To: <20231212064754.6623-1-xry111@xry111.site> References: <20231212064754.6623-1-xry111@xry111.site> Autocrypt: addr=xry111@xry111.site; prefer-encrypt=mutual; keydata=mDMEYnkdPhYJKwYBBAHaRw8BAQdAsY+HvJs3EVKpwIu2gN89cQT/pnrbQtlvd6Yfq7egugi0HlhpIFJ1b3lhbyA8eHJ5MTExQHhyeTExMS5zaXRlPoiTBBMWCgA7FiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQrKrSDhnnEOPHFgD8D9vUToTd1MF5bng9uPJq5y3DfpcxDp+LD3joA3U2TmwA/jZtN9xLH7CGDHeClKZK/ZYELotWfJsqRcthOIGjsdAPuDgEYnkdPhIKKwYBBAGXVQEFAQEHQG+HnNiPZseiBkzYBHwq/nN638o0NPwgYwH70wlKMZhRAwEIB4h4BBgWCgAgFiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwwACgkQrKrSDhnnEOPjXgD/euD64cxwqDIqckUaisT3VCst11RcnO5iRHm6meNIwj0BALLmWplyi7beKrOlqKfuZtCLbiAPywGfCNg8LOTt4iMD Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.2 MIME-Version: 1.0 X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Ping :). On Tue, 2023-12-12 at 14:47 +0800, Xi Ruoyao wrote: > The problem with peephole2 is it uses a naive sliding-window algorithm > and misses many cases.=C2=A0 For example: >=20 > =C2=A0=C2=A0=C2=A0 float a[10000]; > =C2=A0=C2=A0=C2=A0 float t() { return a[0] + a[8000]; } >=20 > is compiled to: >=20 > =C2=A0=C2=A0=C2=A0 la.local=C2=A0=C2=A0=C2=A0 $r13,a > =C2=A0=C2=A0=C2=A0 la.local=C2=A0=C2=A0=C2=A0 $r12,a+32768 > =C2=A0=C2=A0=C2=A0 fld.s=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $f1,$r13,0 > =C2=A0=C2=A0=C2=A0 fld.s=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $f0,$r12,-76= 8 > =C2=A0=C2=A0=C2=A0 fadd.s=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $f0,$f1,$f0 >=20 > by trunk.=C2=A0 But as we've explained in r14-4851, the following would b= e > better with -mexplicit-relocs=3Dauto: >=20 > =C2=A0=C2=A0=C2=A0 pcalau12i=C2=A0=C2=A0 $r13,%pc_hi20(a) > =C2=A0=C2=A0=C2=A0 pcalau12i=C2=A0=C2=A0 $r12,%pc_hi20(a+32000) > =C2=A0=C2=A0=C2=A0 fld.s=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $f1,$r13,%pc= _lo12(a) > =C2=A0=C2=A0=C2=A0 fld.s=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $f0,$r12,%pc= _lo12(a+32000) > =C2=A0=C2=A0=C2=A0 fadd.s=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $f0,$f1,$f0 >=20 > However the sliding-window algorithm just won't detect the pcalau12i/fld > pair to be optimized.=C2=A0 Use a define_insn_and_split in combine pass w= ill > work around the issue. >=20 > gcc/ChangeLog: >=20 > * config/loongarch/loongarch.md: > (simple_load): New > define_insn_and_split. > (simple_load_off): Likewise. > (simple_load_ext): Likewise. > (simple_load_offext): > Likewise. > (simple_store): Likewise. > (simple_store_off): Likewise. > (define_peephole2): Remove la.local/[f]ld peepholes. >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/loongarch/explicit-relocs-auto-single-load-store-2.c: > New test. > --- >=20 > Bootstrapped & regtested on loongarch64-linux-gnu.=C2=A0 Ok for trunk? >=20 > =C2=A0gcc/config/loongarch/loongarch.md=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 165 +++++++++--------- > =C2=A0...explicit-relocs-auto-single-load-store-2.c |=C2=A0 11 ++ > =C2=A02 files changed, 98 insertions(+), 78 deletions(-) > =C2=A0create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relo= cs-auto-single-load-store-2.c >=20 > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loo= ngarch.md > index 7b26d15aa4e..4009de408fb 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -4033,101 +4033,110 @@ (define_insn "loongarch_crcc_w__w" > =C2=A0;; > =C2=A0;; And if the pseudo op cannot be relaxed, we'll get a worse result= (with > =C2=A0;; 3 instructions). > -(define_peephole2 > -=C2=A0 [(set (match_operand:P 0 "register_operand") > - (match_operand:P 1 "symbolic_pcrel_operand")) > -=C2=A0=C2=A0 (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand"= ) > - (mem:LD_AT_LEAST_32_BIT (match_dup 0)))] > -=C2=A0 "la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > -=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \ > -=C2=A0=C2=A0 && (peep2_reg_dead_p (2, operands[0]) \ > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 || REGNO (operands[0]) =3D=3D REGNO= (operands[2]))" > -=C2=A0 [(set (match_dup 2) > - (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))] > +(define_insn_and_split "simple_load" > +=C2=A0 [(set (match_operand:LD_AT_LEAST_32_BIT 0 "register_operand" "=3D= r,f") > + (mem:LD_AT_LEAST_32_BIT > + =C2=A0 (match_operand:P 1 "symbolic_pcrel_operand" "")))] > +=C2=A0 "loongarch_pre_reload_split () \ > +=C2=A0=C2=A0 && la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > +=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)" > +=C2=A0 "#" > +=C2=A0 "" > +=C2=A0 [(set (match_dup 0) > + (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 2) (match_dup 1))))] > =C2=A0=C2=A0 { > -=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[0], ope= rands[1])); > +=C2=A0=C2=A0=C2=A0 operands[2] =3D gen_reg_rtx (Pmode); > +=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[2], ope= rands[1])); > =C2=A0=C2=A0 }) > =C2=A0 > -(define_peephole2 > -=C2=A0 [(set (match_operand:P 0 "register_operand") > - (match_operand:P 1 "symbolic_pcrel_operand")) > -=C2=A0=C2=A0 (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand"= ) > - (mem:LD_AT_LEAST_32_BIT (plus (match_dup 0) > - (match_operand 3 "const_int_operand"))))] > -=C2=A0 "la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > -=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \ > -=C2=A0=C2=A0 && (peep2_reg_dead_p (2, operands[0]) \ > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 || REGNO (operands[0]) =3D=3D REGNO= (operands[2]))" > -=C2=A0 [(set (match_dup 2) > - (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))] > +(define_insn_and_split "simple_load_off= " > +=C2=A0 [(set (match_operand:LD_AT_LEAST_32_BIT 0 "register_operand" "=3D= r,f") > + (mem:LD_AT_LEAST_32_BIT > + =C2=A0 (plus (match_operand:P 1 "symbolic_pcrel_operand" "") > + (match_operand 2 "const_int_operand" ""))))] > +=C2=A0 "loongarch_pre_reload_split () \ > +=C2=A0=C2=A0 && la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > +=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)" > +=C2=A0 "#" > +=C2=A0 "" > +=C2=A0 [(set (match_dup 0) > + (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 2) (match_dup 1))))] > =C2=A0=C2=A0 { > -=C2=A0=C2=A0=C2=A0 operands[1] =3D plus_constant (Pmode, operands[1], IN= TVAL (operands[3])); > -=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[0], ope= rands[1])); > +=C2=A0=C2=A0=C2=A0 HOST_WIDE_INT offset =3D INTVAL (operands[2]); > +=C2=A0=C2=A0=C2=A0 operands[2] =3D gen_reg_rtx (Pmode); > +=C2=A0=C2=A0=C2=A0 operands[1] =3D plus_constant (Pmode, operands[1], of= fset); > +=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[2], ope= rands[1])); > =C2=A0=C2=A0 }) > =C2=A0 > -(define_peephole2 > -=C2=A0 [(set (match_operand:P 0 "register_operand") > - (match_operand:P 1 "symbolic_pcrel_operand")) > -=C2=A0=C2=A0 (set (match_operand:GPR 2 "register_operand") > - (any_extend:GPR (mem:SUBDI (match_dup 0))))] > -=C2=A0 "la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > -=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \ > -=C2=A0=C2=A0 && (peep2_reg_dead_p (2, operands[0]) \ > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 || REGNO (operands[0]) =3D=3D REGNO= (operands[2]))" > -=C2=A0 [(set (match_dup 2) > - (any_extend:GPR (mem:SUBDI (lo_sum:P (match_dup 0) > - =C2=A0=C2=A0=C2=A0=C2=A0 (match_dup 1)))))] > +(define_insn_and_split "simple_load_ext" > +=C2=A0 [(set (match_operand:GPR 0 "register_operand" "=3Dr") > + (any_extend:GPR > + =C2=A0 (mem:SUBDI (match_operand:P 1 "symbolic_pcrel_operand" ""))))] > +=C2=A0 "loongarch_pre_reload_split () \ > +=C2=A0=C2=A0 && la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > +=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)" > +=C2=A0 "#" > +=C2=A0 "" > +=C2=A0 [(set (match_dup 0) > + (any_extend:GPR > + =C2=A0 (mem:SUBDI (lo_sum:P (match_dup 2) (match_dup 1)))))] > =C2=A0=C2=A0 { > -=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[0], ope= rands[1])); > +=C2=A0=C2=A0=C2=A0 operands[2] =3D gen_reg_rtx (Pmode); > +=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[2], ope= rands[1])); > =C2=A0=C2=A0 }) > =C2=A0 > -(define_peephole2 > -=C2=A0 [(set (match_operand:P 0 "register_operand") > - (match_operand:P 1 "symbolic_pcrel_operand")) > -=C2=A0=C2=A0 (set (match_operand:GPR 2 "register_operand") > +(define_insn_and_split > +=C2=A0 "simple_load_off_ext" > +=C2=A0 [(set (match_operand:GPR 0 "register_operand" "=3Dr") > + (any_extend:GPR > + =C2=A0 (mem:SUBDI > + =C2=A0=C2=A0=C2=A0 (plus (match_operand:P 1 "symbolic_pcrel_operand" ""= ) > + =C2=A0 (match_operand 2 "const_int_operand" "")))))] > +=C2=A0 "loongarch_pre_reload_split () \ > +=C2=A0=C2=A0 && la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > +=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)" > +=C2=A0 "#" > +=C2=A0 "" > +=C2=A0 [(set (match_dup 0) > =C2=A0 (any_extend:GPR > - =C2=A0 (mem:SUBDI (plus (match_dup 0) > - =C2=A0=C2=A0 (match_operand 3 "const_int_operand")))))] > -=C2=A0 "la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > -=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \ > -=C2=A0=C2=A0 && (peep2_reg_dead_p (2, operands[0]) \ > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 || REGNO (operands[0]) =3D=3D REGNO= (operands[2]))" > -=C2=A0 [(set (match_dup 2) > - (any_extend:GPR (mem:SUBDI (lo_sum:P (match_dup 0) > - =C2=A0=C2=A0=C2=A0=C2=A0 (match_dup 1)))))] > + =C2=A0 (mem:SUBDI (lo_sum:P (match_dup 2) (match_dup 1)))))] > =C2=A0=C2=A0 { > -=C2=A0=C2=A0=C2=A0 operands[1] =3D plus_constant (Pmode, operands[1], IN= TVAL (operands[3])); > -=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[0], ope= rands[1])); > +=C2=A0=C2=A0=C2=A0 HOST_WIDE_INT offset =3D INTVAL (operands[2]); > +=C2=A0=C2=A0=C2=A0 operands[2] =3D gen_reg_rtx (Pmode); > +=C2=A0=C2=A0=C2=A0 operands[1] =3D plus_constant (Pmode, operands[1], of= fset); > +=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[2], ope= rands[1])); > =C2=A0=C2=A0 }) > =C2=A0 > -(define_peephole2 > -=C2=A0 [(set (match_operand:P 0 "register_operand") > - (match_operand:P 1 "symbolic_pcrel_operand")) > -=C2=A0=C2=A0 (set (mem:ST_ANY (match_dup 0)) > - (match_operand:ST_ANY 2 "register_operand"))] > -=C2=A0 "la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > -=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \ > -=C2=A0=C2=A0 && (peep2_reg_dead_p (2, operands[0])) \ > -=C2=A0=C2=A0 && REGNO (operands[0]) !=3D REGNO (operands[2])" > -=C2=A0 [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_= dup 2))] > +(define_insn_and_split "simple_store" > +=C2=A0 [(set (mem:ST_ANY (match_operand:P 0 "symbolic_pcrel_operand")) > + (match_operand:ST_ANY 1 "register_operand" "r,f"))] > +=C2=A0 "loongarch_pre_reload_split () \ > +=C2=A0=C2=A0 && la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > +=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)" > +=C2=A0 "#" > +=C2=A0 "" > +=C2=A0 [(set (mem:ST_ANY (lo_sum:P (match_dup 2) (match_dup 0))) (match_= dup 1))] > =C2=A0=C2=A0 { > -=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[0], ope= rands[1])); > +=C2=A0=C2=A0=C2=A0 operands[2] =3D gen_reg_rtx (Pmode); > +=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[2], ope= rands[0])); > =C2=A0=C2=A0 }) > =C2=A0 > -(define_peephole2 > -=C2=A0 [(set (match_operand:P 0 "register_operand") > - (match_operand:P 1 "symbolic_pcrel_operand")) > -=C2=A0=C2=A0 (set (mem:ST_ANY (plus (match_dup 0) > - =C2=A0 (match_operand 3 "const_int_operand"))) > - (match_operand:ST_ANY 2 "register_operand"))] > -=C2=A0 "la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > -=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \ > -=C2=A0=C2=A0 && (peep2_reg_dead_p (2, operands[0])) \ > -=C2=A0=C2=A0 && REGNO (operands[0]) !=3D REGNO (operands[2])" > -=C2=A0 [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_= dup 2))] > +(define_insn_and_split "simple_store_off" > +=C2=A0 [(set (mem:ST_ANY > + =C2=A0 (plus (match_operand:P 0 "symbolic_pcrel_operand" "") > + (match_operand 1 "const_int_operand" ""))) > + (match_operand:ST_ANY 2 "register_operand" "r,f"))] > +=C2=A0 "loongarch_pre_reload_split () \ > +=C2=A0=C2=A0 && la_opt_explicit_relocs =3D=3D EXPLICIT_RELOCS_AUTO \ > +=C2=A0=C2=A0 && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM)" > +=C2=A0 "#" > +=C2=A0 "" > +=C2=A0 [(set (mem:ST_ANY (lo_sum:P (match_dup 1) (match_dup 0))) (match_= dup 2))] > =C2=A0=C2=A0 { > -=C2=A0=C2=A0=C2=A0 operands[1] =3D plus_constant (Pmode, operands[1], IN= TVAL (operands[3])); > -=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[0], ope= rands[1])); > +=C2=A0=C2=A0=C2=A0 HOST_WIDE_INT offset =3D INTVAL (operands[1]); > +=C2=A0=C2=A0=C2=A0 operands[1] =3D gen_reg_rtx (Pmode); > +=C2=A0=C2=A0=C2=A0 operands[0] =3D plus_constant (Pmode, operands[0], of= fset); > +=C2=A0=C2=A0=C2=A0 emit_insn (gen_pcalau12i_gr (operands[1], ope= rands[0])); > =C2=A0=C2=A0 }) > =C2=A0 > =C2=A0;; Synchronization instructions. > diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-auto-sing= le-load-store-2.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-auto= -single-load-store-2.c > new file mode 100644 > index 00000000000..42cb966d1e0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-auto-single-load= -store-2.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -march=3Dloongarch64 -mabi=3Dlp64d -mexplicit-reloc= s=3Dauto" } */ > + > +float a[8001]; > +float > +t (void) > +{ > +=C2=A0 return a[0] + a[8000]; > +} > + > +/* { dg-final { scan-assembler-not "la.local" } } */ --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University