From: Jeff Law <jeffreyalaw@gmail.com>
To: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>,
gcc-patches@gcc.gnu.org
Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com,
philipp.tomsich@vrull.eu, christoph.muellner@vrull.eu,
juzhe.zhong@rivai.ai, Jin Ma <jinma@linux.alibaba.com>,
Xianmiao Qu <cooper.qu@linux.alibaba.com>
Subject: Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
Date: Wed, 20 Dec 2023 11:22:03 -0700 [thread overview]
Message-ID: <c548e187-d3a6-4a07-a00c-85aa1eea1f8e@gmail.com> (raw)
In-Reply-To: <20231220123249.555-1-cooper.joshua@linux.alibaba.com>
On 12/20/23 05:32, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h
> (riscv_asm_output_opcode): New function.
> * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
>
> Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
> Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
> Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> gcc/config/riscv/riscv-protos.h | 1 +
> gcc/config/riscv/riscv.cc | 26 +++++++++++++++++++
> gcc/config/riscv/riscv.h | 4 +++
> .../riscv/rvv/xtheadvector/prefix.c | 12 +++++++++
> 4 files changed, 43 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index eaee53ce94e..f0eee71a18a 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -101,6 +101,7 @@ struct riscv_address_info {
> };
>
> /* Routines implemented in riscv.cc. */
> +extern void riscv_asm_output_opcode(FILE *asm_out_file, const char *p);
> extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
> extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
> extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 8ae65760b6e..d3010bed8d8 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5595,6 +5595,32 @@ riscv_get_v_regno_alignment (machine_mode mode)
> return lmul;
> }
>
> +void
> +riscv_asm_output_opcode(FILE *asm_out_file, const char *p)
Needs a function comment. There's several examples in this file you can
use to see the style we commonly use. And a minor formatting nit,
always put a space between a function name and an open paren.
> +{
> + if (!TARGET_XTHEADVECTOR)
> + return;
> +
> + if (current_output_insn == NULL_RTX)
> + return;
> +
> + /* We need to handle the 'vset' special case here since it cannot
> + be controlled by vector mode. */
> + if (!strncmp (p, "vset", 4))
> + {
> + fputs ("th.", asm_out_file);
> + return;
> + }
> +
> + subrtx_iterator::array_type array;
> + FOR_EACH_SUBRTX (iter, array, PATTERN (current_output_insn), ALL)
> + if (*iter && riscv_v_ext_mode_p (GET_MODE (*iter)) && p[0] == 'v')
> + {
> + fputs ("th.", asm_out_file);
> + return;
> + }
> +}
So rather than looking at the mode, would it make more sense to have an
attribute (or re-use an existing attribute) to identify which opcodes
are going to need prefixing? We've got access to the INSN via
current_output_insn. So we can lookup attributes trivially.
This is a question, not a demand -- I'm looking for a solution that's
going to be reliable with minimal effort going forward.
jeff
next prev parent reply other threads:[~2023-12-20 18:22 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 4:22 [PATCH v2 0/9] RISC-V: Support XTheadVector extensions Jun Sha (Joshua)
2023-11-18 4:26 ` [PATCH v2 1/9] RISC-V: minimal support for xtheadvector Jun Sha (Joshua)
2023-11-18 10:06 ` Kito Cheng
2023-11-18 4:28 ` [PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector Jun Sha (Joshua)
2023-11-18 10:13 ` Kito Cheng
2023-11-18 4:29 ` [PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1) Jun Sha (Joshua)
2023-11-18 4:32 ` [PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2) Jun Sha (Joshua)
2023-11-18 4:34 ` [PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3) Jun Sha (Joshua)
2023-11-18 4:35 ` [PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4) Jun Sha (Joshua)
2023-11-18 4:37 ` [PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics Jun Sha (Joshua)
2023-11-18 4:39 ` [PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension Jun Sha (Joshua)
2023-12-20 12:20 ` [PATCH v3 0/6] RISC-V: Support " Jun Sha (Joshua)
2023-12-20 12:25 ` [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-20 18:14 ` Jeff Law
2023-12-27 2:46 ` 回复:[PATCH " joshua
2023-12-29 1:44 ` joshua
2023-12-20 12:27 ` [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns Jun Sha (Joshua)
2023-12-20 18:16 ` Jeff Law
2023-12-27 2:49 ` 回复:[PATCH " joshua
2023-12-28 15:50 ` Jeff Law
2023-12-20 12:30 ` [PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2023-12-20 12:32 ` [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-20 18:22 ` Jeff Law [this message]
2023-12-20 22:48 ` 钟居哲
2023-12-21 4:41 ` Jeff Law
2023-12-21 9:43 ` Kito Cheng
2023-12-25 6:25 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-25 6:37 ` juzhe.zhong
2023-12-25 7:08 ` 回复:[PATCH " joshua
2023-12-25 7:09 ` juzhe.zhong
2023-12-25 8:14 ` [PATCH " Jun Sha (Joshua)
2023-12-25 8:18 ` juzhe.zhong
2023-12-20 12:34 ` [PATCH v3 5/6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2023-12-20 14:00 ` 钟居哲
2023-12-20 14:24 ` 回复:[PATCH " joshua
2023-12-20 14:27 ` 钟居哲
2023-12-20 14:41 ` 回复:回复:[PATCH " joshua
2023-12-20 14:48 ` 回复:[PATCH " 钟居哲
2023-12-20 14:55 ` 钟居哲
2023-12-20 15:21 ` 回复:回复:[PATCH " joshua
2023-12-20 15:29 ` 回复:[PATCH " 钟居哲
2023-12-25 6:29 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:46 ` Jun Sha (Joshua)
2023-12-29 1:58 ` juzhe.zhong
2023-12-29 2:09 ` 回复:[PATCH " joshua
2023-12-29 2:11 ` Re:[PATCH " joshua
2023-12-29 2:14 ` 回复:[PATCH " juzhe.zhong
2023-12-29 2:17 ` Re:[PATCH " joshua
2023-12-29 2:22 ` juzhe.zhong
2023-12-29 2:25 ` Re:Re:[PATCH " joshua
2023-12-29 2:25 ` Re:[PATCH " juzhe.zhong
2023-12-29 2:30 ` joshua
2023-12-29 2:31 ` juzhe.zhong
2023-12-29 2:47 ` juzhe.zhong
2023-12-20 12:36 ` [PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2023-12-25 6:31 ` [PATCH v4 " Jun Sha (Joshua)
2023-12-29 1:49 ` Jun Sha (Joshua)
2023-12-20 23:04 ` [PATCH v3 0/6] RISC-V: Support XTheadVector extension 钟居哲
2023-12-22 3:33 ` 回复:[PATCH " joshua
2023-12-22 8:07 ` juzhe.zhong
2023-12-22 10:29 ` 回复:回复:[PATCH " joshua
2023-12-22 10:31 ` 回复:[PATCH " juzhe.zhong
2023-12-23 3:37 ` 回复:回复:[PATCH " joshua
2023-12-23 22:52 ` 回复:[PATCH " 钟居哲
2023-12-22 17:21 ` Jeff Law
2023-12-20 23:08 ` [PATCH " 钟居哲
2023-12-21 3:28 ` Jeff Law
2023-12-21 3:30 ` juzhe.zhong
2023-12-21 4:04 ` Jeff Law
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