From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 188B13858D32 for ; Wed, 19 Jul 2023 03:10:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 188B13858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353723.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J39MYY030313; Wed, 19 Jul 2023 03:10:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : subject : to : references : cc : from : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pp1; bh=VKBXqgg4D6W/ZrV5N6HG6ssxNGXTFdXadOgcPDi65kU=; b=L9mz0RieEcD+G7O/wOzuGU5aRxQMGpjkKDvCQ/bYZ65pka2Pm2OudE8ckVfSsa90EHe2 NxniTrfg41IHHdRZyHOjCXfRq+4lje2C+IaLP4s34HsNK7Trr8ZOJQEbJEPxXy/ZSgav Wgk59Fg34hif/S8xo2J8sxOwa63wZFgq1MoPAQQ926skGB8ebJAH7g1lnC2jCvXkJm1w FjYo18NyXFEyxr4J5Lai11HOZAqdW/BOJlGr6l9wnFp3G/N/gBYSBSFhHHZkbTAhxF5+ F1KW/NJ7Z0taUMR+EI1UriIgGmIbjxvnFXBU5sjLFZYplBGGaE/vtXHpLikuqpz+sARO Ag== Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rx6yngndv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 03:10:30 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 36INRrWn016880; Wed, 19 Jul 2023 03:10:30 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3rv5srrkvd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 03:10:30 +0000 Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 36J3ASFR41681360 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 19 Jul 2023 03:10:28 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4951320043; Wed, 19 Jul 2023 03:10:28 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 83F5720040; Wed, 19 Jul 2023 03:10:26 +0000 (GMT) Received: from [9.177.7.147] (unknown [9.177.7.147]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 19 Jul 2023 03:10:26 +0000 (GMT) Message-ID: Date: Wed, 19 Jul 2023 11:10:24 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: rs6000: Fix expected counts powerpc/p9-vec-length-full Content-Language: en-US To: Carl Love References: <0e14ae076c1bc2e9b1d749f1111a44646ef50cca.camel@us.ibm.com> <92bd2b3ab2f2a23041cd26103d23b05c8e15efea.camel@us.ibm.com> Cc: gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner From: "Kewen.Lin" In-Reply-To: <92bd2b3ab2f2a23041cd26103d23b05c8e15efea.camel@us.ibm.com> Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 2Ovcvr53WvzXh6ZPaV5KwRl7pFT_XSo_ X-Proofpoint-ORIG-GUID: 2Ovcvr53WvzXh6ZPaV5KwRl7pFT_XSo_ Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-18_19,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190027 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Carl, The issue was tracked by PR109971 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109971) and I think it had been resolved. btw, when the expected insn count changes, it does expose some issues but which can be either test or functionality issue, if it's taken as a test issue, it needs some justification why it changes like that and the change is expected. BR, Kewen on 2023/7/18 23:39, Carl Love wrote: > Ping > > On Thu, 2023-06-01 at 16:11 -0700, Carl Love wrote: >> GCC maintainers: >> >> The following patch updates the expected instruction counts in four >> tests. The counts in all of the tests changed with commit >> f574e2dfae79055f16d0c63cc12df24815d8ead6. >> >> The updated counts have been verified on both Power 9 and Power 10. >> >> Please let me know if this patch is acceptable for mainline. Thanks. >> >> Carl >> >> -------------------- >> rs6000: Fix expected counts powerpc/p9-vec-length-full tests >> >> The counts for instructions lxvl and stxvl in tests: >> >> p9-vec-length-full-1.c >> p9-vec-length-full-2.c >> p9-vec-length-full-6.c >> p9-vec-length-full-7.c >> >> changed with commit: >> >> commit f574e2dfae79055f16d0c63cc12df24815d8ead6 >> Author: Ju-Zhe Zhong >> Date: Thu May 25 22:42:35 2023 +0800 >> >> VECT: Add decrement IV iteration loop control by variable amount >> support >> >> This patch is supporting decrement IV by following the flow >> designed by >> Richard: >> ... >> >> The expected counts for lxvl changed from 20 to 40 and the counts for >> stxvl >> changed from 10 to 20 in the first three tests. The number of stxvl >> instructions changed from 12 to 20 in p9-vec-length-full-7.c. This >> patch updates the number of expected instructions in the four tests. >> >> The counts have been verified on Power 9 and Power 10. >> --- >> gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c | 4 ++-- >> gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c | 4 ++-- >> gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c | 4 ++-- >> gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c | 2 +- >> 4 files changed, 7 insertions(+), 7 deletions(-) >> >> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c >> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c >> index f01f1c54fa5..5e4f34421d3 100644 >> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c >> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c >> @@ -12,5 +12,5 @@ >> /* { dg-final { scan-assembler-not {\mstxv\M} } } */ >> /* { dg-final { scan-assembler-not {\mlxvx\M} } } */ >> /* { dg-final { scan-assembler-not {\mstxvx\M} } } */ >> -/* { dg-final { scan-assembler-times {\mlxvl\M} 20 } } */ >> -/* { dg-final { scan-assembler-times {\mstxvl\M} 10 } } */ >> +/* { dg-final { scan-assembler-times {\mlxvl\M} 40 } } */ >> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */ >> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c >> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c >> index f546e97fa7d..c7d927382c3 100644 >> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c >> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c >> @@ -12,5 +12,5 @@ >> /* { dg-final { scan-assembler-not {\mstxv\M} } } */ >> /* { dg-final { scan-assembler-not {\mlxvx\M} } } */ >> /* { dg-final { scan-assembler-not {\mstxvx\M} } } */ >> -/* { dg-final { scan-assembler-times {\mlxvl\M} 20 } } */ >> -/* { dg-final { scan-assembler-times {\mstxvl\M} 10 } } */ >> +/* { dg-final { scan-assembler-times {\mlxvl\M} 40 } } */ >> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */ >> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c >> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c >> index 65ddf2b098a..f3be3842c62 100644 >> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c >> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c >> @@ -11,5 +11,5 @@ >> /* It can use normal vector load for constant vector load. */ >> /* { dg-final { scan-assembler-times {\mstxvx?\M} 6 } } */ >> /* 64bit/32bit pairs won't use partial vectors. */ >> -/* { dg-final { scan-assembler-times {\mlxvl\M} 10 } } */ >> -/* { dg-final { scan-assembler-times {\mstxvl\M} 10 } } */ >> +/* { dg-final { scan-assembler-times {\mlxvl\M} 20 } } */ >> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */ >> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c >> b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c >> index e0e51d9a972..da086f1826a 100644 >> --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c >> +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c >> @@ -12,4 +12,4 @@ >> >> /* Each type has one stxvl excepting for int8 and uint8, that have >> two due to >> rtl pass bbro duplicating the block which has one stxvl. */ >> -/* { dg-final { scan-assembler-times {\mstxvl\M} 12 } } */ >> +/* { dg-final { scan-assembler-times {\mstxvl\M} 20 } } */ >