From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 115385 invoked by alias); 29 Jun 2017 13:56:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 115358 invoked by uid 89); 29 Jun 2017 13:56:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,RCVD_IN_SORBS_SPAM,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=STRONG X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Jun 2017 13:56:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7D04344; Thu, 29 Jun 2017 06:56:00 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32DDF3F557; Thu, 29 Jun 2017 06:56:00 -0700 (PDT) Subject: [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture From: Thomas Preudhomme To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <9ab04ae2-a65a-11cc-dfaf-1a20a8137e4e@foss.arm.com> Message-ID: Date: Thu, 29 Jun 2017 13:56:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <9ab04ae2-a65a-11cc-dfaf-1a20a8137e4e@foss.arm.com> Content-Type: multipart/mixed; boundary="------------05217AB187EC388956E86BA9" X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg02274.txt.bz2 This is a multi-part message in MIME format. --------------05217AB187EC388956E86BA9 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1613 Hi, This patch adds support for ARMv8-R architecture [1] which was recently announced. User level instructions for ARMv8-R are the same as those in ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same features as ARMv8-A in ARM backend. [1] https://developer.arm.com/products/architecture/r-profile/docs/ddi0568/latest/arm-architecture-reference-manual-supplement-armv8-for-the-armv8-r-aarch32-architecture-profile ChangeLog entries are as follow: *** gcc/ChangeLog *** 2017-01-31 Thomas Preud'homme * config/arm/arm-cpus.in (armv8-r, armv8-r+rcr): Add new entry. * config/arm/arm-cpu-cdata.h: Regenerate. * config/arm/arm-cpu-data.h: Regenerate. * config/arm/arm-isa.h (ISA_ARMv8r): Define macro. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.h (enum base_architecture): Add BASE_ARCH_8R enumerator. * config/arm/bpabi.h (BE8_LINK_SPEC): Add entry for ARMv8-R and ARMv8-R with CRC extensions. * doc/invoke.texi: Mention -march=armv8-r and -march=armv8-r+crc options. Document meaning of -march=armv8-r+rcr. *** gcc/testsuite/ChangeLog *** 2017-01-31 Thomas Preud'homme * lib/target-supports.exp: Generate check_effective_target_arm_arch_v8r_ok, add_options_for_arm_arch_v8r and check_effective_target_arm_arch_v8r_multilib. *** libgcc/ChangeLog *** 2017-01-31 Thomas Preud'homme * config/arm/lib1funcs.S: Defined __ARM_ARCH__ to 8 for ARMv8-R. Tested by building an arm-none-eabi GCC cross-compiler targetting ARMv8-R. Is this ok for stage1? Best regards, Thomas --------------05217AB187EC388956E86BA9 Content-Type: text/x-patch; name="2_add_armv8r_support.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="2_add_armv8r_support.patch" Content-length: 6987 diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index b3888120daa8494eb41bde0368122ad2f06d81af..0a122f5febaaceeeb5a405cb5a64e1edd9b044f3 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -1041,6 +1041,20 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = }, }, { + "armv8-r", + { + ISA_ARMv8r, + isa_nobit + }, + }, + { + "armv8-r+crc", + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + }, + { "iwmmxt", { ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index d6200f9bdc09a9d0c973853b0152a2800eaf2fe5..48c1d88032c1c5dc7c6cba71511f79fe9f2533ea 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -1478,6 +1478,26 @@ static const struct processors all_architectures[] = NULL }, { + "armv8-r", TARGET_CPU_cortexr4, + (TF_CO_PROC), + "8R", BASE_ARCH_8R, + { + ISA_ARMv8r, + isa_nobit + }, + NULL + }, + { + "armv8-r+crc", TARGET_CPU_cortexr4, + (TF_CO_PROC), + "8R", BASE_ARCH_8R, + { + ISA_ARMv8r,isa_bit_crc32, + isa_nobit + }, + NULL + }, + { "iwmmxt", TARGET_CPU_iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), "5TE", BASE_ARCH_5TE, diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index fc5d935182ba70de5ab2aefeec492318f42e95c5..be1f0ca4e38ae76683b77d8c3b79a066e62325d7 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -287,6 +287,20 @@ begin arch armv8-m.main+dsp isa ARMv8m_main bit_ARMv7em end arch armv8-m.main+dsp +begin arch armv8-r + tune for cortex-r4 + tune flags CO_PROC + base 8R + isa ARMv8r +end arch armv8-r + +begin arch armv8-r+crc + tune for cortex-r4 + tune flags CO_PROC + base 8R + isa ARMv8r bit_crc32 +end arch armv8-r+crc + begin arch iwmmxt tune for iwmmxt tune flags LDSCHED STRONG XSCALE diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index 6050bca95587f68a3671dd2144cf845b83da3692..24ec398b346f8effb346235d6f3ab20eb6f70e0f 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -125,6 +125,7 @@ enum isa_feature #define ISA_ARMv8_2a ISA_ARMv8_1a, isa_bit_ARMv8_2 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse +#define ISA_ARMv8r ISA_ARMv8a /* List of all FPU bits to strip out if -mfpu is used to override the default. isa_bit_fp16 is deliberately missing from this list. */ diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index cbcd85d9906d1fc797ab33b3d61969f32b9cc566..7bab5de5a39e9192c97851929b83175648158cdf 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -461,10 +461,16 @@ EnumValue Enum(arm_arch) String(armv8-m.main+dsp) Value(33) EnumValue -Enum(arm_arch) String(iwmmxt) Value(34) +Enum(arm_arch) String(armv8-r) Value(34) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(35) +Enum(arm_arch) String(armv8-r+crc) Value(35) + +EnumValue +Enum(arm_arch) String(iwmmxt) Value(36) + +EnumValue +Enum(arm_arch) String(iwmmxt2) Value(37) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index e95eda358a54ca0804cfbb9acc0801835c3d7bfb..0b231214cd49b4217a3b9af05acb25b6e73a287b 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -373,7 +373,8 @@ enum base_architecture BASE_ARCH_7EM = 7, BASE_ARCH_8A = 8, BASE_ARCH_8M_BASE = 8, - BASE_ARCH_8M_MAIN = 8 + BASE_ARCH_8M_MAIN = 8, + BASE_ARCH_8R = 8 }; /* The major revision number of the ARM Architecture implemented by the target. */ diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index 56a4a4750428fa76cd5305b71a01d7ff7aa4256f..c394ac805c7577113ed72b31a06ff93dc7f5f490 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -99,6 +99,8 @@ |march=armv8-m.base|mcpu=cortex-m23 \ |march=armv8-m.main \ |march=armv8-m.main+dsp|mcpu=cortex-m33 \ + |march-armv8-r \ + |march-armv8-r+crc \ :%{!r:--be8}}}" #else #define BE8_LINK_SPEC \ @@ -139,6 +141,8 @@ |march=armv8-m.base|mcpu=cortex-m23 \ |march=armv8-m.main \ |march=armv8-m.main+dsp|mcpu=cortex-m33 \ + |march=armv8-r \ + |march=armv8-r+crc \ :%{!r:--be8}}}" #endif diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c205023d59cf9bb495c58a3a08461736cce1ad66..9ea580626749dc9d27bb72d56bbbef6a474a5055 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15147,7 +15147,8 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @samp{armv7}, @samp{armv7-a}, @samp{armv7-m}, @samp{armv7-r}, @samp{armv7e-m}, @samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a}, @samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main}, -@samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}. +@samp{armv8-m.main+dsp}, @samp{armv8-r}, , @samp{armv8-r+crc}, +@samp{iwmmxt}, @samp{iwmmxt2}. Architecture revisions older than @samp{armv4t} are deprecated. @@ -15161,6 +15162,8 @@ compatibility. extensions. @option{-march=armv8-a+crc} enables code generation for the ARMv8-A +architecture together with the optional CRC32 extensions. Similarly, +@option{-march=armv8-r+crc} enables code generation for the ARMv8-R architecture together with the optional CRC32 extensions. @option{-march=armv8.1-a} enables compiler support for the ARMv8.1-A diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 95a1c500c28a0612835436787a55c51bb1866fea..92cafc52b201d610fe30f57e020b29a736c01a09 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3781,7 +3781,8 @@ foreach { armfunc armflag armdef } { v8_1a "-march=armv8.1a" __ARM_ARCH_8A__ v8_2a "-march=armv8.2a" __ARM_ARCH_8A__ v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft" __ARM_ARCH_8M_BASE__ - v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } { + v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__ + v8r "-march=armv8-r" __ARM_ARCH_8R__ } { eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] { proc check_effective_target_arm_arch_FUNC_ok { } { if { [ string match "*-marm*" "FLAG" ] && diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 89ebebcd68a790c6bec140e4a8bd5a3b44dce291..8d8c3cead5f77f6dfeb2887e68483119ee3a400a 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -109,7 +109,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #endif #if defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH_8M_BASE__) \ - || defined(__ARM_ARCH_8M_MAIN__) + || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8R__) # define __ARM_ARCH__ 8 #endif --------------05217AB187EC388956E86BA9--