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Sat, 10 Jun 2023 10:54:03 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id d36-20020a634f24000000b0050fa6546a45sm4776696pgb.6.2023.06.10.10.54.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Jun 2023 10:54:03 -0700 (PDT) Message-ID: Date: Sat, 10 Jun 2023 11:54:02 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH 11/11] riscv: thead: Add support for the XTheadFMemIdx ISA extension Content-Language: en-US To: Christoph Muellner , gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu References: <20230428062314.2995571-1-christoph.muellner@vrull.eu> <20230428062314.2995571-2-christoph.muellner@vrull.eu> From: Jeff Law In-Reply-To: <20230428062314.2995571-2-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_MANYTO,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/28/23 00:23, Christoph Muellner wrote: > From: Christoph Müllner > > The XTheadFMemIdx ISA extension provides additional load and store > instructions for floating-point registers with new addressing modes. > > The following memory accesses types are supported: > * ftype = [w,d] (single-precision, double-precision) > > The following addressing modes are supported: > * register offset with additional immediate offset (4 instructions): > flr, fsr > * zero-extended register offset with additional immediate offset > (4 instructions): flur, fsur > > These addressing modes are also part of the similar XTheadMemIdx > ISA extension support, whose code is reused and extended to support > floating-point registers. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_index_reg_class): Also allow > for XTheadFMemIdx. > (riscv_regno_ok_for_index_p): Likewise. > * config/riscv/thead-peephole.md (TARGET_64BIT): > Generalize peepholes for XTheadFMemIdx. > * config/riscv/thead.cc (is_fmemidx_mode): New function. > (th_memidx_classify_address_index): Add support for > XTheadFMemIdx. > (th_fmemidx_output_index): New function. > (th_output_move): Add support for XTheadFMemIdx. > * config/riscv/thead.md (*th_fmemidx_movsf_hardfloat): New INSN. > (*th_fmemidx_movdf_hardfloat_rv64): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xtheadmemidx-helpers.h: Add helpers for > XTheadMemFIdx. > * gcc.target/riscv/xtheadfmemidx-index-update.c: New test. > * gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c: New test. > * gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c: New test. > * gcc.target/riscv/xtheadfmemidx-index.c: New test. > * gcc.target/riscv/xtheadfmemidx-uindex-update.c: New test. > * gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c: New test. > * gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c: New test. > * gcc.target/riscv/xtheadfmemidx-uindex.c: New test. Same core questions/comments as in patch #10 of this series. jeff