From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id E96023858403 for ; Thu, 18 Aug 2022 11:37:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E96023858403 Received: from [IPv6:240e:358:11b1:ee00:dc73:854d:832e:3] (unknown [IPv6:240e:358:11b1:ee00:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 73DAB66996; Thu, 18 Aug 2022 07:37:41 -0400 (EDT) Message-ID: Subject: Re: [PATCH v1] LoongArch: Add support code model extreme. From: Xi Ruoyao To: Lulu Cheng , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn Date: Thu, 18 Aug 2022 19:37:33 +0800 In-Reply-To: <20220818100112.142343-1-chenglulu@loongson.cn> References: <20220818100112.142343-1-chenglulu@loongson.cn> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.45.2 MIME-Version: 1.0 X-Spam-Status: No, score=0.8 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Aug 2022 11:37:49 -0000 On Thu, 2022-08-18 at 18:01 +0800, Lulu Cheng wrote: > Use five instructions to calculate a signed 64-bit offset relative to the= pc. > gcc/ChangeLog: >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* config/loongarch/loonga= rch-opts.cc: Allow cmodel to be extreme. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* config/loongarch/loonga= rch.cc (loongarch_call_tls_get_addr): > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0Add extreme support for T= LS GD and LD types. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(loongarch_legitimize_tls= _address): Add extreme support for TLS LE > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0and IE. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(loongarch_split_symbol):= When compiling with -mcmodel=3Dextreme, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0the symbol address will b= e obtained through five instructions. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(loongarch_print_operand_= reloc): Add support. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(loongarch_print_operand)= : Add support. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(loongarch_print_operand_= address): Add support. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0(loongarch_option_overrid= e_internal): Set '-mcmodel=3Dlarge' option Should be "-mcmodel=3Dextreme"? > + if (!TARGET_EXPLICIT_RELOCS) > + error ("code model %qs not support %s mode", > + "extreme", "-mno-explicit-relocs"); Would ("code model %qs needs %s", "extreme", "-mexplicit-relocs") be better? > + if (opts->x_flag_plt) > + error ("code model %qs and %qs not support %s mode", > + "tiny-static", "extreme", "plt"); I think we can ignore the effect of -fplt if code model is extreme, instead of forcing everyone to explicitly add -fno-plt. The "large" code model of x86_64 also does not limit the address range and it always avoids PLT (even if someone adds "-fplt" explicitly). --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University